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authorBen Skeggs <skeggsb@gmail.com>2009-01-12 15:06:15 +1000
committerBen Skeggs <skeggsb@gmail.com>2009-01-12 16:59:34 +1000
commit515c3d9bc15f66e5ffea87efee52fc27b4b558db (patch)
treeb000c364ac41763628d55bd7a100451ce27392f0 /src/gallium/drivers/nv50
parented8f0b753b42cc9c9519b8cdc6c40729efb7243a (diff)
nv50: fix a typo and a thinko
Diffstat (limited to 'src/gallium/drivers/nv50')
-rw-r--r--src/gallium/drivers/nv50/nv50_miptree.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c b/src/gallium/drivers/nv50/nv50_miptree.c
index 415080bc98d..430e75a4116 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -124,7 +124,7 @@ nv50_miptree_sync(struct pipe_screen *pscreen, struct nv50_miptree *mt,
struct pipe_surface *dst, *src;
unsigned face = 0, zslice = 0;
- if (!lvl->image_dirty_cpu & (1 << image))
+ if (!(lvl->image_dirty_cpu & (1 << image)))
return;
if (mt->base.target == PIPE_TEXTURE_CUBE)
@@ -138,14 +138,15 @@ nv50_miptree_sync(struct pipe_screen *pscreen, struct nv50_miptree *mt,
*/
lvl->image_dirty_cpu &= ~(1 << image);
- dst = pscreen->get_tex_surface(pscreen, &mt->base, face, level, zslice,
- PIPE_BUFFER_USAGE_GPU_WRITE);
/* Pretend we're doing CPU access so we get the backing pipe_surface
* and not a view into the larger miptree.
*/
src = pscreen->get_tex_surface(pscreen, &mt->base, face, level, zslice,
PIPE_BUFFER_USAGE_CPU_READ);
+ dst = pscreen->get_tex_surface(pscreen, &mt->base, face, level, zslice,
+ PIPE_BUFFER_USAGE_GPU_WRITE);
+
nvws->surface_copy(nvws, dst, 0, 0, src, 0, 0, dst->width, dst->height);
pscreen->tex_surface_release(pscreen, &dst);