nv30, nv40: move last files to nvfx/ and rm -rf nv30 nv40

This is the last nvfx unification patch.

nv[34]0_fragtex.c are moved to the common directory
nv[34]0_shader.h are renamed to nv[34]0_vertprog.h and moved to
the common directory

The separate nv30 and nv40 directories are removed from the build
system

3 files changed, 0 insertions, 363 deletions

diff --git a/src/gallium/drivers/nv40/Makefile b/src/gallium/drivers/nv40/Makefile
deleted file mode 100644
index 8b69f9432d1..00000000000
--- a/src/gallium/drivers/nv40/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-TOP = ../../../..
-include $(TOP)/configs/current
-
-LIBNAME = nv40
-
-C_SOURCES = \
-	nv40_fragtex.c
-
-LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/nvfx
-
-include ../../Makefile.template
diff --git a/src/gallium/drivers/nv40/nv40_fragtex.c b/src/gallium/drivers/nv40/nv40_fragtex.c
deleted file mode 100644
index 5889b5e40d5..00000000000
--- a/src/gallium/drivers/nv40/nv40_fragtex.c
+++ /dev/null
@@ -1,174 +0,0 @@
-#include "util/u_format.h"
-#include "nvfx_context.h"
-#include "nvfx_tex.h"
-
-void
-nv40_sampler_state_init(struct pipe_context *pipe,
-			  struct nvfx_sampler_state *ps,
-			  const struct pipe_sampler_state *cso)
-{
-	if (cso->max_anisotropy >= 2) {
-		/* no idea, binary driver sets it, works without it.. meh.. */
-		ps->wrap |= (1 << 5);
-
-		if (cso->max_anisotropy >= 16) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
-		} else
-		if (cso->max_anisotropy >= 12) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
-		} else
-		if (cso->max_anisotropy >= 10) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
-		} else
-		if (cso->max_anisotropy >= 8) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
-		} else
-		if (cso->max_anisotropy >= 6) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
-		} else
-		if (cso->max_anisotropy >= 4) {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
-		} else {
-			ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
-		}
-	}
-
-	{
-		float limit;
-
-		limit = CLAMP(cso->lod_bias, -16.0, 15.0);
-		ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
-
-		limit = CLAMP(cso->max_lod, 0.0, 15.0);
-		ps->en |= (int)(limit * 256.0) << 7;
-
-		limit = CLAMP(cso->min_lod, 0.0, 15.0);
-		ps->en |= (int)(limit * 256.0) << 19;
-	}
-}
-
-#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sx,sy,sz,sw)            \
-{                                                                              \
-  TRUE,                                                                        \
-  PIPE_FORMAT_##m,                                                             \
-  NV40TCL_TEX_FORMAT_FORMAT_##tf,                                              \
-  (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |         \
-   NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |         \
-   NV34TCL_TX_SWIZZLE_S1_X_##ts1x | NV34TCL_TX_SWIZZLE_S1_Y_##ts1y |         \
-   NV34TCL_TX_SWIZZLE_S1_Z_##ts1z | NV34TCL_TX_SWIZZLE_S1_W_##ts1w),         \
-  ((NV34TCL_TX_FILTER_SIGNED_RED*sx) | (NV34TCL_TX_FILTER_SIGNED_GREEN*sy) |       \
-   (NV34TCL_TX_FILTER_SIGNED_BLUE*sz) | (NV34TCL_TX_FILTER_SIGNED_ALPHA*sw))       \
-}
-
-struct nv40_texture_format {
-	boolean defined;
-	uint	pipe;
-	int     format;
-	int     swizzle;
-	int     sign;
-};
-
-static struct nv40_texture_format
-nv40_texture_formats[] = {
-	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B4G4R4A4_UNORM, A4R4G4B4,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B5G6R5_UNORM  , R5G6B5  ,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(L8_UNORM      , L8      ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(A8_UNORM      , L8      , ZERO, ZERO, ZERO,   S1, X, X, X, X, 0, 0, 0, 0),
-	_(R16_SNORM     , A16     , ZERO, ZERO,   S1,  ONE, X, X, X, Y, 1, 1, 1, 1),
-	_(I8_UNORM      , L8      ,   S1,   S1,   S1,   S1, X, X, X, X, 0, 0, 0, 0),
-	_(L8A8_UNORM    , A8L8    ,   S1,   S1,   S1,   S1, X, X, X, Y, 0, 0, 0, 0),
-	_(Z16_UNORM     , Z16     ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(S8Z24_UNORM   , Z24     ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(DXT1_RGB      , DXT1    ,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT1_RGBA     , DXT1    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT3_RGBA     , DXT3    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT5_RGBA     , DXT5    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	{},
-};
-
-static struct nv40_texture_format *
-nv40_fragtex_format(uint pipe_format)
-{
-	struct nv40_texture_format *tf = nv40_texture_formats;
-
-	while (tf->defined) {
-		if (tf->pipe == pipe_format)
-			return tf;
-		tf++;
-	}
-
-	NOUVEAU_ERR("unknown texture format %s\n", util_format_name(pipe_format));
-	return NULL;
-}
-
-
-struct nouveau_stateobj *
-nv40_fragtex_build(struct nvfx_context *nvfx, int unit)
-{
-	struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
-	struct nvfx_miptree *nv40mt = nvfx->tex_miptree[unit];
-	struct nouveau_bo *bo = nouveau_bo(nv40mt->buffer);
-	struct pipe_texture *pt = &nv40mt->base;
-	struct nv40_texture_format *tf;
-	struct nouveau_stateobj *so;
-	uint32_t txf, txs, txp;
-	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
-
-	tf = nv40_fragtex_format(pt->format);
-	if (!tf)
-		assert(0);
-
-	txf  = ps->fmt;
-	txf |= tf->format | 0x8000;
-	txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
-
-	if (1) /* XXX */
-		txf |= NV34TCL_TX_FORMAT_NO_BORDER;
-
-	switch (pt->target) {
-	case PIPE_TEXTURE_CUBE:
-		txf |= NV34TCL_TX_FORMAT_CUBIC;
-		/* fall-through */
-	case PIPE_TEXTURE_2D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
-		break;
-	case PIPE_TEXTURE_3D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_3D;
-		break;
-	case PIPE_TEXTURE_1D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_1D;
-		break;
-	default:
-		NOUVEAU_ERR("Unknown target %d\n", pt->target);
-		return NULL;
-	}
-
-	if (!(pt->tex_usage & NOUVEAU_TEXTURE_USAGE_LINEAR)) {
-		txp = 0;
-	} else {
-		txp  = nv40mt->level[0].pitch;
-		txf |= NV40TCL_TEX_FORMAT_LINEAR;
-	}
-
-	txs = tf->swizzle;
-
-	so = so_new(2, 9, 2);
-	so_method(so, nvfx->screen->eng3d, NV34TCL_TX_OFFSET(unit), 8);
-	so_reloc (so, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
-	so_reloc (so, bo, txf, tex_flags | NOUVEAU_BO_OR,
-		      NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
-	so_data  (so, ps->wrap);
-	so_data  (so, NV40TCL_TEX_ENABLE_ENABLE | ps->en);
-	so_data  (so, txs);
-	so_data  (so, ps->filt | tf->sign | 0x2000 /*voodoo*/);
-	so_data  (so, (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) |
-		       pt->height0);
-	so_data  (so, ps->bcol);
-	so_method(so, nvfx->screen->eng3d, NV40TCL_TEX_SIZE1(unit), 1);
-	so_data  (so, (pt->depth0 << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp);
-
-	return so;
-}
diff --git a/src/gallium/drivers/nv40/nv40_shader.h b/src/gallium/drivers/nv40/nv40_shader.h
deleted file mode 100644
index 8d28137e9de..00000000000
--- a/src/gallium/drivers/nv40/nv40_shader.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef __NV40_SHADER_H__
-#define __NV40_SHADER_H__
-
-/* Vertex programs instruction set
- *
- * The NV40 instruction set is very similar to NV30.  Most fields are in
- * a slightly different position in the instruction however.
- *
- * Merged instructions
- *     In some cases it is possible to put two instructions into one opcode
- *     slot.  The rules for when this is OK is not entirely clear to me yet.
- *
- *     There are separate writemasks and dest temp register fields for each
- *     grouping of instructions.  There is however only one field with the
- *     ID of a result register.  Writing to temp/result regs is selected by
- *     setting VEC_RESULT/SCA_RESULT.
- *
- * Temporary registers
- *     The source/dest temp register fields have been extended by 1 bit, to
- *     give a total of 32 temporary registers.
- *
- * Relative Addressing
- *     NV40 can use an address register to index into vertex attribute regs.
- *     This is done by putting the offset value into INPUT_SRC and setting
- *     the INDEX_INPUT flag.
- *
- * Conditional execution (see NV_vertex_program{2,3} for details)
- *     There is a second condition code register on NV40, it's use is enabled
- *     by setting the COND_REG_SELECT_1 flag.
- *
- * Texture lookup
- *     TODO
- */
-
-/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
-#define NV40_VP_INST_VEC_RESULT                                        (1 << 30)
-/* uncertain.. */
-#define NV40_VP_INST_COND_UPDATE_ENABLE                        ((1 << 14)|1<<29)
-/* use address reg as index into attribs */
-#define NV40_VP_INST_INDEX_INPUT                                       (1 << 27)
-#define NV40_VP_INST_COND_REG_SELECT_1                                 (1 << 25)
-#define NV40_VP_INST_ADDR_REG_SELECT_1                                 (1 << 24)
-#define NV40_VP_INST_SRC2_ABS                                          (1 << 23)
-#define NV40_VP_INST_SRC1_ABS                                          (1 << 22)
-#define NV40_VP_INST_SRC0_ABS                                          (1 << 21)
-#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT                                      15
-#define NV40_VP_INST_VEC_DEST_TEMP_MASK                             (0x1F << 15)
-#define NV40_VP_INST_COND_TEST_ENABLE                                  (1 << 13)
-#define NV40_VP_INST_COND_SHIFT                                               10
-#define NV40_VP_INST_COND_MASK                                       (0x7 << 10)
-#define NV40_VP_INST_COND_SWZ_X_SHIFT                                          8
-#define NV40_VP_INST_COND_SWZ_X_MASK                                    (3 << 8)
-#define NV40_VP_INST_COND_SWZ_Y_SHIFT                                          6
-#define NV40_VP_INST_COND_SWZ_Y_MASK                                    (3 << 6)
-#define NV40_VP_INST_COND_SWZ_Z_SHIFT                                          4
-#define NV40_VP_INST_COND_SWZ_Z_MASK                                    (3 << 4)
-#define NV40_VP_INST_COND_SWZ_W_SHIFT                                          2
-#define NV40_VP_INST_COND_SWZ_W_MASK                                    (3 << 2)
-#define NV40_VP_INST_COND_SWZ_ALL_SHIFT                                        2
-#define NV40_VP_INST_COND_SWZ_ALL_MASK                               (0xFF << 2)
-#define NV40_VP_INST_ADDR_SWZ_SHIFT                                            0
-#define NV40_VP_INST_ADDR_SWZ_MASK                                   (0x03 << 0)
-#define NV40_VP_INST0_KNOWN ( \
-                NV40_VP_INST_INDEX_INPUT | \
-                NV40_VP_INST_COND_REG_SELECT_1 | \
-                NV40_VP_INST_ADDR_REG_SELECT_1 | \
-                NV40_VP_INST_SRC2_ABS | \
-                NV40_VP_INST_SRC1_ABS | \
-                NV40_VP_INST_SRC0_ABS | \
-                NV40_VP_INST_VEC_DEST_TEMP_MASK | \
-                NV40_VP_INST_COND_TEST_ENABLE | \
-                NV40_VP_INST_COND_MASK | \
-                NV40_VP_INST_COND_SWZ_ALL_MASK | \
-                NV40_VP_INST_ADDR_SWZ_MASK)
-
-/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
-#define NV40_VP_INST_VEC_OPCODE_SHIFT                                         22
-#define NV40_VP_INST_VEC_OPCODE_MASK                                (0x1F << 22)
-#define NV40_VP_INST_SCA_OPCODE_SHIFT                                         27
-#define NV40_VP_INST_SCA_OPCODE_MASK                                (0x1F << 27)
-#define NV40_VP_INST_CONST_SRC_SHIFT                                          12
-#define NV40_VP_INST_CONST_SRC_MASK                                 (0xFF << 12)
-#define NV40_VP_INST_INPUT_SRC_SHIFT                                           8
-#define NV40_VP_INST_INPUT_SRC_MASK                                  (0x0F << 8)
-#define NV40_VP_INST_SRC0H_SHIFT                                               0
-#define NV40_VP_INST_SRC0H_MASK                                      (0xFF << 0)
-#define NV40_VP_INST1_KNOWN ( \
-                NV40_VP_INST_VEC_OPCODE_MASK | \
-                NV40_VP_INST_SCA_OPCODE_MASK | \
-                NV40_VP_INST_CONST_SRC_MASK  | \
-                NV40_VP_INST_INPUT_SRC_MASK  | \
-                NV40_VP_INST_SRC0H_MASK \
-                )
-
-/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
-#define NV40_VP_INST_SRC0L_SHIFT                                              23
-#define NV40_VP_INST_SRC0L_MASK                                    (0x1FF << 23)
-#define NV40_VP_INST_SRC1_SHIFT                                                6
-#define NV40_VP_INST_SRC1_MASK                                    (0x1FFFF << 6)
-#define NV40_VP_INST_SRC2H_SHIFT                                               0
-#define NV40_VP_INST_SRC2H_MASK                                      (0x3F << 0)
-#define NV40_VP_INST_IADDRH_SHIFT                                              0
-#define NV40_VP_INST_IADDRH_MASK                                     (0x1F << 0)
-
-/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
-#define NV40_VP_INST_IADDRL_SHIFT                                             29
-#define NV40_VP_INST_IADDRL_MASK                                       (7 << 29)
-#define NV40_VP_INST_SRC2L_SHIFT                                              21
-#define NV40_VP_INST_SRC2L_MASK                                    (0x7FF << 21)
-#define NV40_VP_INST_SCA_WRITEMASK_SHIFT                                      17
-#define NV40_VP_INST_SCA_WRITEMASK_MASK                              (0xF << 17)
-#    define NV40_VP_INST_SCA_WRITEMASK_X                               (1 << 20)
-#    define NV40_VP_INST_SCA_WRITEMASK_Y                               (1 << 19)
-#    define NV40_VP_INST_SCA_WRITEMASK_Z                               (1 << 18)
-#    define NV40_VP_INST_SCA_WRITEMASK_W                               (1 << 17)
-#define NV40_VP_INST_VEC_WRITEMASK_SHIFT                                      13
-#define NV40_VP_INST_VEC_WRITEMASK_MASK                              (0xF << 13)
-#    define NV40_VP_INST_VEC_WRITEMASK_X                               (1 << 16)
-#    define NV40_VP_INST_VEC_WRITEMASK_Y                               (1 << 15)
-#    define NV40_VP_INST_VEC_WRITEMASK_Z                               (1 << 14)
-#    define NV40_VP_INST_VEC_WRITEMASK_W                               (1 << 13)
-#define NV40_VP_INST_SCA_RESULT                                        (1 << 12)
-#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT                                       7
-#define NV40_VP_INST_SCA_DEST_TEMP_MASK                              (0x1F << 7)
-#define NV40_VP_INST_DEST_SHIFT                                                2
-#define NV40_VP_INST_DEST_MASK                                         (31 << 2)
-#    define NV40_VP_INST_DEST_POS                                              0
-#    define NV40_VP_INST_DEST_COL0                                             1
-#    define NV40_VP_INST_DEST_COL1                                             2
-#    define NV40_VP_INST_DEST_BFC0                                             3
-#    define NV40_VP_INST_DEST_BFC1                                             4
-#    define NV40_VP_INST_DEST_FOGC                                             5
-#    define NV40_VP_INST_DEST_PSZ                                              6
-#    define NV40_VP_INST_DEST_TC0                                              7
-#    define NV40_VP_INST_DEST_TC(n)                                        (7+n)
-#    define NV40_VP_INST_DEST_TEMP                                          0x1F
-#define NV40_VP_INST_INDEX_CONST                                        (1 << 1)
-#define NV40_VP_INST3_KNOWN ( \
-                NV40_VP_INST_SRC2L_MASK |\
-                NV40_VP_INST_SCA_WRITEMASK_MASK |\
-                NV40_VP_INST_VEC_WRITEMASK_MASK |\
-                NV40_VP_INST_SCA_DEST_TEMP_MASK |\
-                NV40_VP_INST_DEST_MASK |\
-                NV40_VP_INST_INDEX_CONST)
-
-/* Useful to split the source selection regs into their pieces */
-#define NV40_VP_SRC0_HIGH_SHIFT                                                9
-#define NV40_VP_SRC0_HIGH_MASK                                        0x0001FE00
-#define NV40_VP_SRC0_LOW_MASK                                         0x000001FF
-#define NV40_VP_SRC2_HIGH_SHIFT                                               11
-#define NV40_VP_SRC2_HIGH_MASK                                        0x0001F800
-#define NV40_VP_SRC2_LOW_MASK                                         0x000007FF
-
-/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
-#define NV40_VP_SRC_NEGATE                                             (1 << 16)
-#define NV40_VP_SRC_SWZ_X_SHIFT                                               14
-#define NV40_VP_SRC_SWZ_X_MASK                                         (3 << 14)
-#define NV40_VP_SRC_SWZ_Y_SHIFT                                               12
-#define NV40_VP_SRC_SWZ_Y_MASK                                         (3 << 12)
-#define NV40_VP_SRC_SWZ_Z_SHIFT                                               10
-#define NV40_VP_SRC_SWZ_Z_MASK                                         (3 << 10)
-#define NV40_VP_SRC_SWZ_W_SHIFT                                                8
-#define NV40_VP_SRC_SWZ_W_MASK                                          (3 << 8)
-#define NV40_VP_SRC_SWZ_ALL_SHIFT                                              8
-#define NV40_VP_SRC_SWZ_ALL_MASK                                     (0xFF << 8)
-#define NV40_VP_SRC_TEMP_SRC_SHIFT                                             2
-#define NV40_VP_SRC_TEMP_SRC_MASK                                    (0x1F << 2)
-#define NV40_VP_SRC_REG_TYPE_SHIFT                                             0
-#define NV40_VP_SRC_REG_TYPE_MASK                                       (3 << 0)
-#    define NV40_VP_SRC_REG_TYPE_UNK0                                          0
-#    define NV40_VP_SRC_REG_TYPE_TEMP                                          1
-#    define NV40_VP_SRC_REG_TYPE_INPUT                                         2
-#    define NV40_VP_SRC_REG_TYPE_CONST                                         3
-
-#include "nvfx_shader.h"
-
-#endif
-