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authorSamuel Pitoiset <[email protected]>2015-09-28 17:29:37 +0200
committerSamuel Pitoiset <[email protected]>2015-10-16 21:57:44 +0200
commit8cd4b8478aac56f0ed516c4ff13f8af012fb8eaa (patch)
treed489d95933693647981411b0d9b055a960de6664 /src/gallium/drivers/nouveau
parentcef22f3490f9809a6e77949f73448efac23be7ee (diff)
nvc0: allow only one active query for the MP counters group
Because we can't expose the number of hardware counters needed for each different query, we don't want to allow more than one active query simultaneously to avoid failure when the maximum number of counters is reached. Note that these groups of GPU counters are currently only used by AMD_performance_monitor. Like for Kepler, this limits the maximum number of active queries to 1 on Fermi. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau')
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_query.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index f8d4ba16237..c81b85a1804 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
@@ -371,22 +371,20 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen *pscreen,
info->name = "MP counters";
info->type = PIPE_DRIVER_QUERY_GROUP_TYPE_GPU;
+ /* Because we can't expose the number of hardware counters needed for
+ * each different query, we don't want to allow more than one active
+ * query simultaneously to avoid failure when the maximum number of
+ * counters is reached. Note that these groups of GPU counters are
+ * currently only used by AMD_performance_monitor.
+ */
+ info->max_active_queries = 1;
+
if (screen->base.class_3d == NVE4_3D_CLASS) {
info->num_queries = NVE4_HW_SM_QUERY_COUNT;
-
- /* On NVE4+, each multiprocessor have 8 hardware counters separated
- * in two distinct domains, but we allow only one active query
- * simultaneously because some of them use more than one hardware
- * counter and this will result in an undefined behaviour. */
- info->max_active_queries = 1; /* TODO: handle multiple hw counters */
- return 1;
+ return 1;
} else
if (screen->base.class_3d < NVE4_3D_CLASS) {
info->num_queries = NVC0_HW_SM_QUERY_COUNT;
-
- /* On NVC0:NVE4, each multiprocessor have 8 hardware counters
- * in a single domain. */
- info->max_active_queries = 8;
return 1;
}
}