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authorLyude <[email protected]>2017-03-15 17:15:03 -0400
committerIlia Mirkin <[email protected]>2017-03-31 21:41:36 -0400
commit31970ab9a6526177c585cb92693178b7d5408916 (patch)
treed9046ceb4269896877f79a0fea38515a1665d338 /src/gallium/drivers/nouveau
parent82e0c5f484828565a566bd7fb5bcb67334bbee5e (diff)
nvc0: Add support for NV_fill_rectangle for the GM200+
This enables support for the GL_NV_fill_rectangle extension on the GM200+ for Desktop OpenGL. Signed-off-by: Lyude <[email protected]> Changes since v1: - Fix commit message - Add note to reldocs Changes since v2: - Remove unnessecary parens in nvc0_screen_get_param() - Fix sorting in release notes - Don't execute FILL_RECTANGLE method on pre-GM200+ GPUs Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau')
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h3
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_screen.c3
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_state.c7
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h2
4 files changed, 13 insertions, 2 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h
index 1be59522317..accde94f641 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h
@@ -772,6 +772,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__ESIZE 0x00000004
#define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__LEN 0x00000004
+#define NVC0_3D_FILL_RECTANGLE 0x0000113c
+#define NVC0_3D_FILL_RECTANGLE_ENABLE 0x00000002
+
#define NVC0_3D_UNK1140 0x00001140
#define NVC0_3D_UNK1144 0x00001144
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 9631c6fd0a9..5bb963b0056 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -256,6 +256,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
case PIPE_CAP_TGSI_FS_FBFETCH:
return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+ case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+ return class_3d >= GM200_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -286,7 +288,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_CLOCK:
- case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
return 0;
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 32233a51ff2..c51c9a7778f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -211,6 +211,7 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe,
const struct pipe_rasterizer_state *cso)
{
struct nvc0_rasterizer_stateobj *so;
+ uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
uint32_t reg;
so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
@@ -261,6 +262,12 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe,
SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
+ if (class_3d >= GM200_3D_CLASS) {
+ SB_IMMED_3D(so, FILL_RECTANGLE,
+ cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
+ NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
+ }
+
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h b/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h
index 054b1e77d78..3006ed61956 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h
@@ -23,7 +23,7 @@ struct nvc0_blend_stateobj {
struct nvc0_rasterizer_stateobj {
struct pipe_rasterizer_state pipe;
int size;
- uint32_t state[42];
+ uint32_t state[43];
};
struct nvc0_zsa_stateobj {