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authorIlia Mirkin <[email protected]>2015-07-18 16:43:17 -0400
committerIlia Mirkin <[email protected]>2015-07-18 17:34:48 -0400
commit20e484afa4874e87cd18daffd66286bb893cf3fb (patch)
treeca081966cb6e8ed02dbbfa1e102dc8911b633516 /src/gallium/drivers/nouveau
parent670914ea7cf7808ff37ca54db2844f711436031c (diff)
nvc0/ir: fix txq on indirect samplers
Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
Diffstat (limited to 'src/gallium/drivers/nouveau')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp2
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp56
2 files changed, 56 insertions, 2 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 018a1ec6d1d..e5164ca0d18 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1728,7 +1728,7 @@ Converter::handleTXQ(Value *dst0[4], enum TexQuery query)
}
tex->setSrc((c = 0), fetchSrc(0, 0)); // mip level
- setTexRS(tex, c, 1, -1);
+ setTexRS(tex, ++c, 1, -1);
bb->insertTail(tex);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 7a5d1ce0299..da364f2ad04 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -956,7 +956,61 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
bool
NVC0LoweringPass::handleTXQ(TexInstruction *txq)
{
- // TODO: indirect resource/sampler index
+ if (txq->tex.rIndirectSrc < 0 && txq->tex.sIndirectSrc < 0)
+ return true;
+
+ Value *ticRel = txq->getIndirectR();
+ Value *tscRel = txq->getIndirectS();
+ const int chipset = prog->getTarget()->getChipset();
+
+ txq->setIndirectS(NULL);
+ txq->tex.sIndirectSrc = -1;
+
+ if (chipset < NVISA_GK104_CHIPSET) {
+ LValue *src = new_LValue(func, FILE_GPR); // 0xttxsaaaa
+
+ if (ticRel) {
+ txq->setSrc(txq->tex.rIndirectSrc, NULL);
+ if (txq->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ ticRel, bld.mkImm(txq->tex.r));
+ }
+ if (tscRel) {
+ txq->setSrc(txq->tex.sIndirectSrc, NULL);
+ if (txq->tex.s)
+ tscRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ tscRel, bld.mkImm(txq->tex.s));
+ }
+
+ bld.loadImm(src, 0);
+
+ if (ticRel)
+ bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
+ if (tscRel)
+ bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
+
+ txq->moveSources(0, 1);
+ txq->setSrc(0, src);
+ } else {
+ // XXX this ignores tsc, and assumes a 1:1 mapping
+ assert(txq->tex.rIndirectSrc >= 0);
+ Value *hnd = loadTexHandle(
+ bld.mkOp2v(OP_SHL, TYPE_U32, bld.getSSA(),
+ txq->getIndirectR(), bld.mkImm(2)),
+ txq->tex.r);
+ txq->tex.r = 0xff;
+ txq->tex.s = 0x1f;
+
+ if (chipset < NVISA_GM107_CHIPSET) {
+ txq->setIndirectR(NULL);
+ txq->moveSources(0, 1);
+ txq->setSrc(0, hnd);
+ txq->tex.rIndirectSrc = 0;
+ } else {
+ txq->setIndirectR(hnd);
+ }
+ }
+
return true;
}