diff options
| author | Samuel Pitoiset <[email protected]> | 2016-07-21 22:15:52 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2016-07-22 11:32:04 +0200 |
| commit | dbcff7fdbba8cf1305e1670f47cadffe676df252 (patch) | |
| tree | 123c4ff8bc8883d00409c140c549a808e00287d8 /src/gallium/drivers/nouveau/nvc0 | |
| parent | cb7077312954299fb1febed5b016190c00cccfa0 (diff) | |
nvc0: fix offsets of MP perf counters input parameters
This fixes a regression introduced in
1da704a94c57aa0b0cf8faaa3236fe47dfb8f88c because the offset has moved
from 0x600 to 0x620, and the kernels used for reading MP perf counters
have to be re-assembled.
This also fixes amd_performance_monitor_measure piglit.
Fixes: 1da704a ("nvc0: increase the tex handles area size in the driver")
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau/nvc0')
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c index 944349d9e8a..d4721201bba 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c @@ -372,9 +372,9 @@ static const uint64_t nve4_read_hw_sm_counters_code[] = * mov b32 $r6 $pm6 * mov b32 $r7 $pm7 * set $p0 0x1 eq u32 $r8 0x0 - * mov b32 $r10 c7[0x600] + * mov b32 $r10 c7[0x620] * ext u32 $r8 $r12 0x414 - * mov b32 $r11 c7[0x604] + * mov b32 $r11 c7[0x624] * sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04 * ext u32 $r9 $r12 0x208 * (not $p0) exit @@ -392,7 +392,7 @@ static const uint64_t nve4_read_hw_sm_counters_code[] = * add b32 $r12 $c $r12 $r9 * st b128 wt g[$r10d] $r0q * sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00 - * mov b32 $r0 c7[0x608] + * mov b32 $r0 c7[0x628] * add b32 $r13 $r13 0x0 $c * $p1 st b128 wt g[$r12d+0x40] $r4q * st b32 wt g[$r12d+0x50] $r0 @@ -410,9 +410,9 @@ static const uint64_t nve4_read_hw_sm_counters_code[] = 0x2c00000028019c04ULL, 0x2c0000002c01dc04ULL, 0x190e0000fc81dc03ULL, - 0x28005c1800029de4ULL, + 0x28005c1880029de4ULL, 0x7000c01050c21c03ULL, - 0x28005c181002dde4ULL, + 0x28005c189002dde4ULL, 0x204282020042e047ULL, 0x7000c00820c25c03ULL, 0x80000000000021e7ULL, @@ -430,7 +430,7 @@ static const uint64_t nve4_read_hw_sm_counters_code[] = 0x4801000024c31c03ULL, 0x9400000000a01fc5ULL, 0x200002e04202c047ULL, - 0x28005c1820001de4ULL, + 0x28005c18a0001de4ULL, 0x0800000000d35c42ULL, 0x9400000100c107c5ULL, 0x9400000140c01f85ULL, @@ -453,9 +453,9 @@ static const uint64_t nvf0_read_hw_sm_counters_code[] = 0x86400000051c001aULL, 0x86400000059c001eULL, 0xdb201c007f9c201eULL, - 0x64c03ce0c01c002aULL, + 0x64c03ce0c41c002aULL, 0xc00000020a1c3021ULL, - 0x64c03ce0c09c002eULL, + 0x64c03ce0c49c002eULL, 0x0810a0808010b810ULL, 0xc0000001041c3025ULL, 0x180000000020003cULL, @@ -473,7 +473,7 @@ static const uint64_t nvf0_read_hw_sm_counters_code[] = 0xe0840000049c3032ULL, 0xfe800000001c2800ULL, 0x080000b81080b010ULL, - 0x64c03ce0c11c0002ULL, + 0x64c03ce0c51c0002ULL, 0xe08040007f9c3436ULL, 0xfe80000020043010ULL, 0xfc800000281c3000ULL, @@ -1105,14 +1105,14 @@ static const uint64_t nvc0_read_hw_sm_counters_code[] = * mov b32 $r6 $pm6 * mov b32 $r7 $pm7 * set $p0 0x1 eq u32 $r8 0x0 - * mov b32 $r10 c15[0x600] - * mov b32 $r11 c15[0x604] + * mov b32 $r10 c15[0x620] + * mov b32 $r11 c15[0x624] * ext u32 $r8 $r9 0x414 * (not $p0) exit * mul $r8 u32 $r8 u32 48 * add b32 $r10 $c $r10 $r8 * add b32 $r11 $r11 0x0 $c - * mov b32 $r8 c15[0x608] + * mov b32 $r8 c15[0x628] * st b128 wt g[$r10d+0x00] $r0q * st b128 wt g[$r10d+0x10] $r4q * st b32 wt g[$r10d+0x20] $r8 @@ -1128,14 +1128,14 @@ static const uint64_t nvc0_read_hw_sm_counters_code[] = 0x2c00000028019c04ULL, 0x2c0000002c01dc04ULL, 0x190e0000fc81dc03ULL, - 0x28007c1800029de4ULL, - 0x28007c181002dde4ULL, + 0x28007c1880029de4ULL, + 0x28007c189002dde4ULL, 0x7000c01050921c03ULL, 0x80000000000021e7ULL, 0x10000000c0821c02ULL, 0x4801000020a29c03ULL, 0x0800000000b2dc42ULL, - 0x28007c1820021de4ULL, + 0x28007c18a0021de4ULL, 0x9400000000a01fc5ULL, 0x9400000040a11fc5ULL, 0x9400000080a21f85ULL, |