diff options
author | Boyan Ding <[email protected]> | 2017-04-26 21:21:58 +0800 |
---|---|---|
committer | Samuel Pitoiset <[email protected]> | 2017-04-27 11:11:12 +0200 |
commit | d03bfb078b6aee0361f07cc7368bbed4047a808a (patch) | |
tree | 1d52bf0fb762b87edfe76e6377e4e5d247603b09 /src/gallium/drivers/nouveau/nvc0/nve4_compute.h | |
parent | 2e35bd964ead9d30e52542e39835d52c0fef0ada (diff) |
nvc0: Add new launch descriptor format for GP100
v2:
Also handle the the new format in indirect dispatch
Use compute class check instead of chipset check
Signed-off-by: Boyan Ding <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau/nvc0/nve4_compute.h')
-rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nve4_compute.h | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h index 75b169323bc..7ff6935cc3d 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h @@ -45,6 +45,46 @@ struct nve4_cp_launch_desc u32 unk48[16]; }; +struct gp100_cp_launch_desc +{ + u32 unk0[8]; + u32 entry; + u32 unk9[2]; + u32 unk11_0 : 30; + u32 linked_tsc : 1; + u32 unk11_31 : 1; + u32 griddim_x : 31; + u32 unk12 : 1; + u16 griddim_y; + u16 unk13; + u16 griddim_z; + u16 unk14; + u32 unk15[2]; + u32 shared_size : 18; + u32 unk17 : 14; + u16 unk18; + u16 blockdim_x; + u16 blockdim_y; + u16 blockdim_z; + u32 cb_mask : 8; + u32 unk20 : 24; + u32 unk21[8]; + u32 local_size_p : 24; + u32 unk29 : 3; + u32 bar_alloc : 5; + u32 local_size_n : 24; + u32 gpr_alloc : 8; + u32 cstack_size : 24; + u32 unk31 : 8; + struct { + u32 address_l; + u32 address_h : 17; + u32 reserved : 2; + u32 size_sh4 : 13; + } cb[8]; + u32 unk48[16]; +}; + static inline void nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc) { @@ -73,6 +113,33 @@ nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc, desc->cb_mask |= 1 << index; } +static inline void +gp100_cp_launch_desc_init_default(struct gp100_cp_launch_desc *desc) +{ + memset(desc, 0, sizeof(*desc)); + + desc->unk0[4] = 0x40; + desc->unk11_0 = 0x04014000; +} + +static inline void +gp100_cp_launch_desc_set_cb(struct gp100_cp_launch_desc *desc, + unsigned index, + struct nouveau_bo *bo, + uint32_t base, uint32_t size) +{ + uint64_t address = bo->offset + base; + + assert(index < 8); + assert(!(base & 0xff)); + + desc->cb[index].address_l = address; + desc->cb[index].address_h = address >> 32; + desc->cb[index].size_sh4 = DIV_ROUND_UP(size, 16); + + desc->cb_mask |= 1 << index; +} + struct nve4_mp_trap_info { u32 lock; u32 pc; |