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authorIlia Mirkin <[email protected]>2016-06-29 00:08:01 -0400
committerIlia Mirkin <[email protected]>2016-07-01 23:01:02 -0400
commitb2b5075e04bbe6c6462fd01711524abd80380f45 (patch)
treea9bd6817f9b9c7ab76009cd1222c6041c7e8385a /src/gallium/drivers/nouveau/nvc0/nvc0_program.c
parent07cc838b105dd3f34526db73064f1f21b452240e (diff)
nvc0: fix up image support for allowing multiple samples
Basically we just have to scale up the coordinates and then add the relevant sample offset. The code to handle this was already largely present from Christoph's earlier attempts to pipe images through back in the dark ages, this just hooks it all up. Signed-off-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau/nvc0/nvc0_program.c')
-rw-r--r--src/gallium/drivers/nouveau/nvc0/nvc0_program.c20
1 files changed, 8 insertions, 12 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index aba95114eb7..d75b702c809 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -555,29 +555,25 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
info->io.genUserClip = prog->vp.num_ucps;
info->io.auxCBSlot = 15;
+ info->io.msInfoCBSlot = 15;
info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
+ info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
+ info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
+ info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
+ if (chipset >= NVISA_GK104_CHIPSET) {
+ info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
+ }
if (prog->type == PIPE_SHADER_COMPUTE) {
if (chipset >= NVISA_GK104_CHIPSET) {
info->io.auxCBSlot = 7;
- info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
+ info->io.msInfoCBSlot = 7;
info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO;
info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
}
- info->io.msInfoCBSlot = 0;
- info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
- info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
- info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
} else {
- if (chipset >= NVISA_GK104_CHIPSET) {
- info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
- }
info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
- info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
- info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
- info->io.msInfoCBSlot = 15;
- info->io.msInfoBase = 0; /* TODO */
}
info->assignSlots = nvc0_program_assign_varying_slots;