summaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/nouveau/codegen
diff options
context:
space:
mode:
authorBen Skeggs <[email protected]>2013-12-06 09:09:42 +1000
committerBen Skeggs <[email protected]>2013-12-06 11:28:45 +1000
commit92ceb327bad73cfde0b68aafb3921067351617fd (patch)
tree47661d29285a6d5b7c6d33b8d4a9478da70e26d7 /src/gallium/drivers/nouveau/codegen
parent26f3ff8a916d7315b2d6d23ee9e52d946b68a136 (diff)
nvc0: fixup gk110 and up not being listed in various switch statements
Signed-off-by: Ben Skeggs <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp5
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp5
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp12
3 files changed, 15 insertions, 7 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index d65003ce4eb..bbf9838b1b4 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -851,6 +851,8 @@ GCRA::coalesce(ArrayList& insns)
case 0xc0:
case 0xd0:
case 0xe0:
+ case 0xf0:
+ case 0x100:
ret = doCoalesce(insns, JOIN_MASK_UNION);
break;
default:
@@ -1952,7 +1954,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
texConstraintNVC0(tex);
break;
case 0xe0:
- case NVISA_GK110_CHIPSET:
+ case 0xf0:
+ case 0x100:
texConstraintNVE0(tex);
break;
default:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 443acfcd812..112fca7d152 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -134,11 +134,12 @@ extern Target *getTargetNV50(unsigned int chipset);
Target *Target::create(unsigned int chipset)
{
- switch (chipset & 0xf0) {
+ switch (chipset & ~0xf) {
case 0xc0:
case 0xd0:
case 0xe0:
- case NVISA_GK110_CHIPSET:
+ case 0xf0:
+ case 0x100:
return getTargetNVC0(chipset);
case 0x50:
case 0x80:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 47e9c558d35..1f3932ed759 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -46,12 +46,13 @@ TargetNVC0::TargetNVC0(unsigned int card) : Target(false, card >= 0xe4)
void
TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
{
- switch (chipset & 0xf0) {
+ switch (chipset & ~0xf) {
case 0xe0:
*code = (const uint32_t *)&nve4_builtin_code[0];
*size = sizeof(nve4_builtin_code);
break;
case 0xf0:
+ case 0x100:
*code = (const uint32_t *)&nvf0_builtin_code[0];
*size = sizeof(nvf0_builtin_code);
break;
@@ -67,9 +68,12 @@ TargetNVC0::getBuiltinOffset(int builtin) const
{
assert(builtin < NVC0_BUILTIN_COUNT);
- switch (chipset & 0xf0) {
- case 0xe0: return nve4_builtin_offsets[builtin];
- case 0xf0: return nvf0_builtin_offsets[builtin];
+ switch (chipset & ~0xf) {
+ case 0xe0:
+ return nve4_builtin_offsets[builtin];
+ case 0xf0:
+ case 0x100:
+ return nvf0_builtin_offsets[builtin];
default:
return nvc0_builtin_offsets[builtin];
}