diff options
author | Karol Herbst <[email protected]> | 2017-03-26 21:46:01 +0200 |
---|---|---|
committer | Ilia Mirkin <[email protected]> | 2017-03-31 23:57:16 -0400 |
commit | baaae8cb81bd62a78d63adfc0d9278288162e36b (patch) | |
tree | a1bc8087a487b72359d5800be081f3d0eb98f1a0 /src/gallium/drivers/nouveau/codegen | |
parent | 7d007824a312d4426e8e8e487e502e5fea2bbf58 (diff) |
nv50/ir: also do PostRaLoadPropagation for FMA
Helps Feral-ported games, due to their use of fma()
shader-db changes:
total instructions in shared programs : 3934925 -> 3934327 (-0.02%)
total gprs used in shared programs : 481563 -> 481563 (0.00%)
total local used in shared programs : 27469 -> 27469 (0.00%)
total bytes used in shared programs : 36061888 -> 36056504 (-0.01%)
local gpr inst bytes
helped 0 0 228 228
hurt 0 0 0 0
Signed-off-by: Karol Herbst <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen')
-rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 | ||||
-rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 7cf0166cbbd..4c92a1efb51 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp @@ -3307,6 +3307,7 @@ bool PostRaLoadPropagation::visit(Instruction *i) { switch (i->op) { + case OP_FMA: case OP_MAD: if (prog->getTarget()->getChipset() < 0xc0) handleMADforNV50(i); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index d36c8531a27..193628cfbda 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -1471,7 +1471,7 @@ GCRA::allocateRegisters(ArrayList& insns) if (lval->inFile(FILE_GPR) && lval->getInsn() != NULL && prog->getTarget()->getChipset() < 0xc0) { Instruction *insn = lval->getInsn(); - if (insn->op == OP_MAD || insn->op == OP_SAD) + if (insn->op == OP_MAD || insn->op == OP_FMA || insn->op == OP_SAD) // Short encoding only possible if they're all GPRs, no need to // affect them otherwise. if (insn->flagsDef < 0 && |