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authorErico Nunes <[email protected]>2019-07-22 01:27:11 +0200
committerErico Nunes <[email protected]>2019-08-04 13:38:19 +0200
commit486b33558a5d5fe18fb87e98f75c34ef992428af (patch)
treeb820f414372b9662f77d1c1e36c6b74cf6dea19b /src/gallium/drivers/lima
parentfd29c4d6c561272ab34a71a308c36a0bb72b4816 (diff)
lima/ppir: simplify load uni/temp op lowering and scheduling
The load uniform/temporary operations output only to a pipeline register, which must be consumed by another op in the same instruction later. The current implementation delays the decision of who will consume this result to until the scheduling step. If the consumer node is not able to use the pipeline register, a mov node may have to be created, during the scheduler step. As part of the ppir scheduler simplification, and now that the ppir scheduler supports pipeline register dependencies, this can be simplified by always creating a single mov node outputting to a normal register that can be used directly by all consumers. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
Diffstat (limited to 'src/gallium/drivers/lima')
-rw-r--r--src/gallium/drivers/lima/ir/pp/lower.c29
-rw-r--r--src/gallium/drivers/lima/ir/pp/node_to_instr.c38
2 files changed, 33 insertions, 34 deletions
diff --git a/src/gallium/drivers/lima/ir/pp/lower.c b/src/gallium/drivers/lima/ir/pp/lower.c
index 97837f4c198..2244fc7dc31 100644
--- a/src/gallium/drivers/lima/ir/pp/lower.c
+++ b/src/gallium/drivers/lima/ir/pp/lower.c
@@ -87,6 +87,33 @@ static bool ppir_lower_swap_args(ppir_block *block, ppir_node *node)
return true;
}
+static bool ppir_lower_load(ppir_block *block, ppir_node *node)
+{
+ ppir_node *move = ppir_node_create(block, ppir_op_mov, -1 , 0);
+ if (unlikely(!move))
+ return false;
+
+ ppir_alu_node *alu = ppir_node_to_alu(move);
+
+ ppir_dest *dest = ppir_node_get_dest(node);
+ alu->dest = *dest;
+
+ ppir_node_replace_all_succ(move, node);
+
+ dest->type = ppir_target_pipeline;
+ dest->pipeline = ppir_pipeline_reg_uniform;
+
+ alu->num_src = 1;
+ ppir_node_target_assign(&alu->src[0], dest);
+ for (int i = 0; i < 4; i++)
+ alu->src->swizzle[i] = i;
+
+ ppir_node_add_dep(move, node);
+ list_addtail(&move->list, &node->list);
+
+ return true;
+}
+
static bool ppir_lower_texture(ppir_block *block, ppir_node *node)
{
ppir_load_texture_node *load_tex = ppir_node_to_load_texture(node);
@@ -336,6 +363,8 @@ static bool (*ppir_lower_funcs[ppir_op_num])(ppir_block *, ppir_node *) = {
[ppir_op_trunc] = ppir_lower_trunc,
[ppir_op_sat] = ppir_lower_sat,
[ppir_op_branch] = ppir_lower_branch,
+ [ppir_op_load_uniform] = ppir_lower_load,
+ [ppir_op_load_temp] = ppir_lower_load,
};
bool ppir_lower_prog(ppir_compiler *comp)
diff --git a/src/gallium/drivers/lima/ir/pp/node_to_instr.c b/src/gallium/drivers/lima/ir/pp/node_to_instr.c
index 711fe2153b4..f4b3114852f 100644
--- a/src/gallium/drivers/lima/ir/pp/node_to_instr.c
+++ b/src/gallium/drivers/lima/ir/pp/node_to_instr.c
@@ -121,15 +121,6 @@ static bool insert_to_each_succ_instr(ppir_block *block, ppir_node *node)
dup->instr = instr;
dup->instr_pos = node->instr_pos;
ppir_node_replace_pred(dep, dup);
-
- if ((node->op == ppir_op_load_uniform) || (node->op == ppir_op_load_temp)) {
- ppir_load_node *load = ppir_node_to_load(node);
- ppir_load_node *dup_load = ppir_node_to_load(dup);
- dup_load->dest = load->dest;
- dup_load->index = load->index;
- dup_load->num_components = load->num_components;
- instr->slots[node->instr_pos] = dup;
- }
}
list_splicetail(&dup_list, &node->list);
@@ -190,31 +181,10 @@ static bool ppir_do_one_node_to_instr(ppir_block *block, ppir_node *node, ppir_n
break;
}
case ppir_node_type_load:
- if ((node->op == ppir_op_load_uniform) || (node->op == ppir_op_load_temp)) {
- /* merge pred load_uniform into succ instr can save a reg
- * by using pipeline reg */
- if (!insert_to_each_succ_instr(block, node))
- return false;
-
- ppir_load_node *load = ppir_node_to_load(node);
- load->dest.type = ppir_target_pipeline;
- load->dest.pipeline = ppir_pipeline_reg_uniform;
- }
- else if (node->op == ppir_op_load_temp) {
- /* merge pred load_temp into succ instr can save a reg
- * by using pipeline reg */
- if (!insert_to_each_succ_instr(block, node))
- return false;
-
- ppir_load_node *load = ppir_node_to_load(node);
- load->dest.type = ppir_target_pipeline;
- load->dest.pipeline = ppir_pipeline_reg_uniform;
- }
- else if (node->op == ppir_op_load_varying ||
- node->op == ppir_op_load_fragcoord ||
- node->op == ppir_op_load_pointcoord ||
- node->op == ppir_op_load_frontface) {
- /* delay the load varying dup to scheduler */
+ if (node->op == ppir_op_load_varying ||
+ node->op == ppir_op_load_fragcoord ||
+ node->op == ppir_op_load_pointcoord ||
+ node->op == ppir_op_load_frontface) {
if (!create_new_instr(block, node))
return false;
}