iris: crazy pipe control code

imported from ~kwg/mesa pcx-2, gen < 8 code dropped

1 files changed, 67 insertions, 0 deletions

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 81eef52a7a6..cc79f72b767 100644
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -117,6 +117,57 @@ enum iris_program_cache_id {
    IRIS_CACHE_BLORP_BLIT,
 };
 
+/** @{
+ *
+ * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
+ * additional flushing control.
+ *
+ * The bits here are not the actual hardware values.  The actual values
+ * shift around a bit per-generation, so we just have flags for each
+ * potential operation, and use genxml to encode the actual packet.
+ */
+enum pipe_control_flags
+{
+   PIPE_CONTROL_FLUSH_LLC                       = (1 << 1),
+   PIPE_CONTROL_LRI_POST_SYNC_OP                = (1 << 2),
+   PIPE_CONTROL_STORE_DATA_INDEX                = (1 << 3),
+   PIPE_CONTROL_CS_STALL                        = (1 << 4),
+   PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET     = (1 << 5),
+   PIPE_CONTROL_SYNC_GFDT                       = (1 << 6),
+   PIPE_CONTROL_TLB_INVALIDATE                  = (1 << 7),
+   PIPE_CONTROL_MEDIA_STATE_CLEAR               = (1 << 8),
+   PIPE_CONTROL_WRITE_IMMEDIATE                 = (1 << 9),
+   PIPE_CONTROL_WRITE_DEPTH_COUNT               = (1 << 10),
+   PIPE_CONTROL_WRITE_TIMESTAMP                 = (1 << 11),
+   PIPE_CONTROL_DEPTH_STALL                     = (1 << 12),
+   PIPE_CONTROL_RENDER_TARGET_FLUSH             = (1 << 13),
+   PIPE_CONTROL_INSTRUCTION_INVALIDATE          = (1 << 14),
+   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE        = (1 << 15),
+   PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16),
+   PIPE_CONTROL_NOTIFY_ENABLE                   = (1 << 17),
+   PIPE_CONTROL_FLUSH_ENABLE                    = (1 << 18),
+   PIPE_CONTROL_DATA_CACHE_FLUSH                = (1 << 19),
+   PIPE_CONTROL_VF_CACHE_INVALIDATE             = (1 << 20),
+   PIPE_CONTROL_CONST_CACHE_INVALIDATE          = (1 << 21),
+   PIPE_CONTROL_STATE_CACHE_INVALIDATE          = (1 << 22),
+   PIPE_CONTROL_STALL_AT_SCOREBOARD             = (1 << 23),
+   PIPE_CONTROL_DEPTH_CACHE_FLUSH               = (1 << 24),
+};
+
+#define PIPE_CONTROL_CACHE_FLUSH_BITS \
+   (PIPE_CONTROL_DEPTH_CACHE_FLUSH |  \
+    PIPE_CONTROL_DATA_CACHE_FLUSH |   \
+    PIPE_CONTROL_RENDER_TARGET_FLUSH)
+
+#define PIPE_CONTROL_CACHE_INVALIDATE_BITS  \
+   (PIPE_CONTROL_STATE_CACHE_INVALIDATE |   \
+    PIPE_CONTROL_CONST_CACHE_INVALIDATE |   \
+    PIPE_CONTROL_VF_CACHE_INVALIDATE |      \
+    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+    PIPE_CONTROL_INSTRUCTION_INVALIDATE)
+
+/** @} */
+
 struct iris_compiled_shader {
    /** Buffer containing the uploaded assembly. */
    struct pipe_resource *buffer;
@@ -203,6 +254,9 @@ struct iris_context {
       void (*upload_render_state)(struct iris_context *ice,
                                   struct iris_batch *batch,
                                   const struct pipe_draw_info *draw);
+      void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
+                                    struct iris_bo *bo, uint32_t offset,
+                                    uint64_t imm);
       unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
       void (*set_derived_program_state)(const struct gen_device_info *devinfo,
                                         enum iris_program_cache_id cache_id,
@@ -243,6 +297,19 @@ void iris_update_compiled_shaders(struct iris_context *ice);
 
 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 
+/* iris_pipe_control.c */
+
+void iris_emit_pipe_control_flush(struct iris_context *ice,
+                                  struct iris_batch *batch,
+                                  uint32_t flags);
+void iris_emit_pipe_control_write(struct iris_context *ice,
+                                  struct iris_batch *batch, uint32_t flags,
+                                  struct iris_bo *bo, uint32_t offset,
+                                  uint64_t imm);
+void iris_emit_end_of_pipe_sync(struct iris_context *ice,
+                                struct iris_batch *batch,
+                                uint32_t flags);
+
 /* iris_state.c */
 
 void gen9_init_state(struct iris_context *ice);