ilo: update genhw headers

Generate these new enums

  enum gen_reorder_mode;
  enum gen_clip_mode;
  enum gen_front_winding;
  enum gen_fill_mode;
  enum gen_cull_mode;
  enum gen_pixel_location;
  enum gen_sample_count;
  enum gen_inputattr_select;
  enum gen_msrast_mode;
  enum gen_prefilter_op;

Correct the type of GEN6_SAMPLER_DW0_BASE_LOD.  Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.

11 files changed, 298 insertions, 282 deletions

diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h b/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h
index 16ec4afd15b..093cca12840 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h
+++ b/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h
@@ -66,7 +66,7 @@ gen6_3DSTATE_CLIP(struct ilo_builder *builder,
                   GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
       dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
 
-   dw3 |= GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO |
+   dw3 |= GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO |
           (num_viewports - 1);
 
    ilo_builder_batch_pointer(builder, cmd_len, &dw);
@@ -107,7 +107,7 @@ gen7_internal_3dstate_sf(struct ilo_builder *builder,
 
    if (!sf) {
       dw[1] = 0;
-      dw[2] = (num_samples > 1) ? GEN7_SF_DW2_MSRASTMODE_ON_PATTERN : 0;
+      dw[2] = (num_samples > 1) ? (GEN6_MSRASTMODE_ON_PATTERN << 8) : 0;
       dw[3] = 0;
       dw[4] = 0;
       dw[5] = 0;
@@ -593,23 +593,23 @@ gen8_3DSTATE_WM_HZ_OP(struct ilo_builder *builder, uint32_t op,
    switch (sample_count) {
    case 0:
    case 1:
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 13;
       break;
    case 2:
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_2;
+      dw1 |= GEN8_NUMSAMPLES_2 << 13;
       break;
    case 4:
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_4;
+      dw1 |= GEN6_NUMSAMPLES_4 << 13;
       break;
    case 8:
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_8;
+      dw1 |= GEN7_NUMSAMPLES_8 << 13;
       break;
    case 16:
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_16;
+      dw1 |= GEN8_NUMSAMPLES_16 << 13;
       break;
    default:
       assert(!"unsupported sample count");
-      dw1 |= GEN8_WM_HZ_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 13;
       break;
    }
 
@@ -772,7 +772,7 @@ gen8_3DSTATE_PS_EXTRA(struct ilo_builder *builder,
    dw1 = cso->payload[3];
 
    if (cc_may_kill)
-      dw1 |= GEN8_PSX_DW1_DISPATCH_ENABLE | GEN8_PSX_DW1_KILL_PIXEL;
+      dw1 |= GEN8_PSX_DW1_VALID | GEN8_PSX_DW1_KILL_PIXEL;
    if (per_sample)
       dw1 |= GEN8_PSX_DW1_PER_SAMPLE;
 
@@ -866,34 +866,35 @@ gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
                          bool pixel_location_center)
 {
    const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
+   const enum gen_pixel_location pixloc = (pixel_location_center) ?
+      GEN6_PIXLOC_CENTER : GEN6_PIXLOC_UL_CORNER;
    uint32_t dw1, dw2, dw3, *dw;
 
    ILO_DEV_ASSERT(builder->dev, 6, 7.5);
 
-   dw1 = (pixel_location_center) ? GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER :
-      GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER;
+   dw1 = pixloc << 4;
 
    switch (num_samples) {
    case 0:
    case 1:
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 1;
       dw2 = 0;
       dw3 = 0;
       break;
    case 4:
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
+      dw1 |= GEN6_NUMSAMPLES_4 << 1;
       dw2 = pattern[0];
       dw3 = 0;
       break;
    case 8:
       assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
-      dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
+      dw1 |= GEN7_NUMSAMPLES_8 << 1;
       dw2 = pattern[0];
       dw3 = pattern[1];
       break;
    default:
       assert(!"unsupported sample count");
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 1;
       dw2 = 0;
       dw3 = 0;
       break;
@@ -914,33 +915,34 @@ gen8_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
                          bool pixel_location_center)
 {
    const uint8_t cmd_len = 2;
+   const enum gen_pixel_location pixloc = (pixel_location_center) ?
+      GEN6_PIXLOC_CENTER : GEN6_PIXLOC_UL_CORNER;
    uint32_t dw1, *dw;
 
    ILO_DEV_ASSERT(builder->dev, 8, 8);
 
-   dw1 = (pixel_location_center) ? GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER :
-      GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER;
+   dw1 = pixloc << 4;
 
    switch (num_samples) {
    case 0:
    case 1:
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 1;
       break;
    case 2:
-      dw1 |= GEN8_MULTISAMPLE_DW1_NUMSAMPLES_2;
+      dw1 |= GEN8_NUMSAMPLES_2 << 1;
       break;
    case 4:
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
+      dw1 |= GEN6_NUMSAMPLES_4 << 1;
       break;
    case 8:
-      dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
+      dw1 |= GEN7_NUMSAMPLES_8 << 1;
       break;
    case 16:
-      dw1 |= GEN8_MULTISAMPLE_DW1_NUMSAMPLES_16;
+      dw1 |= GEN8_NUMSAMPLES_16 << 1;
       break;
    default:
       assert(!"unsupported sample count");
-      dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1;
+      dw1 |= GEN6_NUMSAMPLES_1 << 1;
       break;
    }
 
@@ -1732,10 +1734,10 @@ gen6_BLEND_STATE(struct ilo_builder *builder,
          if (caps->can_alpha_test)
             dw[1] |= dsa->dw_blend_alpha;
       } else {
-         dw[1] |= GEN6_RT_DW1_WRITE_DISABLE_A |
-                  GEN6_RT_DW1_WRITE_DISABLE_R |
-                  GEN6_RT_DW1_WRITE_DISABLE_G |
-                  GEN6_RT_DW1_WRITE_DISABLE_B |
+         dw[1] |= GEN6_RT_DW1_WRITE_DISABLES_A |
+                  GEN6_RT_DW1_WRITE_DISABLES_R |
+                  GEN6_RT_DW1_WRITE_DISABLES_G |
+                  GEN6_RT_DW1_WRITE_DISABLES_B |
                   dsa->dw_blend_alpha;
       }
 
@@ -1800,10 +1802,10 @@ gen8_BLEND_STATE(struct ilo_builder *builder,
          if (caps->can_logicop)
             dw[1] |= blend->dw_logicop;
       } else {
-         dw[0] |= GEN8_RT_DW0_WRITE_DISABLE_A |
-                  GEN8_RT_DW0_WRITE_DISABLE_R |
-                  GEN8_RT_DW0_WRITE_DISABLE_G |
-                  GEN8_RT_DW0_WRITE_DISABLE_B;
+         dw[0] |= GEN8_RT_DW0_WRITE_DISABLES_A |
+                  GEN8_RT_DW0_WRITE_DISABLES_R |
+                  GEN8_RT_DW0_WRITE_DISABLES_G |
+                  GEN8_RT_DW0_WRITE_DISABLES_B;
       }
 
       dw += 2;
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
index f9275b64d0e..cfa0e441855 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
+++ b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
@@ -1051,7 +1051,7 @@ gen7_3DSTATE_STREAMOUT(struct ilo_builder *builder,
                GEN7_SO_DW1_STATISTICS;
       /* API_OPENGL */
       if (true)
-         dw[1] |= GEN7_SO_DW1_REORDER_TRAILING;
+         dw[1] |= GEN7_REORDER_TRAILING << GEN7_SO_DW1_REORDER_MODE__SHIFT;
       if (ilo_dev_gen(builder->dev) < ILO_GEN(8))
          dw[1] |= buf_mask << GEN7_SO_DW1_BUFFER_ENABLES__SHIFT;
 
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_decode.c b/src/gallium/drivers/ilo/core/ilo_builder_decode.c
index cedaab1559d..c5a98c91204 100644
--- a/src/gallium/drivers/ilo/core/ilo_builder_decode.c
+++ b/src/gallium/drivers/ilo/core/ilo_builder_decode.c
@@ -319,7 +319,7 @@ writer_decode_color_calc(const struct ilo_builder *builder,
               "stencil ref %d, bf stencil ref %d\n",
 	      GEN_EXTRACT(dw, GEN6_CC_DW0_ALPHATEST) ? "FLOAT32" : "UNORM8",
 	      (bool) (dw & GEN6_CC_DW0_ROUND_DISABLE_DISABLE),
-	      GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL0_REF),
+	      GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL_REF),
 	      GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL1_REF));
 
    writer_dw(builder, which, item->offset, 1, "CC\n");
@@ -347,13 +347,13 @@ writer_decode_depth_stencil(const struct ilo_builder *builder,
    dw = writer_dw(builder, which, item->offset, 0, "D_S");
    ilo_printf("stencil %sable, func %d, write %sable\n",
          (dw & GEN6_ZS_DW0_STENCIL_TEST_ENABLE) ? "en" : "dis",
-         GEN_EXTRACT(dw, GEN6_ZS_DW0_STENCIL0_FUNC),
+         GEN_EXTRACT(dw, GEN6_ZS_DW0_STENCIL_FUNC),
          (dw & GEN6_ZS_DW0_STENCIL_WRITE_ENABLE) ? "en" : "dis");
 
    dw = writer_dw(builder, which, item->offset, 1, "D_S");
    ilo_printf("stencil test mask 0x%x, write mask 0x%x\n",
-         GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL0_VALUEMASK),
-         GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL0_WRITEMASK));
+         GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_TEST_MASK),
+         GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_WRITE_MASK));
 
    dw = writer_dw(builder, which, item->offset, 2, "D_S");
    ilo_printf("depth test %sable, func %d, write %sable\n",
diff --git a/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c b/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
index 22cd4eac82e..9d472d93fdc 100644
--- a/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
+++ b/src/gallium/drivers/ilo/core/ilo_state_3d_bottom.c
@@ -61,20 +61,20 @@ rasterizer_init_clip(const struct ilo_dev *dev,
 
       if (ilo_dev_gen(dev) < ILO_GEN(8)) {
          if (state->front_ccw)
-            dw1 |= GEN7_CLIP_DW1_FRONTWINDING_CCW;
+            dw1 |= GEN6_FRONTWINDING_CCW << 20;
 
          switch (state->cull_face) {
          case PIPE_FACE_NONE:
-            dw1 |= GEN7_CLIP_DW1_CULLMODE_NONE;
+            dw1 |= GEN6_CULLMODE_NONE << 16;
             break;
          case PIPE_FACE_FRONT:
-            dw1 |= GEN7_CLIP_DW1_CULLMODE_FRONT;
+            dw1 |= GEN6_CULLMODE_FRONT << 16;
             break;
          case PIPE_FACE_BACK:
-            dw1 |= GEN7_CLIP_DW1_CULLMODE_BACK;
+            dw1 |= GEN6_CULLMODE_BACK << 16;
             break;
          case PIPE_FACE_FRONT_AND_BACK:
-            dw1 |= GEN7_CLIP_DW1_CULLMODE_BOTH;
+            dw1 |= GEN6_CULLMODE_BOTH << 16;
             break;
          }
       }
@@ -83,7 +83,7 @@ rasterizer_init_clip(const struct ilo_dev *dev,
    dw2 = GEN6_CLIP_DW2_CLIP_ENABLE |
          GEN6_CLIP_DW2_XY_TEST_ENABLE |
          state->clip_plane_enable << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
-         GEN6_CLIP_DW2_CLIPMODE_NORMAL;
+         GEN6_CLIPMODE_NORMAL << 13;
 
    if (state->clip_halfz)
       dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
@@ -160,7 +160,7 @@ rasterizer_init_sf_gen6(const struct ilo_dev *dev,
     *      CLIP_STATE is clear."
     */
    dw1 = GEN7_SF_DW1_STATISTICS |
-         GEN7_SF_DW1_VIEWPORT_ENABLE;
+         GEN7_SF_DW1_VIEWPORT_TRANSFORM;
 
    /* XXX GEN6 path seems to work fine for GEN7 */
    if (false && ilo_dev_gen(dev) >= ILO_GEN(7)) {
@@ -192,30 +192,30 @@ rasterizer_init_sf_gen6(const struct ilo_dev *dev,
 
    switch (state->fill_front) {
    case PIPE_POLYGON_MODE_FILL:
-      dw1 |= GEN7_SF_DW1_FRONTFACE_SOLID;
+      dw1 |= GEN6_FILLMODE_SOLID << 5;
       break;
    case PIPE_POLYGON_MODE_LINE:
-      dw1 |= GEN7_SF_DW1_FRONTFACE_WIREFRAME;
+      dw1 |= GEN6_FILLMODE_WIREFRAME << 5;
       break;
    case PIPE_POLYGON_MODE_POINT:
-      dw1 |= GEN7_SF_DW1_FRONTFACE_POINT;
+      dw1 |= GEN6_FILLMODE_POINT << 5;
       break;
    }
 
    switch (state->fill_back) {
    case PIPE_POLYGON_MODE_FILL:
-      dw1 |= GEN7_SF_DW1_BACKFACE_SOLID;
+      dw1 |= GEN6_FILLMODE_SOLID << 3;
       break;
    case PIPE_POLYGON_MODE_LINE:
-      dw1 |= GEN7_SF_DW1_BACKFACE_WIREFRAME;
+      dw1 |= GEN6_FILLMODE_WIREFRAME << 3;
       break;
    case PIPE_POLYGON_MODE_POINT:
-      dw1 |= GEN7_SF_DW1_BACKFACE_POINT;
+      dw1 |= GEN6_FILLMODE_POINT << 3;
       break;
    }
 
    if (state->front_ccw)
-      dw1 |= GEN7_SF_DW1_FRONTWINDING_CCW;
+      dw1 |= GEN6_FRONTWINDING_CCW;
 
    dw2 = 0;
 
@@ -239,16 +239,16 @@ rasterizer_init_sf_gen6(const struct ilo_dev *dev,
 
    switch (state->cull_face) {
    case PIPE_FACE_NONE:
-      dw2 |= GEN7_SF_DW2_CULLMODE_NONE;
+      dw2 |= GEN6_CULLMODE_NONE << 29;
       break;
    case PIPE_FACE_FRONT:
-      dw2 |= GEN7_SF_DW2_CULLMODE_FRONT;
+      dw2 |= GEN6_CULLMODE_FRONT << 29;
       break;
    case PIPE_FACE_BACK:
-      dw2 |= GEN7_SF_DW2_CULLMODE_BACK;
+      dw2 |= GEN6_CULLMODE_BACK << 29;
       break;
    case PIPE_FACE_FRONT_AND_BACK:
-      dw2 |= GEN7_SF_DW2_CULLMODE_BOTH;
+      dw2 |= GEN6_CULLMODE_BOTH << 29;
       break;
    }
 
@@ -307,7 +307,7 @@ rasterizer_init_sf_gen6(const struct ilo_dev *dev,
    sf->payload[2] = dw3;
 
    if (state->multisample) {
-      sf->dw_msaa = GEN7_SF_DW2_MSRASTMODE_ON_PATTERN;
+      sf->dw_msaa = GEN6_MSRASTMODE_ON_PATTERN << 8;
 
       /*
        * From the Sandy Bridge PRM, volume 2 part 1, page 251:
@@ -339,20 +339,20 @@ rasterizer_get_sf_raster_gen8(const struct ilo_dev *dev,
    ILO_DEV_ASSERT(dev, 8, 8);
 
    if (state->front_ccw)
-      dw |= GEN8_RASTER_DW1_FRONTWINDING_CCW;
+      dw |= GEN6_FRONTWINDING_CCW << 21;
 
    switch (state->cull_face) {
    case PIPE_FACE_NONE:
-      dw |= GEN8_RASTER_DW1_CULLMODE_NONE;
+      dw |= GEN6_CULLMODE_NONE << 16;
       break;
    case PIPE_FACE_FRONT:
-      dw |= GEN8_RASTER_DW1_CULLMODE_FRONT;
+      dw |= GEN6_CULLMODE_FRONT << 16;
       break;
    case PIPE_FACE_BACK:
-      dw |= GEN8_RASTER_DW1_CULLMODE_BACK;
+      dw |= GEN6_CULLMODE_BACK << 16;
       break;
    case PIPE_FACE_FRONT_AND_BACK:
-      dw |= GEN8_RASTER_DW1_CULLMODE_BOTH;
+      dw |= GEN6_CULLMODE_BOTH << 16;
       break;
    }
 
@@ -371,25 +371,25 @@ rasterizer_get_sf_raster_gen8(const struct ilo_dev *dev,
 
    switch (state->fill_front) {
    case PIPE_POLYGON_MODE_FILL:
-      dw |= GEN8_RASTER_DW1_FRONTFACE_SOLID;
+      dw |= GEN6_FILLMODE_SOLID << 5;
       break;
    case PIPE_POLYGON_MODE_LINE:
-      dw |= GEN8_RASTER_DW1_FRONTFACE_WIREFRAME;
+      dw |= GEN6_FILLMODE_WIREFRAME << 5;
       break;
    case PIPE_POLYGON_MODE_POINT:
-      dw |= GEN8_RASTER_DW1_FRONTFACE_POINT;
+      dw |= GEN6_FILLMODE_POINT << 5;
       break;
    }
 
    switch (state->fill_back) {
    case PIPE_POLYGON_MODE_FILL:
-      dw |= GEN8_RASTER_DW1_BACKFACE_SOLID;
+      dw |= GEN6_FILLMODE_SOLID << 3;
       break;
    case PIPE_POLYGON_MODE_LINE:
-      dw |= GEN8_RASTER_DW1_BACKFACE_WIREFRAME;
+      dw |= GEN6_FILLMODE_WIREFRAME << 3;
       break;
    case PIPE_POLYGON_MODE_POINT:
-      dw |= GEN8_RASTER_DW1_BACKFACE_POINT;
+      dw |= GEN6_FILLMODE_POINT << 3;
       break;
    }
 
@@ -429,7 +429,7 @@ rasterizer_init_sf_gen8(const struct ilo_dev *dev,
    point_width = CLAMP(point_width, 1, 2047);
 
    dw1 = GEN7_SF_DW1_STATISTICS |
-         GEN7_SF_DW1_VIEWPORT_ENABLE;
+         GEN7_SF_DW1_VIEWPORT_TRANSFORM;
 
    dw2 = line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
    if (state->line_smooth)
@@ -497,15 +497,15 @@ rasterizer_init_wm_gen6(const struct ilo_dev *dev,
     *
     * is valid
     */
-   STATIC_ASSERT(GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL == 0 &&
+   STATIC_ASSERT(GEN6_MSRASTMODE_OFF_PIXEL == 0 &&
                  GEN6_WM_DW6_MSDISPMODE_PERSAMPLE == 0);
-   dw6 = GEN6_WM_DW6_ZW_INTERP_PIXEL;
+   dw6 = GEN6_ZW_INTERP_PIXEL << GEN6_WM_DW6_ZW_INTERP__SHIFT;
 
    if (state->bottom_edge_rule)
       dw6 |= GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT;
 
    wm->dw_msaa_rast =
-      (state->multisample) ? GEN6_WM_DW6_MSRASTMODE_ON_PATTERN : 0;
+      (state->multisample) ? (GEN6_MSRASTMODE_ON_PATTERN << 1) : 0;
    wm->dw_msaa_disp = GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
 
    STATIC_ASSERT(Elements(wm->payload) >= 2);
@@ -530,9 +530,9 @@ rasterizer_init_wm_gen7(const struct ilo_dev *dev,
     *
     * is valid
     */
-   STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL == 0 &&
+   STATIC_ASSERT(GEN6_MSRASTMODE_OFF_PIXEL == 0 &&
                  GEN7_WM_DW2_MSDISPMODE_PERSAMPLE == 0);
-   dw1 = GEN7_WM_DW1_ZW_INTERP_PIXEL |
+   dw1 = GEN6_ZW_INTERP_PIXEL << GEN7_WM_DW1_ZW_INTERP__SHIFT |
          GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
    dw2 = 0;
 
@@ -549,7 +549,7 @@ rasterizer_init_wm_gen7(const struct ilo_dev *dev,
       dw1 |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
 
    wm->dw_msaa_rast =
-      (state->multisample) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN : 0;
+      (state->multisample) ? GEN6_MSRASTMODE_ON_PATTERN : 0;
    wm->dw_msaa_disp = GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
 
    STATIC_ASSERT(Elements(wm->payload) >= 2);
@@ -565,7 +565,7 @@ rasterizer_get_wm_gen8(const struct ilo_dev *dev,
 
    ILO_DEV_ASSERT(dev, 8, 8);
 
-   dw = GEN7_WM_DW1_ZW_INTERP_PIXEL |
+   dw = GEN6_ZW_INTERP_PIXEL << GEN7_WM_DW1_ZW_INTERP__SHIFT |
         GEN7_WM_DW1_AA_LINE_WIDTH_2_0;
 
    /* same value as in 3DSTATE_SF */
@@ -691,7 +691,7 @@ fs_init_cso_gen6(const struct ilo_dev *dev,
    dw5 |= GEN6_PS_DISPATCH_8 << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
 
    dw6 = input_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
-         GEN6_WM_DW6_PS_POSOFFSET_NONE |
+         GEN6_POSOFFSET_NONE << GEN6_WM_DW6_PS_POSOFFSET__SHIFT |
          interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT;
 
    STATIC_ASSERT(Elements(cso->payload) >= 4);
@@ -752,7 +752,7 @@ fs_get_wm_gen7(const struct ilo_dev *dev,
       dw |= GEN7_WM_DW1_PS_KILL_PIXEL;
 
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
-      dw |= GEN7_WM_DW1_PSCDEPTH_ON;
+      dw |= GEN7_PSCDEPTH_ON << GEN7_WM_DW1_PSCDEPTH__SHIFT;
 
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
       dw |= GEN7_WM_DW1_PS_USE_DEPTH;
@@ -779,7 +779,7 @@ fs_init_cso_gen7(const struct ilo_dev *dev,
    dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT;
    dw2 |= ((sampler_count + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
 
-   dw4 = GEN7_PS_DW4_POSOFFSET_NONE;
+   dw4 = GEN6_POSOFFSET_NONE << GEN7_PS_DW4_POSOFFSET__SHIFT;
 
    /* see brwCreateContext() */
    switch (ilo_dev_gen(dev)) {
@@ -823,12 +823,12 @@ fs_get_psx_gen8(const struct ilo_dev *dev,
 
    ILO_DEV_ASSERT(dev, 8, 8);
 
-   dw = GEN8_PSX_DW1_DISPATCH_ENABLE;
+   dw = GEN8_PSX_DW1_VALID;
 
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL))
       dw |= GEN8_PSX_DW1_KILL_PIXEL;
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z))
-      dw |= GEN8_PSX_DW1_PSCDEPTH_ON;
+      dw |= GEN7_PSCDEPTH_ON << GEN8_PSX_DW1_PSCDEPTH__SHIFT;
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z))
       dw |= GEN8_PSX_DW1_USE_DEPTH;
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W))
@@ -868,7 +868,7 @@ fs_init_cso_gen8(const struct ilo_dev *dev,
 
    /* always 64? */
    dw6 = (64 - 2) << GEN8_PS_DW6_MAX_THREADS__SHIFT |
-         GEN8_PS_DW6_POSOFFSET_NONE;
+         GEN6_POSOFFSET_NONE << GEN8_PS_DW6_POSOFFSET__SHIFT;
    if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE))
       dw6 |= GEN8_PS_DW6_PUSH_CONSTANT_ENABLE;
 
@@ -1604,13 +1604,13 @@ blend_init_cso_gen6(const struct ilo_dev *dev,
                      GEN6_RT_DW1_POST_BLEND_CLAMP;
 
    if (!(rt->colormask & PIPE_MASK_A))
-      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_A;
+      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_A;
    if (!(rt->colormask & PIPE_MASK_R))
-      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_R;
+      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_R;
    if (!(rt->colormask & PIPE_MASK_G))
-      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_G;
+      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_G;
    if (!(rt->colormask & PIPE_MASK_B))
-      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLE_B;
+      cso->payload[1] |= GEN6_RT_DW1_WRITE_DISABLES_B;
 
    /*
     * From the Sandy Bridge PRM, volume 2 part 1, page 365:
@@ -1649,13 +1649,13 @@ blend_init_cso_gen8(const struct ilo_dev *dev,
                      GEN8_RT_DW1_POST_BLEND_CLAMP;
 
    if (!(rt->colormask & PIPE_MASK_A))
-      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_A;
+      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_A;
    if (!(rt->colormask & PIPE_MASK_R))
-      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_R;
+      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_R;
    if (!(rt->colormask & PIPE_MASK_G))
-      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_G;
+      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_G;
    if (!(rt->colormask & PIPE_MASK_B))
-      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLE_B;
+      cso->payload[0] |= GEN8_RT_DW0_WRITE_DISABLES_B;
 
    if (state->logicop_enable) {
       cso->dw_blend = 0;
diff --git a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
index 24d726adcb3..5a0bb4f8d77 100644
--- a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
@@ -97,6 +97,9 @@ enum gen_mi_alu_operand {
 #define GEN6_MI_LENGTH__MASK					0x0000003f
 #define GEN6_MI_LENGTH__SHIFT					0
 #define GEN6_MI_NOOP__SIZE					1
+#define GEN6_MI_NOOP_DW0_WRITE_NOPID				(0x1 << 22)
+#define GEN6_MI_NOOP_DW0_VALUE__MASK				0x003fffff
+#define GEN6_MI_NOOP_DW0_VALUE__SHIFT				0
 
 #define GEN75_MI_SET_PREDICATE__SIZE				1
 #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK		0x00000003
diff --git a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
index 2bdd72b29bc..c51e4f78bc0 100644
--- a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
@@ -35,6 +35,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_REG_MASK__MASK					0xffff0000
 #define GEN6_REG_MASK__SHIFT					16
 #define GEN6_REG__SIZE						0x400000
+#define GEN6_REG_NOPID						0x2094
+
 #define GEN7_REG_HS_INVOCATION_COUNT				0x2300
 
 #define GEN7_REG_DS_INVOCATION_COUNT				0x2308
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
index d25542e8cc2..1abfef987b5 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
@@ -32,7 +32,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
 
-enum gen_prim_type {
+enum gen_3dprim_type {
     GEN6_3DPRIM_POINTLIST				      = 0x1,
     GEN6_3DPRIM_LINELIST				      = 0x2,
     GEN6_3DPRIM_LINESTRIP				      = 0x3,
@@ -123,6 +123,87 @@ enum gen_depth_format {
     GEN6_ZFORMAT_D16_UNORM				      = 0x5,
 };
 
+enum gen_reorder_mode {
+    GEN7_REORDER_LEADING				      = 0x0,
+    GEN7_REORDER_TRAILING				      = 0x1,
+};
+
+enum gen_clip_mode {
+    GEN6_CLIPMODE_NORMAL				      = 0x0,
+    GEN6_CLIPMODE_REJECT_ALL				      = 0x3,
+    GEN6_CLIPMODE_ACCEPT_ALL				      = 0x4,
+};
+
+enum gen_front_winding {
+    GEN6_FRONTWINDING_CW				      = 0x0,
+    GEN6_FRONTWINDING_CCW				      = 0x1,
+};
+
+enum gen_fill_mode {
+    GEN6_FILLMODE_SOLID					      = 0x0,
+    GEN6_FILLMODE_WIREFRAME				      = 0x1,
+    GEN6_FILLMODE_POINT					      = 0x2,
+};
+
+enum gen_cull_mode {
+    GEN6_CULLMODE_BOTH					      = 0x0,
+    GEN6_CULLMODE_NONE					      = 0x1,
+    GEN6_CULLMODE_FRONT					      = 0x2,
+    GEN6_CULLMODE_BACK					      = 0x3,
+};
+
+enum gen_pixel_location {
+    GEN6_PIXLOC_CENTER					      = 0x0,
+    GEN6_PIXLOC_UL_CORNER				      = 0x1,
+};
+
+enum gen_sample_count {
+    GEN6_NUMSAMPLES_1					      = 0x0,
+    GEN8_NUMSAMPLES_2					      = 0x1,
+    GEN6_NUMSAMPLES_4					      = 0x2,
+    GEN7_NUMSAMPLES_8					      = 0x3,
+    GEN8_NUMSAMPLES_16					      = 0x4,
+};
+
+enum gen_inputattr_select {
+    GEN6_INPUTATTR_NORMAL				      = 0x0,
+    GEN6_INPUTATTR_FACING				      = 0x1,
+    GEN6_INPUTATTR_W					      = 0x2,
+    GEN6_INPUTATTR_FACING_W				      = 0x3,
+};
+
+enum gen_zw_interp {
+    GEN6_ZW_INTERP_PIXEL				      = 0x0,
+    GEN6_ZW_INTERP_CENTROID				      = 0x2,
+    GEN6_ZW_INTERP_SAMPLE				      = 0x3,
+};
+
+enum gen_position_offset {
+    GEN6_POSOFFSET_NONE					      = 0x0,
+    GEN6_POSOFFSET_CENTROID				      = 0x2,
+    GEN6_POSOFFSET_SAMPLE				      = 0x3,
+};
+
+enum gen_edsc_mode {
+    GEN7_EDSC_NORMAL					      = 0x0,
+    GEN7_EDSC_PSEXEC					      = 0x1,
+    GEN7_EDSC_PREPS					      = 0x2,
+};
+
+enum gen_pscdepth_mode {
+    GEN7_PSCDEPTH_OFF					      = 0x0,
+    GEN7_PSCDEPTH_ON					      = 0x1,
+    GEN7_PSCDEPTH_ON_GE					      = 0x2,
+    GEN7_PSCDEPTH_ON_LE					      = 0x3,
+};
+
+enum gen_msrast_mode {
+    GEN6_MSRASTMODE_OFF_PIXEL				      = 0x0,
+    GEN6_MSRASTMODE_OFF_PATTERN				      = 0x1,
+    GEN6_MSRASTMODE_ON_PIXEL				      = 0x2,
+    GEN6_MSRASTMODE_ON_PATTERN				      = 0x3,
+};
+
 #define GEN6_INTERP_NONPERSPECTIVE_SAMPLE			(0x1 << 5)
 #define GEN6_INTERP_NONPERSPECTIVE_CENTROID			(0x1 << 4)
 #define GEN6_INTERP_NONPERSPECTIVE_PIXEL			(0x1 << 3)
@@ -614,7 +695,7 @@ enum gen_depth_format {
 #define GEN6_GS_DW5_SO_STATISTICS				(0x1 << 9)
 #define GEN6_GS_DW5_RENDER_ENABLE				(0x1 << 8)
 
-#define GEN6_GS_DW6_REORDER_ENABLE				(0x1 << 30)
+#define GEN6_GS_DW6_REORDER_LEADING_ENABLE			(0x1 << 30)
 #define GEN6_GS_DW6_DISCARD_ADJACENCY				(0x1 << 29)
 #define GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE				(0x1 << 28)
 #define GEN6_GS_DW6_SVBI_POST_INC_ENABLE			(0x1 << 27)
@@ -666,11 +747,9 @@ enum gen_depth_format {
 #define GEN7_GS_DW5_INVOCATION_INCR__SHIFT			5
 #define GEN7_GS_DW5_INCLUDE_PRIMITIVE_ID			(0x1 << 4)
 #define GEN7_GS_DW5_HINT					(0x1 << 3)
-#define GEN7_GS_DW5_REORDER_ENABLE				(0x1 << 2)
-#define GEN75_GS_DW5_REORDER__MASK				0x00000004
-#define GEN75_GS_DW5_REORDER__SHIFT				2
-#define GEN75_GS_DW5_REORDER_LEADING				(0x0 << 2)
-#define GEN75_GS_DW5_REORDER_TRAILING				(0x1 << 2)
+#define GEN7_GS_DW5_REORDER_LEADING_ENABLE			(0x1 << 2)
+#define GEN75_GS_DW5_REORDER_MODE__MASK				0x00000004
+#define GEN75_GS_DW5_REORDER_MODE__SHIFT			2
 #define GEN7_GS_DW5_DISCARD_ADJACENCY				(0x1 << 1)
 #define GEN7_GS_DW5_GS_ENABLE					(0x1 << 0)
 
@@ -727,10 +806,8 @@ enum gen_depth_format {
 #define GEN8_GS_DW7_INVOCATION_INCR__SHIFT			5
 #define GEN8_GS_DW7_INCLUDE_PRIMITIVE_ID			(0x1 << 4)
 #define GEN8_GS_DW7_HINT					(0x1 << 3)
-#define GEN8_GS_DW7_REORDER__MASK				0x00000004
-#define GEN8_GS_DW7_REORDER__SHIFT				2
-#define GEN8_GS_DW7_REORDER_LEADING				(0x0 << 2)
-#define GEN8_GS_DW7_REORDER_TRAILING				(0x1 << 2)
+#define GEN8_GS_DW7_REORDER_MODE__MASK				0x00000004
+#define GEN8_GS_DW7_REORDER_MODE__SHIFT				2
 #define GEN8_GS_DW7_DISCARD_ADJACENCY				(0x1 << 1)
 #define GEN8_GS_DW7_GS_ENABLE					(0x1 << 0)
 
@@ -758,10 +835,8 @@ enum gen_depth_format {
 #define GEN7_SO_DW1_RENDER_DISABLE				(0x1 << 30)
 #define GEN7_SO_DW1_RENDER_STREAM_SELECT__MASK			0x18000000
 #define GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT			27
-#define GEN7_SO_DW1_REORDER__MASK				0x04000000
-#define GEN7_SO_DW1_REORDER__SHIFT				26
-#define GEN7_SO_DW1_REORDER_LEADING				(0x0 << 26)
-#define GEN7_SO_DW1_REORDER_TRAILING				(0x1 << 26)
+#define GEN7_SO_DW1_REORDER_MODE__MASK				0x04000000
+#define GEN7_SO_DW1_REORDER_MODE__SHIFT				26
 #define GEN7_SO_DW1_STATISTICS					(0x1 << 25)
 #define GEN7_SO_DW1_BUFFER_ENABLES__MASK			0x00000f00
 #define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT			8
@@ -862,21 +937,15 @@ enum gen_depth_format {
 #define GEN6_3DSTATE_CLIP__SIZE					4
 
 
-#define GEN7_CLIP_DW1_FRONTWINDING__MASK			0x00100000
-#define GEN7_CLIP_DW1_FRONTWINDING__SHIFT			20
-#define GEN7_CLIP_DW1_FRONTWINDING_CW				(0x0 << 20)
-#define GEN7_CLIP_DW1_FRONTWINDING_CCW				(0x1 << 20)
+#define GEN7_CLIP_DW1_FRONT_WINDING__MASK			0x00100000
+#define GEN7_CLIP_DW1_FRONT_WINDING__SHIFT			20
 #define GEN7_CLIP_DW1_SUBPIXEL__MASK				0x00080000
 #define GEN7_CLIP_DW1_SUBPIXEL__SHIFT				19
 #define GEN7_CLIP_DW1_SUBPIXEL_8BITS				(0x0 << 19)
 #define GEN7_CLIP_DW1_SUBPIXEL_4BITS				(0x1 << 19)
 #define GEN7_CLIP_DW1_EARLY_CULL_ENABLE				(0x1 << 18)
-#define GEN7_CLIP_DW1_CULLMODE__MASK				0x00030000
-#define GEN7_CLIP_DW1_CULLMODE__SHIFT				16
-#define GEN7_CLIP_DW1_CULLMODE_BOTH				(0x0 << 16)
-#define GEN7_CLIP_DW1_CULLMODE_NONE				(0x1 << 16)
-#define GEN7_CLIP_DW1_CULLMODE_FRONT				(0x2 << 16)
-#define GEN7_CLIP_DW1_CULLMODE_BACK				(0x3 << 16)
+#define GEN7_CLIP_DW1_CULL_MODE__MASK				0x00030000
+#define GEN7_CLIP_DW1_CULL_MODE__SHIFT				16
 #define GEN6_CLIP_DW1_STATISTICS				(0x1 << 10)
 #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK			0x000000ff
 #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT			0
@@ -891,11 +960,8 @@ enum gen_depth_format {
 #define GEN6_CLIP_DW2_GB_TEST_ENABLE				(0x1 << 26)
 #define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__MASK			0x00ff0000
 #define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT			16
-#define GEN6_CLIP_DW2_CLIPMODE__MASK				0x0000e000
-#define GEN6_CLIP_DW2_CLIPMODE__SHIFT				13
-#define GEN6_CLIP_DW2_CLIPMODE_NORMAL				(0x0 << 13)
-#define GEN6_CLIP_DW2_CLIPMODE_REJECT_ALL			(0x3 << 13)
-#define GEN6_CLIP_DW2_CLIPMODE_ACCEPT_ALL			(0x4 << 13)
+#define GEN6_CLIP_DW2_CLIP_MODE__MASK				0x0000e000
+#define GEN6_CLIP_DW2_CLIP_MODE__SHIFT				13
 #define GEN6_CLIP_DW2_PERSPECTIVE_DIVIDE_DISABLE		(0x1 << 9)
 #define GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE		(0x1 << 8)
 #define GEN6_CLIP_DW2_TRI_PROVOKE__MASK				0x00000030
@@ -911,7 +977,7 @@ enum gen_depth_format {
 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__MASK			0x0001ffc0
 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT			6
 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__RADIX			3
-#define GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO			(0x1 << 5)
+#define GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO			(0x1 << 5)
 #define GEN6_CLIP_DW3_MAX_VPINDEX__MASK				0x0000000f
 #define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT			0
 
@@ -927,29 +993,17 @@ enum gen_depth_format {
 #define GEN7_SF_DW1_DEPTH_OFFSET_SOLID				(0x1 << 9)
 #define GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME			(0x1 << 8)
 #define GEN7_SF_DW1_DEPTH_OFFSET_POINT				(0x1 << 7)
-#define GEN7_SF_DW1_FRONTFACE__MASK				0x00000060
-#define GEN7_SF_DW1_FRONTFACE__SHIFT				5
-#define GEN7_SF_DW1_FRONTFACE_SOLID				(0x0 << 5)
-#define GEN7_SF_DW1_FRONTFACE_WIREFRAME				(0x1 << 5)
-#define GEN7_SF_DW1_FRONTFACE_POINT				(0x2 << 5)
-#define GEN7_SF_DW1_BACKFACE__MASK				0x00000018
-#define GEN7_SF_DW1_BACKFACE__SHIFT				3
-#define GEN7_SF_DW1_BACKFACE_SOLID				(0x0 << 3)
-#define GEN7_SF_DW1_BACKFACE_WIREFRAME				(0x1 << 3)
-#define GEN7_SF_DW1_BACKFACE_POINT				(0x2 << 3)
-#define GEN7_SF_DW1_VIEWPORT_ENABLE				(0x1 << 1)
-#define GEN7_SF_DW1_FRONTWINDING__MASK				0x00000001
-#define GEN7_SF_DW1_FRONTWINDING__SHIFT				0
-#define GEN7_SF_DW1_FRONTWINDING_CW				0x0
-#define GEN7_SF_DW1_FRONTWINDING_CCW				0x1
+#define GEN7_SF_DW1_FILL_MODE_FRONT__MASK			0x00000060
+#define GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT			5
+#define GEN7_SF_DW1_FILL_MODE_BACK__MASK			0x00000018
+#define GEN7_SF_DW1_FILL_MODE_BACK__SHIFT			3
+#define GEN7_SF_DW1_VIEWPORT_TRANSFORM				(0x1 << 1)
+#define GEN7_SF_DW1_FRONT_WINDING__MASK				0x00000001
+#define GEN7_SF_DW1_FRONT_WINDING__SHIFT			0
 
 #define GEN7_SF_DW2_AA_LINE_ENABLE				(0x1 << 31)
-#define GEN7_SF_DW2_CULLMODE__MASK				0x60000000
-#define GEN7_SF_DW2_CULLMODE__SHIFT				29
-#define GEN7_SF_DW2_CULLMODE_BOTH				(0x0 << 29)
-#define GEN7_SF_DW2_CULLMODE_NONE				(0x1 << 29)
-#define GEN7_SF_DW2_CULLMODE_FRONT				(0x2 << 29)
-#define GEN7_SF_DW2_CULLMODE_BACK				(0x3 << 29)
+#define GEN7_SF_DW2_CULL_MODE__MASK				0x60000000
+#define GEN7_SF_DW2_CULL_MODE__SHIFT				29
 #define GEN7_SF_DW2_LINE_WIDTH__MASK				0x0ffc0000
 #define GEN7_SF_DW2_LINE_WIDTH__SHIFT				18
 #define GEN7_SF_DW2_LINE_WIDTH__RADIX				7
@@ -963,10 +1017,6 @@ enum gen_depth_format {
 #define GEN7_SF_DW2_SCISSOR_ENABLE				(0x1 << 11)
 #define GEN7_SF_DW2_MSRASTMODE__MASK				0x00000300
 #define GEN7_SF_DW2_MSRASTMODE__SHIFT				8
-#define GEN7_SF_DW2_MSRASTMODE_OFF_PIXEL			(0x0 << 8)
-#define GEN7_SF_DW2_MSRASTMODE_OFF_PATTERN			(0x1 << 8)
-#define GEN7_SF_DW2_MSRASTMODE_ON_PIXEL				(0x2 << 8)
-#define GEN7_SF_DW2_MSRASTMODE_ON_PATTERN			(0x3 << 8)
 
 #define GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE			(0x1 << 31)
 #define GEN7_SF_DW3_TRI_PROVOKE__MASK				0x60000000
@@ -1021,14 +1071,10 @@ enum gen_depth_format {
 #define GEN8_SBE_SWIZ_CONST_0001_FLOAT				(0x1 << 9)
 #define GEN8_SBE_SWIZ_CONST_1111_FLOAT				(0x2 << 9)
 #define GEN8_SBE_SWIZ_CONST_PRIM_ID				(0x3 << 9)
-#define GEN8_SBE_SWIZ_INPUTATTR__MASK				0x000000c0
-#define GEN8_SBE_SWIZ_INPUTATTR__SHIFT				6
-#define GEN8_SBE_SWIZ_INPUTATTR_NORMAL				(0x0 << 6)
-#define GEN8_SBE_SWIZ_INPUTATTR_FACING				(0x1 << 6)
-#define GEN8_SBE_SWIZ_INPUTATTR_W				(0x2 << 6)
-#define GEN8_SBE_SWIZ_INPUTATTR_FACING_W			(0x3 << 6)
-#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__MASK			0x0000001f
-#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__SHIFT			0
+#define GEN8_SBE_SWIZ_SWIZZLE_SELECT__MASK			0x000000c0
+#define GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT			6
+#define GEN8_SBE_SWIZ_SRC_ATTR__MASK				0x0000001f
+#define GEN8_SBE_SWIZ_SRC_ATTR__SHIFT				0
 
 #define GEN6_3DSTATE_SF__SIZE					20
 
@@ -1080,31 +1126,19 @@ enum gen_depth_format {
 
 
 #define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE			(0x1 << 26)
-#define GEN8_RASTER_DW1_FRONTWINDING__MASK			0x00200000
-#define GEN8_RASTER_DW1_FRONTWINDING__SHIFT			21
-#define GEN8_RASTER_DW1_FRONTWINDING_CW				(0x0 << 21)
-#define GEN8_RASTER_DW1_FRONTWINDING_CCW			(0x1 << 21)
-#define GEN8_RASTER_DW1_CULLMODE__MASK				0x00030000
-#define GEN8_RASTER_DW1_CULLMODE__SHIFT				16
-#define GEN8_RASTER_DW1_CULLMODE_BOTH				(0x0 << 16)
-#define GEN8_RASTER_DW1_CULLMODE_NONE				(0x1 << 16)
-#define GEN8_RASTER_DW1_CULLMODE_FRONT				(0x2 << 16)
-#define GEN8_RASTER_DW1_CULLMODE_BACK				(0x3 << 16)
+#define GEN8_RASTER_DW1_FRONT_WINDING__MASK			0x00200000
+#define GEN8_RASTER_DW1_FRONT_WINDING__SHIFT			21
+#define GEN8_RASTER_DW1_CULL_MODE__MASK				0x00030000
+#define GEN8_RASTER_DW1_CULL_MODE__SHIFT			16
 #define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE			(0x1 << 13)
 #define GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE			(0x1 << 12)
 #define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID			(0x1 << 9)
 #define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME			(0x1 << 8)
 #define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT			(0x1 << 7)
-#define GEN8_RASTER_DW1_FRONTFACE__MASK				0x00000060
-#define GEN8_RASTER_DW1_FRONTFACE__SHIFT			5
-#define GEN8_RASTER_DW1_FRONTFACE_SOLID				(0x0 << 5)
-#define GEN8_RASTER_DW1_FRONTFACE_WIREFRAME			(0x1 << 5)
-#define GEN8_RASTER_DW1_FRONTFACE_POINT				(0x2 << 5)
-#define GEN8_RASTER_DW1_BACKFACE__MASK				0x00000018
-#define GEN8_RASTER_DW1_BACKFACE__SHIFT				3
-#define GEN8_RASTER_DW1_BACKFACE_SOLID				(0x0 << 3)
-#define GEN8_RASTER_DW1_BACKFACE_WIREFRAME			(0x1 << 3)
-#define GEN8_RASTER_DW1_BACKFACE_POINT				(0x2 << 3)
+#define GEN8_RASTER_DW1_FILL_MODE_FRONT__MASK			0x00000060
+#define GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT			5
+#define GEN8_RASTER_DW1_FILL_MODE_BACK__MASK			0x00000018
+#define GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT			3
 #define GEN8_RASTER_DW1_AA_LINE_ENABLE				(0x1 << 2)
 #define GEN8_RASTER_DW1_SCISSOR_ENABLE				(0x1 << 1)
 #define GEN8_RASTER_DW1_Z_TEST_ENABLE				(0x1 << 0)
@@ -1164,14 +1198,8 @@ enum gen_depth_format {
 #define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT			20
 #define GEN6_WM_DW6_PS_POSOFFSET__MASK				0x000c0000
 #define GEN6_WM_DW6_PS_POSOFFSET__SHIFT				18
-#define GEN6_WM_DW6_PS_POSOFFSET_NONE				(0x0 << 18)
-#define GEN6_WM_DW6_PS_POSOFFSET_CENTROID			(0x2 << 18)
-#define GEN6_WM_DW6_PS_POSOFFSET_SAMPLE				(0x3 << 18)
 #define GEN6_WM_DW6_ZW_INTERP__MASK				0x00030000
 #define GEN6_WM_DW6_ZW_INTERP__SHIFT				16
-#define GEN6_WM_DW6_ZW_INTERP_PIXEL				(0x0 << 16)
-#define GEN6_WM_DW6_ZW_INTERP_CENTROID				(0x2 << 16)
-#define GEN6_WM_DW6_ZW_INTERP_SAMPLE				(0x3 << 16)
 #define GEN6_WM_DW6_BARYCENTRIC_INTERP__MASK			0x0000fc00
 #define GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT			10
 #define GEN6_WM_DW6_POINT_RASTRULE__MASK			0x00000200
@@ -1180,10 +1208,6 @@ enum gen_depth_format {
 #define GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT			(0x1 << 9)
 #define GEN6_WM_DW6_MSRASTMODE__MASK				0x00000006
 #define GEN6_WM_DW6_MSRASTMODE__SHIFT				1
-#define GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL			(0x0 << 1)
-#define GEN6_WM_DW6_MSRASTMODE_OFF_PATTERN			(0x1 << 1)
-#define GEN6_WM_DW6_MSRASTMODE_ON_PIXEL				(0x2 << 1)
-#define GEN6_WM_DW6_MSRASTMODE_ON_PATTERN			(0x3 << 1)
 #define GEN6_WM_DW6_MSDISPMODE__MASK				0x00000001
 #define GEN6_WM_DW6_MSDISPMODE__SHIFT				0
 #define GEN6_WM_DW6_MSDISPMODE_PERSAMPLE			0x0
@@ -1207,22 +1231,12 @@ enum gen_depth_format {
 #define GEN7_WM_DW1_PS_KILL_PIXEL				(0x1 << 25)
 #define GEN7_WM_DW1_PSCDEPTH__MASK				0x01800000
 #define GEN7_WM_DW1_PSCDEPTH__SHIFT				23
-#define GEN7_WM_DW1_PSCDEPTH_OFF				(0x0 << 23)
-#define GEN7_WM_DW1_PSCDEPTH_ON					(0x1 << 23)
-#define GEN7_WM_DW1_PSCDEPTH_ON_GE				(0x2 << 23)
-#define GEN7_WM_DW1_PSCDEPTH_ON_LE				(0x3 << 23)
 #define GEN7_WM_DW1_EDSC__MASK					0x00600000
 #define GEN7_WM_DW1_EDSC__SHIFT					21
-#define GEN7_WM_DW1_EDSC_NORMAL					(0x0 << 21)
-#define GEN7_WM_DW1_EDSC_PSEXEC					(0x1 << 21)
-#define GEN7_WM_DW1_EDSC_PREPS					(0x2 << 21)
 #define GEN7_WM_DW1_PS_USE_DEPTH				(0x1 << 20)
 #define GEN7_WM_DW1_PS_USE_W					(0x1 << 19)
 #define GEN7_WM_DW1_ZW_INTERP__MASK				0x00060000
 #define GEN7_WM_DW1_ZW_INTERP__SHIFT				17
-#define GEN7_WM_DW1_ZW_INTERP_PIXEL				(0x0 << 17)
-#define GEN7_WM_DW1_ZW_INTERP_CENTROID				(0x2 << 17)
-#define GEN7_WM_DW1_ZW_INTERP_SAMPLE				(0x3 << 17)
 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK			0x0001f800
 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT			11
 #define GEN7_WM_DW1_PS_USE_COVERAGE_MASK			(0x1 << 10)
@@ -1247,10 +1261,6 @@ enum gen_depth_format {
 #define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT			(0x1 << 2)
 #define GEN7_WM_DW1_MSRASTMODE__MASK				0x00000003
 #define GEN7_WM_DW1_MSRASTMODE__SHIFT				0
-#define GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL			0x0
-#define GEN7_WM_DW1_MSRASTMODE_OFF_PATTERN			0x1
-#define GEN7_WM_DW1_MSRASTMODE_ON_PIXEL				0x2
-#define GEN7_WM_DW1_MSRASTMODE_ON_PATTERN			0x3
 
 #define GEN7_WM_DW2_MSDISPMODE__MASK				0x80000000
 #define GEN7_WM_DW2_MSDISPMODE__SHIFT				31
@@ -1265,12 +1275,12 @@ enum gen_depth_format {
 #define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE			4
 
 
-#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__MASK			0xe0000000
-#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__SHIFT			29
-#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__MASK			0x1c000000
-#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__SHIFT			26
-#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__MASK			0x03800000
-#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__SHIFT			23
+#define GEN8_ZS_DW1_STENCIL_FAIL_OP__MASK			0xe0000000
+#define GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT			29
+#define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__MASK			0x1c000000
+#define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__SHIFT			26
+#define GEN8_ZS_DW1_STENCIL_ZPASS_OP__MASK			0x03800000
+#define GEN8_ZS_DW1_STENCIL_ZPASS_OP__SHIFT			23
 #define GEN8_ZS_DW1_STENCIL1_FUNC__MASK				0x00700000
 #define GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT			20
 #define GEN8_ZS_DW1_STENCIL1_FAIL_OP__MASK			0x000e0000
@@ -1279,8 +1289,8 @@ enum gen_depth_format {
 #define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT			14
 #define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__MASK			0x00003800
 #define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT			11
-#define GEN8_ZS_DW1_STENCIL0_FUNC__MASK				0x00000700
-#define GEN8_ZS_DW1_STENCIL0_FUNC__SHIFT			8
+#define GEN8_ZS_DW1_STENCIL_FUNC__MASK				0x00000700
+#define GEN8_ZS_DW1_STENCIL_FUNC__SHIFT				8
 #define GEN8_ZS_DW1_DEPTH_FUNC__MASK				0x000000e0
 #define GEN8_ZS_DW1_DEPTH_FUNC__SHIFT				5
 #define GEN8_ZS_DW1_STENCIL1_ENABLE				(0x1 << 4)
@@ -1289,17 +1299,17 @@ enum gen_depth_format {
 #define GEN8_ZS_DW1_DEPTH_TEST_ENABLE				(0x1 << 1)
 #define GEN8_ZS_DW1_DEPTH_WRITE_ENABLE				(0x1 << 0)
 
-#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__MASK			0xff000000
-#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__SHIFT			24
-#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__MASK			0x00ff0000
-#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__SHIFT			16
-#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__MASK			0x0000ff00
-#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__SHIFT			8
-#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__MASK			0x000000ff
-#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__SHIFT			0
-
-#define GEN9_ZS_DW3_STENCIL0_REF__MASK				0x0000ff00
-#define GEN9_ZS_DW3_STENCIL0_REF__SHIFT				8
+#define GEN8_ZS_DW2_STENCIL_TEST_MASK__MASK			0xff000000
+#define GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT			24
+#define GEN8_ZS_DW2_STENCIL_WRITE_MASK__MASK			0x00ff0000
+#define GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT			16
+#define GEN8_ZS_DW2_STENCIL1_TEST_MASK__MASK			0x0000ff00
+#define GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT			8
+#define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__MASK			0x000000ff
+#define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT			0
+
+#define GEN9_ZS_DW3_STENCIL_REF__MASK				0x0000ff00
+#define GEN9_ZS_DW3_STENCIL_REF__SHIFT				8
 #define GEN9_ZS_DW3_STENCIL1_REF__MASK				0x000000ff
 #define GEN9_ZS_DW3_STENCIL1_REF__SHIFT				0
 
@@ -1314,13 +1324,8 @@ enum gen_depth_format {
 #define GEN8_WM_HZ_DW1_FULL_SURFACE_DEPTH_CLEAR			(0x1 << 25)
 #define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__MASK		0x00ff0000
 #define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__SHIFT		16
-#define GEN8_WM_HZ_DW1_NUMSAMPLES__MASK				0x0000e000
-#define GEN8_WM_HZ_DW1_NUMSAMPLES__SHIFT			13
-#define GEN8_WM_HZ_DW1_NUMSAMPLES_1				(0x0 << 13)
-#define GEN8_WM_HZ_DW1_NUMSAMPLES_2				(0x1 << 13)
-#define GEN8_WM_HZ_DW1_NUMSAMPLES_4				(0x2 << 13)
-#define GEN8_WM_HZ_DW1_NUMSAMPLES_8				(0x3 << 13)
-#define GEN8_WM_HZ_DW1_NUMSAMPLES_16				(0x4 << 13)
+#define GEN8_WM_HZ_DW1_NUM_SAMPLES__MASK			0x0000e000
+#define GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT			13
 
 #define GEN8_WM_HZ_DW2_RECT_MIN_Y__MASK				0xffff0000
 #define GEN8_WM_HZ_DW2_RECT_MIN_Y__SHIFT			16
@@ -1359,9 +1364,6 @@ enum gen_depth_format {
 #define GEN75_PS_DW4_ACCESS_UAV					(0x1 << 5)
 #define GEN7_PS_DW4_POSOFFSET__MASK				0x00000018
 #define GEN7_PS_DW4_POSOFFSET__SHIFT				3
-#define GEN7_PS_DW4_POSOFFSET_NONE				(0x0 << 3)
-#define GEN7_PS_DW4_POSOFFSET_CENTROID				(0x2 << 3)
-#define GEN7_PS_DW4_POSOFFSET_SAMPLE				(0x3 << 3)
 #define GEN7_PS_DW4_DISPATCH_MODE__MASK				0x00000007
 #define GEN7_PS_DW4_DISPATCH_MODE__SHIFT			0
 
@@ -1397,9 +1399,6 @@ enum gen_depth_format {
 #define GEN8_PS_DW6_RT_RESOLVE					(0x1 << 6)
 #define GEN8_PS_DW6_POSOFFSET__MASK				0x00000018
 #define GEN8_PS_DW6_POSOFFSET__SHIFT				3
-#define GEN8_PS_DW6_POSOFFSET_NONE				(0x0 << 3)
-#define GEN8_PS_DW6_POSOFFSET_CENTROID				(0x2 << 3)
-#define GEN8_PS_DW6_POSOFFSET_SAMPLE				(0x3 << 3)
 #define GEN8_PS_DW6_DISPATCH_MODE__MASK				0x00000007
 #define GEN8_PS_DW6_DISPATCH_MODE__SHIFT			0
 
@@ -1423,16 +1422,12 @@ enum gen_depth_format {
 #define GEN8_3DSTATE_PS_EXTRA__SIZE				2
 
 
-#define GEN8_PSX_DW1_DISPATCH_ENABLE				(0x1 << 31)
+#define GEN8_PSX_DW1_VALID					(0x1 << 31)
 #define GEN8_PSX_DW1_UAV_ONLY					(0x1 << 30)
 #define GEN8_PSX_DW1_COMPUTE_OMASK				(0x1 << 29)
 #define GEN8_PSX_DW1_KILL_PIXEL					(0x1 << 28)
 #define GEN8_PSX_DW1_PSCDEPTH__MASK				0x0c000000
 #define GEN8_PSX_DW1_PSCDEPTH__SHIFT				26
-#define GEN8_PSX_DW1_PSCDEPTH_OFF				(0x0 << 26)
-#define GEN8_PSX_DW1_PSCDEPTH_ON				(0x1 << 26)
-#define GEN8_PSX_DW1_PSCDEPTH_ON_GE				(0x2 << 26)
-#define GEN8_PSX_DW1_PSCDEPTH_ON_LE				(0x3 << 26)
 #define GEN8_PSX_DW1_FORCE_COMPUTE_DEPTH			(0x1 << 25)
 #define GEN8_PSX_DW1_USE_DEPTH					(0x1 << 24)
 #define GEN8_PSX_DW1_USE_W					(0x1 << 23)
@@ -1696,17 +1691,10 @@ enum gen_depth_format {
 
 
 #define GEN75_MULTISAMPLE_DW1_DX9_MULTISAMPLE_ENABLE		(0x1 << 5)
-#define GEN6_MULTISAMPLE_DW1_PIXLOC__MASK			0x00000010
-#define GEN6_MULTISAMPLE_DW1_PIXLOC__SHIFT			4
-#define GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER			(0x0 << 4)
-#define GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER			(0x1 << 4)
-#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__MASK			0x0000000e
-#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__SHIFT			1
-#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1			(0x0 << 1)
-#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_2			(0x1 << 1)
-#define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4			(0x2 << 1)
-#define GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8			(0x3 << 1)
-#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_16			(0x4 << 1)
+#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__MASK		0x00000010
+#define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT		4
+#define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__MASK			0x0000000e
+#define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT			1
 
 
 
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
index 6d815beecb3..b65b704adc6 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
@@ -84,7 +84,7 @@ enum gen_blend_function {
     GEN6_BLENDFUNCTION_MAX				      = 0x4,
 };
 
-enum gen_logicop_function {
+enum gen_logic_op {
     GEN6_LOGICOP_CLEAR					      = 0x0,
     GEN6_LOGICOP_NOR					      = 0x1,
     GEN6_LOGICOP_AND_INVERTED				      = 0x2,
@@ -103,20 +103,31 @@ enum gen_logicop_function {
     GEN6_LOGICOP_SET					      = 0xf,
 };
 
-enum gen_sampler_mip_filter {
+enum gen_mip_filter {
     GEN6_MIPFILTER_NONE					      = 0x0,
     GEN6_MIPFILTER_NEAREST				      = 0x1,
     GEN6_MIPFILTER_LINEAR				      = 0x3,
 };
 
-enum gen_sampler_map_filter {
+enum gen_map_filter {
     GEN6_MAPFILTER_NEAREST				      = 0x0,
     GEN6_MAPFILTER_LINEAR				      = 0x1,
     GEN6_MAPFILTER_ANISOTROPIC				      = 0x2,
     GEN6_MAPFILTER_MONO					      = 0x6,
 };
 
-enum gen_sampler_aniso_ratio {
+enum gen_prefilter_op {
+    GEN6_PREFILTEROP_ALWAYS				      = 0x0,
+    GEN6_PREFILTEROP_NEVER				      = 0x1,
+    GEN6_PREFILTEROP_LESS				      = 0x2,
+    GEN6_PREFILTEROP_EQUAL				      = 0x3,
+    GEN6_PREFILTEROP_LEQUAL				      = 0x4,
+    GEN6_PREFILTEROP_GREATER				      = 0x5,
+    GEN6_PREFILTEROP_NOTEQUAL				      = 0x6,
+    GEN6_PREFILTEROP_GEQUAL				      = 0x7,
+};
+
+enum gen_aniso_ratio {
     GEN6_ANISORATIO_2					      = 0x0,
     GEN6_ANISORATIO_4					      = 0x1,
     GEN6_ANISORATIO_6					      = 0x2,
@@ -127,7 +138,7 @@ enum gen_sampler_aniso_ratio {
     GEN6_ANISORATIO_16					      = 0x7,
 };
 
-enum gen_sampler_texcoord_mode {
+enum gen_texcoord_mode {
     GEN6_TEXCOORDMODE_WRAP				      = 0x0,
     GEN6_TEXCOORDMODE_MIRROR				      = 0x1,
     GEN6_TEXCOORDMODE_CLAMP				      = 0x2,
@@ -137,15 +148,15 @@ enum gen_sampler_texcoord_mode {
     GEN8_TEXCOORDMODE_HALF_BORDER			      = 0x6,
 };
 
-enum gen_sampler_key_filter {
+enum gen_key_filter {
     GEN6_KEYFILTER_KILL_ON_ANY_MATCH			      = 0x0,
     GEN6_KEYFILTER_REPLACE_BLACK			      = 0x1,
 };
 
 #define GEN6_COLOR_CALC_STATE__SIZE				6
 
-#define GEN6_CC_DW0_STENCIL0_REF__MASK				0xff000000
-#define GEN6_CC_DW0_STENCIL0_REF__SHIFT				24
+#define GEN6_CC_DW0_STENCIL_REF__MASK				0xff000000
+#define GEN6_CC_DW0_STENCIL_REF__SHIFT				24
 #define GEN6_CC_DW0_STENCIL1_REF__MASK				0x00ff0000
 #define GEN6_CC_DW0_STENCIL1_REF__SHIFT				16
 #define GEN6_CC_DW0_ROUND_DISABLE_DISABLE			(0x1 << 15)
@@ -162,14 +173,14 @@ enum gen_sampler_key_filter {
 #define GEN6_DEPTH_STENCIL_STATE__SIZE				3
 
 #define GEN6_ZS_DW0_STENCIL_TEST_ENABLE				(0x1 << 31)
-#define GEN6_ZS_DW0_STENCIL0_FUNC__MASK				0x70000000
-#define GEN6_ZS_DW0_STENCIL0_FUNC__SHIFT			28
-#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__MASK			0x0e000000
-#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__SHIFT			25
-#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__MASK			0x01c00000
-#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__SHIFT			22
-#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__MASK			0x00380000
-#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__SHIFT			19
+#define GEN6_ZS_DW0_STENCIL_FUNC__MASK				0x70000000
+#define GEN6_ZS_DW0_STENCIL_FUNC__SHIFT				28
+#define GEN6_ZS_DW0_STENCIL_FAIL_OP__MASK			0x0e000000
+#define GEN6_ZS_DW0_STENCIL_FAIL_OP__SHIFT			25
+#define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__MASK			0x01c00000
+#define GEN6_ZS_DW0_STENCIL_ZFAIL_OP__SHIFT			22
+#define GEN6_ZS_DW0_STENCIL_ZPASS_OP__MASK			0x00380000
+#define GEN6_ZS_DW0_STENCIL_ZPASS_OP__SHIFT			19
 #define GEN6_ZS_DW0_STENCIL_WRITE_ENABLE			(0x1 << 18)
 #define GEN6_ZS_DW0_STENCIL1_ENABLE				(0x1 << 15)
 #define GEN6_ZS_DW0_STENCIL1_FUNC__MASK				0x00007000
@@ -181,14 +192,14 @@ enum gen_sampler_key_filter {
 #define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__MASK			0x00000038
 #define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT			3
 
-#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__MASK			0xff000000
-#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__SHIFT			24
-#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__MASK			0x00ff0000
-#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__SHIFT			16
-#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__MASK			0x0000ff00
-#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__SHIFT			8
-#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__MASK			0x000000ff
-#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__SHIFT			0
+#define GEN6_ZS_DW1_STENCIL_TEST_MASK__MASK			0xff000000
+#define GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT			24
+#define GEN6_ZS_DW1_STENCIL_WRITE_MASK__MASK			0x00ff0000
+#define GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT			16
+#define GEN6_ZS_DW1_STENCIL1_TEST_MASK__MASK			0x0000ff00
+#define GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT			8
+#define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__MASK			0x000000ff
+#define GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT			0
 
 #define GEN6_ZS_DW2_DEPTH_TEST_ENABLE				(0x1 << 31)
 #define GEN6_ZS_DW2_DEPTH_FUNC__MASK				0x38000000
@@ -216,10 +227,12 @@ enum gen_sampler_key_filter {
 #define GEN6_RT_DW1_ALPHA_TO_COVERAGE				(0x1 << 31)
 #define GEN6_RT_DW1_ALPHA_TO_ONE				(0x1 << 30)
 #define GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER			(0x1 << 29)
-#define GEN6_RT_DW1_WRITE_DISABLE_A				(0x1 << 27)
-#define GEN6_RT_DW1_WRITE_DISABLE_R				(0x1 << 26)
-#define GEN6_RT_DW1_WRITE_DISABLE_G				(0x1 << 25)
-#define GEN6_RT_DW1_WRITE_DISABLE_B				(0x1 << 24)
+#define GEN6_RT_DW1_WRITE_DISABLES__MASK			0x0f000000
+#define GEN6_RT_DW1_WRITE_DISABLES__SHIFT			24
+#define GEN6_RT_DW1_WRITE_DISABLES_A				(0x1 << 27)
+#define GEN6_RT_DW1_WRITE_DISABLES_R				(0x1 << 26)
+#define GEN6_RT_DW1_WRITE_DISABLES_G				(0x1 << 25)
+#define GEN6_RT_DW1_WRITE_DISABLES_B				(0x1 << 24)
 #define GEN6_RT_DW1_LOGICOP_ENABLE				(0x1 << 22)
 #define GEN6_RT_DW1_LOGICOP_FUNC__MASK				0x003c0000
 #define GEN6_RT_DW1_LOGICOP_FUNC__SHIFT				18
@@ -267,10 +280,12 @@ enum gen_sampler_key_filter {
 #define GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT			8
 #define GEN8_RT_DW0_ALPHA_FUNC__MASK				0x000000e0
 #define GEN8_RT_DW0_ALPHA_FUNC__SHIFT				5
-#define GEN8_RT_DW0_WRITE_DISABLE_A				(0x1 << 3)
-#define GEN8_RT_DW0_WRITE_DISABLE_R				(0x1 << 2)
-#define GEN8_RT_DW0_WRITE_DISABLE_G				(0x1 << 1)
-#define GEN8_RT_DW0_WRITE_DISABLE_B				(0x1 << 0)
+#define GEN8_RT_DW0_WRITE_DISABLES__MASK			0x0000000f
+#define GEN8_RT_DW0_WRITE_DISABLES__SHIFT			0
+#define GEN8_RT_DW0_WRITE_DISABLES_A				(0x1 << 3)
+#define GEN8_RT_DW0_WRITE_DISABLES_R				(0x1 << 2)
+#define GEN8_RT_DW0_WRITE_DISABLES_G				(0x1 << 1)
+#define GEN8_RT_DW0_WRITE_DISABLES_B				(0x1 << 0)
 
 #define GEN8_RT_DW1_LOGICOP_ENABLE				(0x1 << 31)
 #define GEN8_RT_DW1_LOGICOP_FUNC__MASK				0x78000000
@@ -419,6 +434,7 @@ enum gen_sampler_key_filter {
 #define GEN8_SAMPLER_DW0_LOD_PRECLAMP_ENABLE__SHIFT		27
 #define GEN6_SAMPLER_DW0_BASE_LOD__MASK				0x07c00000
 #define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT			22
+#define GEN6_SAMPLER_DW0_BASE_LOD__RADIX			1
 #define GEN6_SAMPLER_DW0_MIP_FILTER__MASK			0x00300000
 #define GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT			20
 #define GEN6_SAMPLER_DW0_MAG_FILTER__MASK			0x000e0000
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
index 7c2349f2447..b5d09f64429 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
@@ -299,7 +299,10 @@ enum gen_surface_scs {
 #define GEN6_SURFACE_DW0_MIPLAYOUT__SHIFT			10
 #define GEN6_SURFACE_DW0_MIPLAYOUT_BELOW			(0x0 << 10)
 #define GEN6_SURFACE_DW0_MIPLAYOUT_RIGHT			(0x1 << 10)
-#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE			(0x1 << 9)
+#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__MASK		0x00000200
+#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE__SHIFT		9
+#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_REPLICATE		(0x0 << 9)
+#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE		(0x1 << 9)
 #define GEN6_SURFACE_DW0_RENDER_CACHE_RW			(0x1 << 8)
 #define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK	0x000000c0
 #define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT	6
@@ -485,6 +488,8 @@ enum gen_surface_scs {
 #define GEN7_SURFACE_DW7_CC_B__SHIFT				29
 #define GEN7_SURFACE_DW7_CC_A__MASK				0x10000000
 #define GEN7_SURFACE_DW7_CC_A__SHIFT				28
+#define GEN75_SURFACE_DW7_SCS__MASK				0x0fff0000
+#define GEN75_SURFACE_DW7_SCS__SHIFT				16
 #define GEN75_SURFACE_DW7_SCS_R__MASK				0x0e000000
 #define GEN75_SURFACE_DW7_SCS_R__SHIFT				25
 #define GEN75_SURFACE_DW7_SCS_G__MASK				0x01c00000
diff --git a/src/gallium/drivers/ilo/genhw/genhw.h b/src/gallium/drivers/ilo/genhw/genhw.h
index 9e05bf5beca..3a777a18c2a 100644
--- a/src/gallium/drivers/ilo/genhw/genhw.h
+++ b/src/gallium/drivers/ilo/genhw/genhw.h
@@ -1,6 +1,4 @@
 /*
- * Mesa 3-D graphics library
- *
  * Copyright (C) 2014 LunarG, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,8 +23,9 @@
 #ifndef GENHW_H
 #define GENHW_H
 
-#include "pipe/p_compiler.h"
-#include "util/u_debug.h"
+#include <stdbool.h>
+#include <stdint.h>
+#include <assert.h>
 
 #include "gen_regs.xml.h"
 #include "gen_mi.xml.h"
diff --git a/src/gallium/drivers/ilo/ilo_shader.c b/src/gallium/drivers/ilo/ilo_shader.c
index 799db2cbfcb..af467064fe4 100644
--- a/src/gallium/drivers/ilo/ilo_shader.c
+++ b/src/gallium/drivers/ilo/ilo_shader.c
@@ -930,7 +930,8 @@ ilo_shader_select_kernel_routing(struct ilo_shader_state *shader,
           src_slot + 1 < routing->source_len &&
           src_semantics[src_slot + 1] == TGSI_SEMANTIC_BCOLOR &&
           src_indices[src_slot + 1] == index) {
-         routing->swizzles[dst_slot] |= GEN8_SBE_SWIZ_INPUTATTR_FACING;
+         routing->swizzles[dst_slot] |= GEN6_INPUTATTR_FACING <<
+            GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT;
          src_slot++;
       }