diff options
| author | Chia-I Wu <[email protected]> | 2014-09-10 10:34:04 +0800 |
|---|---|---|
| committer | Chia-I Wu <[email protected]> | 2014-09-11 16:29:38 +0800 |
| commit | 6816d853dbbfdc8b960b25496a9fe96a58053815 (patch) | |
| tree | 2e17f2ba21ae5076c0af9f0dd3f28430f96ad12f /src/gallium/drivers/ilo | |
| parent | b51b349942ffd22a12d578bee6ba5db60d88d1bd (diff) | |
ilo: add a new disassembler
The old disassembler was modified from i965's. It is as much work as doing a
new one to keep it up-to-date, which also requires copying more headers over.
The outputs of this new disassembler should match i965's as closely as
possible.
Diffstat (limited to 'src/gallium/drivers/ilo')
| -rw-r--r-- | src/gallium/drivers/ilo/include/brw_defines.h | 1726 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/include/brw_structs.h | 1453 | ||||
| -rw-r--r-- | src/gallium/drivers/ilo/shader/toy_compiler_disasm.c | 2617 |
3 files changed, 1352 insertions, 4444 deletions
diff --git a/src/gallium/drivers/ilo/include/brw_defines.h b/src/gallium/drivers/ilo/include/brw_defines.h deleted file mode 100644 index 04c8854d22f..00000000000 --- a/src/gallium/drivers/ilo/include/brw_defines.h +++ /dev/null @@ -1,1726 +0,0 @@ -/* - Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics to - develop this 3D driver. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial - portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - **********************************************************************/ - /* - * Authors: - * Keith Whitwell <[email protected]> - */ - -#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) -#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) -#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) - -#ifndef BRW_DEFINES_H -#define BRW_DEFINES_H - -/* 3D state: - */ -#define PIPE_CONTROL_NOWRITE 0x00 -#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 -#define PIPE_CONTROL_WRITEDEPTH 0x02 -#define PIPE_CONTROL_WRITETIMESTAMP 0x03 - -#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 -#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 - -#define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */ -/* DW0 */ -# define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10 -# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15) -# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 15) -/* DW1 */ -# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) -# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) - -#define _3DPRIM_POINTLIST 0x01 -#define _3DPRIM_LINELIST 0x02 -#define _3DPRIM_LINESTRIP 0x03 -#define _3DPRIM_TRILIST 0x04 -#define _3DPRIM_TRISTRIP 0x05 -#define _3DPRIM_TRIFAN 0x06 -#define _3DPRIM_QUADLIST 0x07 -#define _3DPRIM_QUADSTRIP 0x08 -#define _3DPRIM_LINELIST_ADJ 0x09 -#define _3DPRIM_LINESTRIP_ADJ 0x0A -#define _3DPRIM_TRILIST_ADJ 0x0B -#define _3DPRIM_TRISTRIP_ADJ 0x0C -#define _3DPRIM_TRISTRIP_REVERSE 0x0D -#define _3DPRIM_POLYGON 0x0E -#define _3DPRIM_RECTLIST 0x0F -#define _3DPRIM_LINELOOP 0x10 -#define _3DPRIM_POINTLIST_BF 0x11 -#define _3DPRIM_LINESTRIP_CONT 0x12 -#define _3DPRIM_LINESTRIP_BF 0x13 -#define _3DPRIM_LINESTRIP_CONT_BF 0x14 -#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 - -#define BRW_ANISORATIO_2 0 -#define BRW_ANISORATIO_4 1 -#define BRW_ANISORATIO_6 2 -#define BRW_ANISORATIO_8 3 -#define BRW_ANISORATIO_10 4 -#define BRW_ANISORATIO_12 5 -#define BRW_ANISORATIO_14 6 -#define BRW_ANISORATIO_16 7 - -#define BRW_BLENDFACTOR_ONE 0x1 -#define BRW_BLENDFACTOR_SRC_COLOR 0x2 -#define BRW_BLENDFACTOR_SRC_ALPHA 0x3 -#define BRW_BLENDFACTOR_DST_ALPHA 0x4 -#define BRW_BLENDFACTOR_DST_COLOR 0x5 -#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 -#define BRW_BLENDFACTOR_CONST_COLOR 0x7 -#define BRW_BLENDFACTOR_CONST_ALPHA 0x8 -#define BRW_BLENDFACTOR_SRC1_COLOR 0x9 -#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A -#define BRW_BLENDFACTOR_ZERO 0x11 -#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 -#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 -#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 -#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 -#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 -#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 -#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 -#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A - -#define BRW_BLENDFUNCTION_ADD 0 -#define BRW_BLENDFUNCTION_SUBTRACT 1 -#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 -#define BRW_BLENDFUNCTION_MIN 3 -#define BRW_BLENDFUNCTION_MAX 4 - -#define BRW_ALPHATEST_FORMAT_UNORM8 0 -#define BRW_ALPHATEST_FORMAT_FLOAT32 1 - -#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 -#define BRW_CHROMAKEY_REPLACE_BLACK 1 - -#define BRW_CLIP_API_OGL 0 -#define BRW_CLIP_API_DX 1 - -#define BRW_CLIPMODE_NORMAL 0 -#define BRW_CLIPMODE_CLIP_ALL 1 -#define BRW_CLIPMODE_CLIP_NON_REJECTED 2 -#define BRW_CLIPMODE_REJECT_ALL 3 -#define BRW_CLIPMODE_ACCEPT_ALL 4 -#define BRW_CLIPMODE_KERNEL_CLIP 5 - -#define BRW_CLIP_NDCSPACE 0 -#define BRW_CLIP_SCREENSPACE 1 - -#define BRW_COMPAREFUNCTION_ALWAYS 0 -#define BRW_COMPAREFUNCTION_NEVER 1 -#define BRW_COMPAREFUNCTION_LESS 2 -#define BRW_COMPAREFUNCTION_EQUAL 3 -#define BRW_COMPAREFUNCTION_LEQUAL 4 -#define BRW_COMPAREFUNCTION_GREATER 5 -#define BRW_COMPAREFUNCTION_NOTEQUAL 6 -#define BRW_COMPAREFUNCTION_GEQUAL 7 - -#define BRW_COVERAGE_PIXELS_HALF 0 -#define BRW_COVERAGE_PIXELS_1 1 -#define BRW_COVERAGE_PIXELS_2 2 -#define BRW_COVERAGE_PIXELS_4 3 - -#define BRW_CULLMODE_BOTH 0 -#define BRW_CULLMODE_NONE 1 -#define BRW_CULLMODE_FRONT 2 -#define BRW_CULLMODE_BACK 3 - -#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 -#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 - -#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 -#define BRW_DEPTHFORMAT_D32_FLOAT 1 -#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 -#define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT 3 /* GEN5 */ -#define BRW_DEPTHFORMAT_D16_UNORM 5 - -#define BRW_FLOATING_POINT_IEEE_754 0 -#define BRW_FLOATING_POINT_NON_IEEE_754 1 - -#define BRW_FRONTWINDING_CW 0 -#define BRW_FRONTWINDING_CCW 1 - -#define BRW_SPRITE_POINT_ENABLE 16 - -#define BRW_CUT_INDEX_ENABLE (1 << 10) - -#define BRW_INDEX_BYTE 0 -#define BRW_INDEX_WORD 1 -#define BRW_INDEX_DWORD 2 - -#define BRW_LOGICOPFUNCTION_CLEAR 0 -#define BRW_LOGICOPFUNCTION_NOR 1 -#define BRW_LOGICOPFUNCTION_AND_INVERTED 2 -#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 -#define BRW_LOGICOPFUNCTION_AND_REVERSE 4 -#define BRW_LOGICOPFUNCTION_INVERT 5 -#define BRW_LOGICOPFUNCTION_XOR 6 -#define BRW_LOGICOPFUNCTION_NAND 7 -#define BRW_LOGICOPFUNCTION_AND 8 -#define BRW_LOGICOPFUNCTION_EQUIV 9 -#define BRW_LOGICOPFUNCTION_NOOP 10 -#define BRW_LOGICOPFUNCTION_OR_INVERTED 11 -#define BRW_LOGICOPFUNCTION_COPY 12 -#define BRW_LOGICOPFUNCTION_OR_REVERSE 13 -#define BRW_LOGICOPFUNCTION_OR 14 -#define BRW_LOGICOPFUNCTION_SET 15 - -#define BRW_MAPFILTER_NEAREST 0x0 -#define BRW_MAPFILTER_LINEAR 0x1 -#define BRW_MAPFILTER_ANISOTROPIC 0x2 - -#define BRW_MIPFILTER_NONE 0 -#define BRW_MIPFILTER_NEAREST 1 -#define BRW_MIPFILTER_LINEAR 3 - -#define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG 0x20 -#define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN 0x10 -#define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG 0x08 -#define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN 0x04 -#define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG 0x02 -#define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN 0x01 - -#define BRW_POLYGON_FRONT_FACING 0 -#define BRW_POLYGON_BACK_FACING 1 - -#define BRW_PREFILTER_ALWAYS 0x0 -#define BRW_PREFILTER_NEVER 0x1 -#define BRW_PREFILTER_LESS 0x2 -#define BRW_PREFILTER_EQUAL 0x3 -#define BRW_PREFILTER_LEQUAL 0x4 -#define BRW_PREFILTER_GREATER 0x5 -#define BRW_PREFILTER_NOTEQUAL 0x6 -#define BRW_PREFILTER_GEQUAL 0x7 - -#define BRW_PROVOKING_VERTEX_0 0 -#define BRW_PROVOKING_VERTEX_1 1 -#define BRW_PROVOKING_VERTEX_2 2 - -#define BRW_RASTRULE_UPPER_LEFT 0 -#define BRW_RASTRULE_UPPER_RIGHT 1 -/* These are listed as "Reserved, but not seen as useful" - * in Intel documentation (page 212, "Point Rasterization Rule", - * section 7.4 "SF Pipeline State Summary", of document - * "Intel® 965 Express Chipset Family and Intel® G35 Express - * Chipset Graphics Controller Programmer's Reference Manual, - * Volume 2: 3D/Media", Revision 1.0b as of January 2008, - * available at - * http://intellinuxgraphics.org/documentation.html - * at the time of this writing). - * - * These appear to be supported on at least some - * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT - * is useful when using OpenGL to render to a FBO - * (which has the pixel coordinate Y orientation inverted - * with respect to the normal OpenGL pixel coordinate system). - */ -#define BRW_RASTRULE_LOWER_LEFT 2 -#define BRW_RASTRULE_LOWER_RIGHT 3 - -#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 -#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 -#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 - -#define BRW_STENCILOP_KEEP 0 -#define BRW_STENCILOP_ZERO 1 -#define BRW_STENCILOP_REPLACE 2 -#define BRW_STENCILOP_INCRSAT 3 -#define BRW_STENCILOP_DECRSAT 4 -#define BRW_STENCILOP_INCR 5 -#define BRW_STENCILOP_DECR 6 -#define BRW_STENCILOP_INVERT 7 - -/* Surface state DW0 */ -#define BRW_SURFACE_RC_READ_WRITE (1 << 8) -#define BRW_SURFACE_MIPLAYOUT_SHIFT 10 -#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 -#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 -#define BRW_SURFACE_CUBEFACE_ENABLES 0x3f -#define BRW_SURFACE_BLEND_ENABLED (1 << 13) -#define BRW_SURFACE_WRITEDISABLE_B_SHIFT 14 -#define BRW_SURFACE_WRITEDISABLE_G_SHIFT 15 -#define BRW_SURFACE_WRITEDISABLE_R_SHIFT 16 -#define BRW_SURFACE_WRITEDISABLE_A_SHIFT 17 - -#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 -#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 -#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 -#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 -#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 -#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 -#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 -#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 -#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 -#define BRW_SURFACEFORMAT_R32G32B32A32_SFIXED 0x020 -#define BRW_SURFACEFORMAT_R64G64_PASSTHRU 0x021 -#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 -#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 -#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 -#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 -#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 -#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 -#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 -#define BRW_SURFACEFORMAT_R32G32B32_SFIXED 0x050 -#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 -#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 -#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 -#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 -#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 -#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 -#define BRW_SURFACEFORMAT_R32G32_SINT 0x086 -#define BRW_SURFACEFORMAT_R32G32_UINT 0x087 -#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 -#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 -#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A -#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B -#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C -#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D -#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E -#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F -#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 -#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 -#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 -#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 -#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 -#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 -#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 -#define BRW_SURFACEFORMAT_R32G32_SFIXED 0x0A0 -#define BRW_SURFACEFORMAT_R64_PASSTHRU 0x0A1 -#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 -#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 -#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 -#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 -#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 -#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 -#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 -#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 -#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 -#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA -#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB -#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC -#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD -#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE -#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF -#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 -#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 -#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 -#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 -#define BRW_SURFACEFORMAT_R32_SINT 0x0D6 -#define BRW_SURFACEFORMAT_R32_UINT 0x0D7 -#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 -#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 -#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA -#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF -#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 -#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 -#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 -#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 -#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 -#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 -#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 -#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA -#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB -#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC -#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED -#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE -#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 -#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 -#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 -#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 -#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 -#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 -#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 -#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 -#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 -#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 -#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 -#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 -#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 -#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 -#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 -#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 -#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 -#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 -#define BRW_SURFACEFORMAT_R8G8_SINT 0x108 -#define BRW_SURFACEFORMAT_R8G8_UINT 0x109 -#define BRW_SURFACEFORMAT_R16_UNORM 0x10A -#define BRW_SURFACEFORMAT_R16_SNORM 0x10B -#define BRW_SURFACEFORMAT_R16_SINT 0x10C -#define BRW_SURFACEFORMAT_R16_UINT 0x10D -#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E -#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0 0x10F -#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1 0x110 -#define BRW_SURFACEFORMAT_I16_UNORM 0x111 -#define BRW_SURFACEFORMAT_L16_UNORM 0x112 -#define BRW_SURFACEFORMAT_A16_UNORM 0x113 -#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 -#define BRW_SURFACEFORMAT_I16_FLOAT 0x115 -#define BRW_SURFACEFORMAT_L16_FLOAT 0x116 -#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 -#define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118 -#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 -#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A -#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B -#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C -#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D -#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E -#define BRW_SURFACEFORMAT_R16_USCALED 0x11F -#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0 0x122 -#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1 0x123 -#define BRW_SURFACEFORMAT_A1B5G5R5_UNORM 0x124 -#define BRW_SURFACEFORMAT_A4B4G4R4_UNORM 0x125 -#define BRW_SURFACEFORMAT_L8A8_UINT 0x126 -#define BRW_SURFACEFORMAT_L8A8_SINT 0x127 -#define BRW_SURFACEFORMAT_R8_UNORM 0x140 -#define BRW_SURFACEFORMAT_R8_SNORM 0x141 -#define BRW_SURFACEFORMAT_R8_SINT 0x142 -#define BRW_SURFACEFORMAT_R8_UINT 0x143 -#define BRW_SURFACEFORMAT_A8_UNORM 0x144 -#define BRW_SURFACEFORMAT_I8_UNORM 0x145 -#define BRW_SURFACEFORMAT_L8_UNORM 0x146 -#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 -#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 -#define BRW_SURFACEFORMAT_R8_SSCALED 0x149 -#define BRW_SURFACEFORMAT_R8_USCALED 0x14A -#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE0 0x14B -#define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C -#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE1 0x14D -#define BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1 0x14E -#define BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1 0x14F -#define BRW_SURFACEFORMAT_Y8_SNORM 0x150 -#define BRW_SURFACEFORMAT_L8_UINT 0x152 -#define BRW_SURFACEFORMAT_L8_SINT 0x153 -#define BRW_SURFACEFORMAT_I8_UINT 0x154 -#define BRW_SURFACEFORMAT_I8_SINT 0x155 -#define BRW_SURFACEFORMAT_DXT1_RGB_SRGB 0x180 -#define BRW_SURFACEFORMAT_R1_UINT 0x181 -#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 -#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 -#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE0 0x184 -#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE1 0x185 -#define BRW_SURFACEFORMAT_BC1_UNORM 0x186 -#define BRW_SURFACEFORMAT_BC2_UNORM 0x187 -#define BRW_SURFACEFORMAT_BC3_UNORM 0x188 -#define BRW_SURFACEFORMAT_BC4_UNORM 0x189 -#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A -#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B -#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C -#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D -#define BRW_SURFACEFORMAT_MONO8 0x18E -#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F -#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 -#define BRW_SURFACEFORMAT_DXT1_RGB 0x191 -#define BRW_SURFACEFORMAT_FXT1 0x192 -#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 -#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 -#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 -#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 -#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 -#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 -#define BRW_SURFACEFORMAT_BC4_SNORM 0x199 -#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A -#define BRW_SURFACEFORMAT_R16G16B16_FLOAT 0x19B -#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C -#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D -#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E -#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F -#define BRW_SURFACEFORMAT_BC6H_SF16 0x1A1 -#define BRW_SURFACEFORMAT_BC7_UNORM 0x1A2 -#define BRW_SURFACEFORMAT_BC7_UNORM_SRGB 0x1A3 -#define BRW_SURFACEFORMAT_BC6H_UF16 0x1A4 -#define BRW_SURFACEFORMAT_PLANAR_420_8 0x1A5 -#define BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB 0x1A8 -#define BRW_SURFACEFORMAT_ETC1_RGB8 0x1A9 -#define BRW_SURFACEFORMAT_ETC2_RGB8 0x1AA -#define BRW_SURFACEFORMAT_EAC_R11 0x1AB -#define BRW_SURFACEFORMAT_EAC_RG11 0x1AC -#define BRW_SURFACEFORMAT_EAC_SIGNED_R11 0x1AD -#define BRW_SURFACEFORMAT_EAC_SIGNED_RG11 0x1AE -#define BRW_SURFACEFORMAT_ETC2_SRGB8 0x1AF -#define BRW_SURFACEFORMAT_R16G16B16_UINT 0x1B0 -#define BRW_SURFACEFORMAT_R16G16B16_SINT 0x1B1 -#define BRW_SURFACEFORMAT_R32_SFIXED 0x1B2 -#define BRW_SURFACEFORMAT_R10G10B10A2_SNORM 0x1B3 -#define BRW_SURFACEFORMAT_R10G10B10A2_USCALED 0x1B4 -#define BRW_SURFACEFORMAT_R10G10B10A2_SSCALED 0x1B5 -#define BRW_SURFACEFORMAT_R10G10B10A2_SINT 0x1B6 -#define BRW_SURFACEFORMAT_B10G10R10A2_SNORM 0x1B7 -#define BRW_SURFACEFORMAT_B10G10R10A2_USCALED 0x1B8 -#define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED 0x1B9 -#define BRW_SURFACEFORMAT_B10G10R10A2_UINT 0x1BA -#define BRW_SURFACEFORMAT_B10G10R10A2_SINT 0x1BB -#define BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU 0x1BC -#define BRW_SURFACEFORMAT_R64G64B64_PASSTHRU 0x1BD -#define BRW_SURFACEFORMAT_ETC2_RGB8_PTA 0x1C0 -#define BRW_SURFACEFORMAT_ETC2_SRGB8_PTA 0x1C1 -#define BRW_SURFACEFORMAT_ETC2_EAC_RGBA8 0x1C2 -#define BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8 0x1C3 -#define BRW_SURFACEFORMAT_R8G8B8_UINT 0x1C8 -#define BRW_SURFACEFORMAT_R8G8B8_SINT 0x1C9 -#define BRW_SURFACEFORMAT_RAW 0x1FF -#define BRW_SURFACE_FORMAT_SHIFT 18 -#define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18) - -#define BRW_SURFACERETURNFORMAT_FLOAT32 0 -#define BRW_SURFACERETURNFORMAT_S1 1 - -#define BRW_SURFACE_TYPE_SHIFT 29 -#define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29) -#define BRW_SURFACE_1D 0 -#define BRW_SURFACE_2D 1 -#define BRW_SURFACE_3D 2 -#define BRW_SURFACE_CUBE 3 -#define BRW_SURFACE_BUFFER 4 -#define BRW_SURFACE_NULL 7 - -#define GEN7_SURFACE_IS_ARRAY (1 << 28) -#define GEN7_SURFACE_VALIGN_2 (0 << 16) -#define GEN7_SURFACE_VALIGN_4 (1 << 16) -#define GEN7_SURFACE_HALIGN_4 (0 << 15) -#define GEN7_SURFACE_HALIGN_8 (1 << 15) -#define GEN7_SURFACE_TILING_NONE (0 << 13) -#define GEN7_SURFACE_TILING_X (2 << 13) -#define GEN7_SURFACE_TILING_Y (3 << 13) -#define GEN7_SURFACE_ARYSPC_FULL (0 << 10) -#define GEN7_SURFACE_ARYSPC_LOD0 (1 << 10) - -/* Surface state DW2 */ -#define BRW_SURFACE_HEIGHT_SHIFT 19 -#define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19) -#define BRW_SURFACE_WIDTH_SHIFT 6 -#define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6) -#define BRW_SURFACE_LOD_SHIFT 2 -#define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2) -#define GEN7_SURFACE_HEIGHT_SHIFT 16 -#define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16) -#define GEN7_SURFACE_WIDTH_SHIFT 0 -#define GEN7_SURFACE_WIDTH_MASK INTEL_MASK(13, 0) - -/* Surface state DW3 */ -#define BRW_SURFACE_DEPTH_SHIFT 21 -#define BRW_SURFACE_DEPTH_MASK INTEL_MASK(31, 21) -#define BRW_SURFACE_PITCH_SHIFT 3 -#define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3) -#define BRW_SURFACE_TILED (1 << 1) -#define BRW_SURFACE_TILED_Y (1 << 0) - -/* Surface state DW4 */ -#define BRW_SURFACE_MIN_LOD_SHIFT 28 -#define BRW_SURFACE_MIN_LOD_MASK INTEL_MASK(31, 28) -#define BRW_SURFACE_MULTISAMPLECOUNT_1 (0 << 4) -#define BRW_SURFACE_MULTISAMPLECOUNT_4 (2 << 4) -#define GEN7_SURFACE_MULTISAMPLECOUNT_1 (0 << 3) -#define GEN7_SURFACE_MULTISAMPLECOUNT_4 (2 << 3) -#define GEN7_SURFACE_MULTISAMPLECOUNT_8 (3 << 3) -#define GEN7_SURFACE_MSFMT_MSS (0 << 6) -#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL (1 << 6) - -/* Surface state DW5 */ -#define BRW_SURFACE_X_OFFSET_SHIFT 25 -#define BRW_SURFACE_X_OFFSET_MASK INTEL_MASK(31, 25) -#define BRW_SURFACE_VERTICAL_ALIGN_ENABLE (1 << 24) -#define BRW_SURFACE_Y_OFFSET_SHIFT 20 -#define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20) -#define GEN7_SURFACE_MIN_LOD_SHIFT 4 -#define GEN7_SURFACE_MIN_LOD_MASK INTEL_MASK(7, 4) - -/* Surface state DW6 */ -#define GEN7_SURFACE_MCS_ENABLE (1 << 0) -#define GEN7_SURFACE_MCS_PITCH_SHIFT 3 -#define GEN7_SURFACE_MCS_PITCH_MASK INTEL_MASK(11, 3) - -/* Surface state DW7 */ -#define GEN7_SURFACE_SCS_R_SHIFT 25 -#define GEN7_SURFACE_SCS_R_MASK INTEL_MASK(27, 25) -#define GEN7_SURFACE_SCS_G_SHIFT 22 -#define GEN7_SURFACE_SCS_G_MASK INTEL_MASK(24, 22) -#define GEN7_SURFACE_SCS_B_SHIFT 19 -#define GEN7_SURFACE_SCS_B_MASK INTEL_MASK(21, 19) -#define GEN7_SURFACE_SCS_A_SHIFT 16 -#define GEN7_SURFACE_SCS_A_MASK INTEL_MASK(18, 16) - -/* The actual swizzle values/what channel to use */ -#define HSW_SCS_ZERO 0 -#define HSW_SCS_ONE 1 -#define HSW_SCS_RED 4 -#define HSW_SCS_GREEN 5 -#define HSW_SCS_BLUE 6 -#define HSW_SCS_ALPHA 7 - -#define BRW_TEXCOORDMODE_WRAP 0 -#define BRW_TEXCOORDMODE_MIRROR 1 -#define BRW_TEXCOORDMODE_CLAMP 2 -#define BRW_TEXCOORDMODE_CUBE 3 -#define BRW_TEXCOORDMODE_CLAMP_BORDER 4 -#define BRW_TEXCOORDMODE_MIRROR_ONCE 5 - -#define BRW_THREAD_PRIORITY_NORMAL 0 -#define BRW_THREAD_PRIORITY_HIGH 1 - -#define BRW_TILEWALK_XMAJOR 0 -#define BRW_TILEWALK_YMAJOR 1 - -#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 -#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 - -/* Execution Unit (EU) defines - */ - -#define BRW_ALIGN_1 0 -#define BRW_ALIGN_16 1 - -#define BRW_ADDRESS_DIRECT 0 -#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 - -#define BRW_CHANNEL_X 0 -#define BRW_CHANNEL_Y 1 -#define BRW_CHANNEL_Z 2 -#define BRW_CHANNEL_W 3 - -enum brw_compression { - BRW_COMPRESSION_NONE = 0, - BRW_COMPRESSION_2NDHALF = 1, - BRW_COMPRESSION_COMPRESSED = 2, -}; - -#define GEN6_COMPRESSION_1Q 0 -#define GEN6_COMPRESSION_2Q 1 -#define GEN6_COMPRESSION_3Q 2 -#define GEN6_COMPRESSION_4Q 3 -#define GEN6_COMPRESSION_1H 0 -#define GEN6_COMPRESSION_2H 2 - -#define BRW_CONDITIONAL_NONE 0 -#define BRW_CONDITIONAL_Z 1 -#define BRW_CONDITIONAL_NZ 2 -#define BRW_CONDITIONAL_EQ 1 /* Z */ -#define BRW_CONDITIONAL_NEQ 2 /* NZ */ -#define BRW_CONDITIONAL_G 3 -#define BRW_CONDITIONAL_GE 4 -#define BRW_CONDITIONAL_L 5 -#define BRW_CONDITIONAL_LE 6 -#define BRW_CONDITIONAL_R 7 -#define BRW_CONDITIONAL_O 8 -#define BRW_CONDITIONAL_U 9 - -#define BRW_DEBUG_NONE 0 -#define BRW_DEBUG_BREAKPOINT 1 - -#define BRW_DEPENDENCY_NORMAL 0 -#define BRW_DEPENDENCY_NOTCLEARED 1 -#define BRW_DEPENDENCY_NOTCHECKED 2 -#define BRW_DEPENDENCY_DISABLE 3 - -#define BRW_EXECUTE_1 0 -#define BRW_EXECUTE_2 1 -#define BRW_EXECUTE_4 2 -#define BRW_EXECUTE_8 3 -#define BRW_EXECUTE_16 4 -#define BRW_EXECUTE_32 5 - -#define BRW_HORIZONTAL_STRIDE_0 0 -#define BRW_HORIZONTAL_STRIDE_1 1 -#define BRW_HORIZONTAL_STRIDE_2 2 -#define BRW_HORIZONTAL_STRIDE_4 3 - -#define BRW_INSTRUCTION_NORMAL 0 -#define BRW_INSTRUCTION_SATURATE 1 - -#define BRW_MASK_ENABLE 0 -#define BRW_MASK_DISABLE 1 - -/** @{ - * - * Gen6 has replaced "mask enable/disable" with WECtrl, which is - * effectively the same but much simpler to think about. Now, there - * are two contributors ANDed together to whether channels are - * executed: The predication on the instruction, and the channel write - * enable. - */ -/** - * This is the default value. It means that a channel's write enable is set - * if the per-channel IP is pointing at this instruction. - */ -#define BRW_WE_NORMAL 0 -/** - * This is used like BRW_MASK_DISABLE, and causes all channels to have - * their write enable set. Note that predication still contributes to - * whether the channel actually gets written. - */ -#define BRW_WE_ALL 1 -/** @} */ - -enum opcode { - /* These are the actual hardware opcodes. */ - BRW_OPCODE_MOV = 1, - BRW_OPCODE_SEL = 2, - BRW_OPCODE_NOT = 4, - BRW_OPCODE_AND = 5, - BRW_OPCODE_OR = 6, - BRW_OPCODE_XOR = 7, - BRW_OPCODE_SHR = 8, - BRW_OPCODE_SHL = 9, - BRW_OPCODE_RSR = 10, - BRW_OPCODE_RSL = 11, - BRW_OPCODE_ASR = 12, - BRW_OPCODE_CMP = 16, - BRW_OPCODE_CMPN = 17, - BRW_OPCODE_F32TO16 = 19, - BRW_OPCODE_F16TO32 = 20, - BRW_OPCODE_BFREV = 23, - BRW_OPCODE_BFE = 24, - BRW_OPCODE_BFI1 = 25, - BRW_OPCODE_BFI2 = 26, - BRW_OPCODE_JMPI = 32, - BRW_OPCODE_IF = 34, - BRW_OPCODE_IFF = 35, - BRW_OPCODE_ELSE = 36, - BRW_OPCODE_ENDIF = 37, - BRW_OPCODE_DO = 38, - BRW_OPCODE_WHILE = 39, - BRW_OPCODE_BREAK = 40, - BRW_OPCODE_CONTINUE = 41, - BRW_OPCODE_HALT = 42, - BRW_OPCODE_MSAVE = 44, - BRW_OPCODE_MRESTORE = 45, - BRW_OPCODE_PUSH = 46, - BRW_OPCODE_POP = 47, - BRW_OPCODE_WAIT = 48, - BRW_OPCODE_SEND = 49, - BRW_OPCODE_SENDC = 50, - BRW_OPCODE_MATH = 56, - BRW_OPCODE_ADD = 64, - BRW_OPCODE_MUL = 65, - BRW_OPCODE_AVG = 66, - BRW_OPCODE_FRC = 67, - BRW_OPCODE_RNDU = 68, - BRW_OPCODE_RNDD = 69, - BRW_OPCODE_RNDE = 70, - BRW_OPCODE_RNDZ = 71, - BRW_OPCODE_MAC = 72, - BRW_OPCODE_MACH = 73, - BRW_OPCODE_LZD = 74, - BRW_OPCODE_FBH = 75, - BRW_OPCODE_FBL = 76, - BRW_OPCODE_CBIT = 77, - BRW_OPCODE_SAD2 = 80, - BRW_OPCODE_SADA2 = 81, - BRW_OPCODE_DP4 = 84, - BRW_OPCODE_DPH = 85, - BRW_OPCODE_DP3 = 86, - BRW_OPCODE_DP2 = 87, - BRW_OPCODE_DPA2 = 88, - BRW_OPCODE_LINE = 89, - BRW_OPCODE_PLN = 90, - BRW_OPCODE_MAD = 91, - BRW_OPCODE_LRP = 92, - BRW_OPCODE_NOP = 126, - - /* These are compiler backend opcodes that get translated into other - * instructions. - */ - FS_OPCODE_FB_WRITE = 128, - SHADER_OPCODE_RCP, - SHADER_OPCODE_RSQ, - SHADER_OPCODE_SQRT, - SHADER_OPCODE_EXP2, - SHADER_OPCODE_LOG2, - SHADER_OPCODE_POW, - SHADER_OPCODE_INT_QUOTIENT, - SHADER_OPCODE_INT_REMAINDER, - SHADER_OPCODE_SIN, - SHADER_OPCODE_COS, - - SHADER_OPCODE_TEX, - SHADER_OPCODE_TXD, - SHADER_OPCODE_TXF, - SHADER_OPCODE_TXL, - SHADER_OPCODE_TXS, - FS_OPCODE_TXB, - SHADER_OPCODE_TXF_MS, - SHADER_OPCODE_LOD, - - SHADER_OPCODE_SHADER_TIME_ADD, - - FS_OPCODE_DDX, - FS_OPCODE_DDY, - FS_OPCODE_PIXEL_X, - FS_OPCODE_PIXEL_Y, - FS_OPCODE_CINTERP, - FS_OPCODE_LINTERP, - FS_OPCODE_SPILL, - FS_OPCODE_UNSPILL, - FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, - FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7, - FS_OPCODE_VARYING_PULL_CONSTANT_LOAD, - FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7, - FS_OPCODE_MOV_DISPATCH_TO_FLAGS, - FS_OPCODE_DISCARD_JUMP, - FS_OPCODE_SET_SIMD4X2_OFFSET, - FS_OPCODE_PACK_HALF_2x16_SPLIT, - FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, - FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, - FS_OPCODE_PLACEHOLDER_HALT, - - VS_OPCODE_URB_WRITE, - VS_OPCODE_SCRATCH_READ, - VS_OPCODE_SCRATCH_WRITE, - VS_OPCODE_PULL_CONSTANT_LOAD, - VS_OPCODE_PULL_CONSTANT_LOAD_GEN7, -}; - -#define BRW_PREDICATE_NONE 0 -#define BRW_PREDICATE_NORMAL 1 -#define BRW_PREDICATE_ALIGN1_ANYV 2 -#define BRW_PREDICATE_ALIGN1_ALLV 3 -#define BRW_PREDICATE_ALIGN1_ANY2H 4 -#define BRW_PREDICATE_ALIGN1_ALL2H 5 -#define BRW_PREDICATE_ALIGN1_ANY4H 6 -#define BRW_PREDICATE_ALIGN1_ALL4H 7 -#define BRW_PREDICATE_ALIGN1_ANY8H 8 -#define BRW_PREDICATE_ALIGN1_ALL8H 9 -#define BRW_PREDICATE_ALIGN1_ANY16H 10 -#define BRW_PREDICATE_ALIGN1_ALL16H 11 -#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 -#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 -#define BRW_PREDICATE_ALIGN16_ANY4H 6 -#define BRW_PREDICATE_ALIGN16_ALL4H 7 - -#define BRW_ARCHITECTURE_REGISTER_FILE 0 -#define BRW_GENERAL_REGISTER_FILE 1 -#define BRW_MESSAGE_REGISTER_FILE 2 -#define BRW_IMMEDIATE_VALUE 3 - -#define BRW_REGISTER_TYPE_UD 0 -#define BRW_REGISTER_TYPE_D 1 -#define BRW_REGISTER_TYPE_UW 2 -#define BRW_REGISTER_TYPE_W 3 -#define BRW_REGISTER_TYPE_UB 4 -#define BRW_REGISTER_TYPE_B 5 -#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ -#define BRW_REGISTER_TYPE_HF 6 -#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ -#define BRW_REGISTER_TYPE_F 7 - -/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so - * the types were implied. IVB adds BFE and BFI2 that operate on doublewords - * and unsigned doublewords, so a new field is also available in the da3src - * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select - * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*. - */ -#define BRW_3SRC_TYPE_F 0 -#define BRW_3SRC_TYPE_D 1 -#define BRW_3SRC_TYPE_UD 2 -#define BRW_3SRC_TYPE_DF 3 - -#define BRW_ARF_NULL 0x00 -#define BRW_ARF_ADDRESS 0x10 -#define BRW_ARF_ACCUMULATOR 0x20 -#define BRW_ARF_FLAG 0x30 -#define BRW_ARF_MASK 0x40 -#define BRW_ARF_MASK_STACK 0x50 -#define BRW_ARF_MASK_STACK_DEPTH 0x60 -#define BRW_ARF_STATE 0x70 -#define BRW_ARF_CONTROL 0x80 -#define BRW_ARF_NOTIFICATION_COUNT 0x90 -#define BRW_ARF_IP 0xA0 -#define BRW_ARF_TDR 0xB0 -#define BRW_ARF_TIMESTAMP 0xC0 - -#define BRW_MRF_COMPR4 (1 << 7) - -#define BRW_AMASK 0 -#define BRW_IMASK 1 -#define BRW_LMASK 2 -#define BRW_CMASK 3 - - - -#define BRW_THREAD_NORMAL 0 -#define BRW_THREAD_ATOMIC 1 -#define BRW_THREAD_SWITCH 2 - -#define BRW_VERTICAL_STRIDE_0 0 -#define BRW_VERTICAL_STRIDE_1 1 -#define BRW_VERTICAL_STRIDE_2 2 -#define BRW_VERTICAL_STRIDE_4 3 -#define BRW_VERTICAL_STRIDE_8 4 -#define BRW_VERTICAL_STRIDE_16 5 -#define BRW_VERTICAL_STRIDE_32 6 -#define BRW_VERTICAL_STRIDE_64 7 -#define BRW_VERTICAL_STRIDE_128 8 -#define BRW_VERTICAL_STRIDE_256 9 -#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF - -#define BRW_WIDTH_1 0 -#define BRW_WIDTH_2 1 -#define BRW_WIDTH_4 2 -#define BRW_WIDTH_8 3 -#define BRW_WIDTH_16 4 - -#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 -#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 -#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 -#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 -#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 -#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 -#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 -#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 -#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 -#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 -#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 -#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 - -#define BRW_POLYGON_FACING_FRONT 0 -#define BRW_POLYGON_FACING_BACK 1 - -/** - * Message target: Shared Function ID for where to SEND a message. - * - * These are enumerated in the ISA reference under "send - Send Message". - * In particular, see the following tables: - * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition" - * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" - * - BSpec, Volume 1a (GPU Overview) / Graphics Processing Engine (GPE) / - * Overview / GPE Function IDs - */ -enum brw_message_target { - BRW_SFID_NULL = 0, - BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */ - BRW_SFID_SAMPLER = 2, - BRW_SFID_MESSAGE_GATEWAY = 3, - BRW_SFID_DATAPORT_READ = 4, - BRW_SFID_DATAPORT_WRITE = 5, - BRW_SFID_URB = 6, - BRW_SFID_THREAD_SPAWNER = 7, - - GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4, - GEN6_SFID_DATAPORT_RENDER_CACHE = 5, - GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9, - - GEN7_SFID_DATAPORT_DATA_CACHE = 10, - HSW_SFID_DATAPORT_DATA_CACHE_1 = 12, -}; - -#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10 - -#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 -#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 -#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 - -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 -#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 - -#define GEN5_SAMPLER_MESSAGE_SAMPLE 0 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7 -#define GEN5_SAMPLER_MESSAGE_LOD 9 -#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10 -#define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20 -#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29 -#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30 -#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 - -/* for GEN5 only */ -#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 -#define BRW_SAMPLER_SIMD_MODE_SIMD8 1 -#define BRW_SAMPLER_SIMD_MODE_SIMD16 2 -#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 - -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 -#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 -#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 -#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 - -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 - -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 - -/* This one stays the same across generations. */ -#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 -/* GEN4 */ -#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 -#define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 -#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 -/* G45, GEN5 */ -#define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 -#define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 -#define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 -#define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 -#define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 -/* GEN6 */ -#define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 -#define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 -#define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 -#define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 -#define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 - -#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 -#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 -#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 - -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 - -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 -#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 -#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 -#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 -#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 - -/* GEN6 */ -#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 -#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 -#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 -#define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 -#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 -#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 -#define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 -#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 - -/* GEN7 */ -#define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 10 -#define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0 -#define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1 -#define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2 -#define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3 -#define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4 -#define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5 -#define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6 -#define GEN7_DATAPORT_DC_MEMORY_FENCE 7 -#define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8 -#define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10 -#define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11 -#define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12 -#define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13 - -/* HSW */ -#define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0 -#define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1 -#define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2 -#define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3 -#define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4 -#define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7 -#define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8 -#define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10 -#define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11 -#define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12 - -#define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1 -#define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2 -#define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3 -#define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4 -#define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5 -#define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6 -#define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7 -#define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9 -#define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10 -#define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11 -#define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12 -#define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13 - -/* dataport atomic operations. */ -#define BRW_AOP_AND 1 -#define BRW_AOP_OR 2 -#define BRW_AOP_XOR 3 -#define BRW_AOP_MOV 4 -#define BRW_AOP_INC 5 -#define BRW_AOP_DEC 6 -#define BRW_AOP_ADD 7 -#define BRW_AOP_SUB 8 -#define BRW_AOP_REVSUB 9 -#define BRW_AOP_IMAX 10 -#define BRW_AOP_IMIN 11 -#define BRW_AOP_UMAX 12 -#define BRW_AOP_UMIN 13 -#define BRW_AOP_CMPWR 14 -#define BRW_AOP_PREDEC 15 - -#define BRW_MATH_FUNCTION_INV 1 -#define BRW_MATH_FUNCTION_LOG 2 -#define BRW_MATH_FUNCTION_EXP 3 -#define BRW_MATH_FUNCTION_SQRT 4 -#define BRW_MATH_FUNCTION_RSQ 5 -#define BRW_MATH_FUNCTION_SIN 6 -#define BRW_MATH_FUNCTION_COS 7 -#define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */ -#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */ -#define BRW_MATH_FUNCTION_POW 10 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 -#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 - -#define BRW_MATH_INTEGER_UNSIGNED 0 -#define BRW_MATH_INTEGER_SIGNED 1 - -#define BRW_MATH_PRECISION_FULL 0 -#define BRW_MATH_PRECISION_PARTIAL 1 - -#define BRW_MATH_SATURATE_NONE 0 -#define BRW_MATH_SATURATE_SATURATE 1 - -#define BRW_MATH_DATA_VECTOR 0 -#define BRW_MATH_DATA_SCALAR 1 - -#define BRW_URB_OPCODE_WRITE 0 - -#define BRW_URB_SWIZZLE_NONE 0 -#define BRW_URB_SWIZZLE_INTERLEAVE 1 -#define BRW_URB_SWIZZLE_TRANSPOSE 2 - -#define BRW_SCRATCH_SPACE_SIZE_1K 0 -#define BRW_SCRATCH_SPACE_SIZE_2K 1 -#define BRW_SCRATCH_SPACE_SIZE_4K 2 -#define BRW_SCRATCH_SPACE_SIZE_8K 3 -#define BRW_SCRATCH_SPACE_SIZE_16K 4 -#define BRW_SCRATCH_SPACE_SIZE_32K 5 -#define BRW_SCRATCH_SPACE_SIZE_64K 6 -#define BRW_SCRATCH_SPACE_SIZE_128K 7 -#define BRW_SCRATCH_SPACE_SIZE_256K 8 -#define BRW_SCRATCH_SPACE_SIZE_512K 9 -#define BRW_SCRATCH_SPACE_SIZE_1M 10 -#define BRW_SCRATCH_SPACE_SIZE_2M 11 - - -#define CMD_URB_FENCE 0x6000 -#define CMD_CS_URB_STATE 0x6001 -#define CMD_CONST_BUFFER 0x6002 - -#define CMD_STATE_BASE_ADDRESS 0x6101 -#define CMD_STATE_SIP 0x6102 -#define CMD_PIPELINE_SELECT_965 0x6104 -#define CMD_PIPELINE_SELECT_GM45 0x6904 - -#define _3DSTATE_PIPELINED_POINTERS 0x7800 -#define _3DSTATE_BINDING_TABLE_POINTERS 0x7801 -# define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8) -# define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9) -# define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12) - -#define _3DSTATE_BINDING_TABLE_POINTERS_VS 0x7826 /* GEN7+ */ -#define _3DSTATE_BINDING_TABLE_POINTERS_HS 0x7827 /* GEN7+ */ -#define _3DSTATE_BINDING_TABLE_POINTERS_DS 0x7828 /* GEN7+ */ -#define _3DSTATE_BINDING_TABLE_POINTERS_GS 0x7829 /* GEN7+ */ -#define _3DSTATE_BINDING_TABLE_POINTERS_PS 0x782A /* GEN7+ */ - -#define _3DSTATE_SAMPLER_STATE_POINTERS 0x7802 /* GEN6+ */ -# define PS_SAMPLER_STATE_CHANGE (1 << 12) -# define GS_SAMPLER_STATE_CHANGE (1 << 9) -# define VS_SAMPLER_STATE_CHANGE (1 << 8) -/* DW1: VS */ -/* DW2: GS */ -/* DW3: PS */ - -#define _3DSTATE_SAMPLER_STATE_POINTERS_VS 0x782B /* GEN7+ */ -#define _3DSTATE_SAMPLER_STATE_POINTERS_GS 0x782E /* GEN7+ */ -#define _3DSTATE_SAMPLER_STATE_POINTERS_PS 0x782F /* GEN7+ */ - -#define _3DSTATE_VERTEX_BUFFERS 0x7808 -# define BRW_VB0_INDEX_SHIFT 27 -# define GEN6_VB0_INDEX_SHIFT 26 -# define BRW_VB0_ACCESS_VERTEXDATA (0 << 26) -# define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26) -# define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20) -# define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20) -# define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14) -# define BRW_VB0_PITCH_SHIFT 0 - -#define _3DSTATE_VERTEX_ELEMENTS 0x7809 -# define BRW_VE0_INDEX_SHIFT 27 -# define GEN6_VE0_INDEX_SHIFT 26 -# define BRW_VE0_FORMAT_SHIFT 16 -# define BRW_VE0_VALID (1 << 26) -# define GEN6_VE0_VALID (1 << 25) -# define GEN6_VE0_EDGE_FLAG_ENABLE (1 << 15) -# define BRW_VE0_SRC_OFFSET_SHIFT 0 -# define BRW_VE1_COMPONENT_NOSTORE 0 -# define BRW_VE1_COMPONENT_STORE_SRC 1 -# define BRW_VE1_COMPONENT_STORE_0 2 -# define BRW_VE1_COMPONENT_STORE_1_FLT 3 -# define BRW_VE1_COMPONENT_STORE_1_INT 4 -# define BRW_VE1_COMPONENT_STORE_VID 5 -# define BRW_VE1_COMPONENT_STORE_IID 6 -# define BRW_VE1_COMPONENT_STORE_PID 7 -# define BRW_VE1_COMPONENT_0_SHIFT 28 -# define BRW_VE1_COMPONENT_1_SHIFT 24 -# define BRW_VE1_COMPONENT_2_SHIFT 20 -# define BRW_VE1_COMPONENT_3_SHIFT 16 -# define BRW_VE1_DST_OFFSET_SHIFT 0 - -#define CMD_INDEX_BUFFER 0x780a -#define GEN4_3DSTATE_VF_STATISTICS 0x780b -#define GM45_3DSTATE_VF_STATISTICS 0x680b -#define _3DSTATE_CC_STATE_POINTERS 0x780e /* GEN6+ */ -#define _3DSTATE_BLEND_STATE_POINTERS 0x7824 /* GEN7+ */ -#define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS 0x7825 /* GEN7+ */ - -#define _3DSTATE_URB 0x7805 /* GEN6 */ -# define GEN6_URB_VS_SIZE_SHIFT 16 -# define GEN6_URB_VS_ENTRIES_SHIFT 0 -# define GEN6_URB_GS_ENTRIES_SHIFT 8 -# define GEN6_URB_GS_SIZE_SHIFT 0 - -#define _3DSTATE_VF 0x780c /* GEN7.5+ */ -#define HSW_CUT_INDEX_ENABLE (1 << 8) - -#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */ -#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */ -#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */ -#define _3DSTATE_URB_GS 0x7833 /* GEN7+ */ -# define GEN7_URB_ENTRY_SIZE_SHIFT 16 -# define GEN7_URB_STARTING_ADDRESS_SHIFT 25 - -#define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */ -#define _3DSTATE_PUSH_CONSTANT_ALLOC_PS 0x7916 /* GEN7+ */ -# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 - -#define _3DSTATE_VIEWPORT_STATE_POINTERS 0x780d /* GEN6+ */ -# define GEN6_CC_VIEWPORT_MODIFY (1 << 12) -# define GEN6_SF_VIEWPORT_MODIFY (1 << 11) -# define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10) - -#define _3DSTATE_VIEWPORT_STATE_POINTERS_CC 0x7823 /* GEN7+ */ -#define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL 0x7821 /* GEN7+ */ - -#define _3DSTATE_SCISSOR_STATE_POINTERS 0x780f /* GEN6+ */ - -#define _3DSTATE_VS 0x7810 /* GEN6+ */ -/* DW2 */ -# define GEN6_VS_SPF_MODE (1 << 31) -# define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30) -# define GEN6_VS_SAMPLER_COUNT_SHIFT 27 -# define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 -# define GEN6_VS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) -# define GEN6_VS_FLOATING_POINT_MODE_ALT (1 << 16) -/* DW4 */ -# define GEN6_VS_DISPATCH_START_GRF_SHIFT 20 -# define GEN6_VS_URB_READ_LENGTH_SHIFT 11 -# define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4 -/* DW5 */ -# define GEN6_VS_MAX_THREADS_SHIFT 25 -# define HSW_VS_MAX_THREADS_SHIFT 23 -# define GEN6_VS_STATISTICS_ENABLE (1 << 10) -# define GEN6_VS_CACHE_DISABLE (1 << 1) -# define GEN6_VS_ENABLE (1 << 0) - -#define _3DSTATE_GS 0x7811 /* GEN6+ */ -/* DW2 */ -# define GEN6_GS_SPF_MODE (1 << 31) -# define GEN6_GS_VECTOR_MASK_ENABLE (1 << 30) -# define GEN6_GS_SAMPLER_COUNT_SHIFT 27 -# define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 -# define GEN6_GS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) -# define GEN6_GS_FLOATING_POINT_MODE_ALT (1 << 16) -/* DW4 */ -# define GEN6_GS_URB_READ_LENGTH_SHIFT 11 -# define GEN7_GS_INCLUDE_VERTEX_HANDLES (1 << 10) -# define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4 -# define GEN6_GS_DISPATCH_START_GRF_SHIFT 0 -/* DW5 */ -# define GEN6_GS_MAX_THREADS_SHIFT 25 -# define GEN6_GS_STATISTICS_ENABLE (1 << 10) -# define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9) -# define GEN6_GS_RENDERING_ENABLE (1 << 8) -# define GEN7_GS_ENABLE (1 << 0) -/* DW6 */ -# define GEN6_GS_REORDER (1 << 30) -# define GEN6_GS_DISCARD_ADJACENCY (1 << 29) -# define GEN6_GS_SVBI_PAYLOAD_ENABLE (1 << 28) -# define GEN6_GS_SVBI_POSTINCREMENT_ENABLE (1 << 27) -# define GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT 16 -# define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK INTEL_MASK(25, 16) -# define GEN6_GS_ENABLE (1 << 15) - -# define BRW_GS_EDGE_INDICATOR_0 (1 << 8) -# define BRW_GS_EDGE_INDICATOR_1 (1 << 9) - -#define _3DSTATE_HS 0x781B /* GEN7+ */ -#define _3DSTATE_TE 0x781C /* GEN7+ */ -#define _3DSTATE_DS 0x781D /* GEN7+ */ - -#define _3DSTATE_CLIP 0x7812 /* GEN6+ */ -/* DW1 */ -# define GEN7_CLIP_WINDING_CW (0 << 20) -# define GEN7_CLIP_WINDING_CCW (1 << 20) -# define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8 (0 << 19) -# define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4 (1 << 19) -# define GEN7_CLIP_EARLY_CULL (1 << 18) -# define GEN7_CLIP_CULLMODE_BOTH (0 << 16) -# define GEN7_CLIP_CULLMODE_NONE (1 << 16) -# define GEN7_CLIP_CULLMODE_FRONT (2 << 16) -# define GEN7_CLIP_CULLMODE_BACK (3 << 16) -# define GEN6_CLIP_STATISTICS_ENABLE (1 << 10) -/** - * Just does cheap culling based on the clip distance. Bits must be - * disjoint with USER_CLIP_CLIP_DISTANCE bits. - */ -# define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT 0 -/* DW2 */ -# define GEN6_CLIP_ENABLE (1 << 31) -# define GEN6_CLIP_API_OGL (0 << 30) -# define GEN6_CLIP_API_D3D (1 << 30) -# define GEN6_CLIP_XY_TEST (1 << 28) -# define GEN6_CLIP_Z_TEST (1 << 27) -# define GEN6_CLIP_GB_TEST (1 << 26) -/** 8-bit field of which user clip distances to clip aganist. */ -# define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT 16 -# define GEN6_CLIP_MODE_NORMAL (0 << 13) -# define GEN6_CLIP_MODE_REJECT_ALL (3 << 13) -# define GEN6_CLIP_MODE_ACCEPT_ALL (4 << 13) -# define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE (1 << 9) -# define GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE (1 << 8) -# define GEN6_CLIP_TRI_PROVOKE_SHIFT 4 -# define GEN6_CLIP_LINE_PROVOKE_SHIFT 2 -# define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT 0 -/* DW3 */ -# define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17 -# define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6 -# define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5) - -#define _3DSTATE_SF 0x7813 /* GEN6+ */ -/* DW1 (for gen6) */ -# define GEN6_SF_NUM_OUTPUTS_SHIFT 22 -# define GEN6_SF_SWIZZLE_ENABLE (1 << 21) -# define GEN6_SF_POINT_SPRITE_UPPERLEFT (0 << 20) -# define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20) -# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 -# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 -/* DW2 */ -# define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS (1 << 11) -# define GEN6_SF_STATISTICS_ENABLE (1 << 10) -# define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID (1 << 9) -# define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME (1 << 8) -# define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT (1 << 7) -# define GEN6_SF_FRONT_SOLID (0 << 5) -# define GEN6_SF_FRONT_WIREFRAME (1 << 5) -# define GEN6_SF_FRONT_POINT (2 << 5) -# define GEN6_SF_BACK_SOLID (0 << 3) -# define GEN6_SF_BACK_WIREFRAME (1 << 3) -# define GEN6_SF_BACK_POINT (2 << 3) -# define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE (1 << 1) -# define GEN6_SF_WINDING_CCW (1 << 0) -/* DW3 */ -# define GEN6_SF_LINE_AA_ENABLE (1 << 31) -# define GEN6_SF_CULL_BOTH (0 << 29) -# define GEN6_SF_CULL_NONE (1 << 29) -# define GEN6_SF_CULL_FRONT (2 << 29) -# define GEN6_SF_CULL_BACK (3 << 29) -# define GEN6_SF_LINE_WIDTH_SHIFT 18 /* U3.7 */ -# define GEN6_SF_LINE_END_CAP_WIDTH_0_5 (0 << 16) -# define GEN6_SF_LINE_END_CAP_WIDTH_1_0 (1 << 16) -# define GEN6_SF_LINE_END_CAP_WIDTH_2_0 (2 << 16) -# define GEN6_SF_LINE_END_CAP_WIDTH_4_0 (3 << 16) -# define GEN6_SF_SCISSOR_ENABLE (1 << 11) -# define GEN6_SF_MSRAST_OFF_PIXEL (0 << 8) -# define GEN6_SF_MSRAST_OFF_PATTERN (1 << 8) -# define GEN6_SF_MSRAST_ON_PIXEL (2 << 8) -# define GEN6_SF_MSRAST_ON_PATTERN (3 << 8) -/* DW4 */ -# define GEN6_SF_TRI_PROVOKE_SHIFT 29 -# define GEN6_SF_LINE_PROVOKE_SHIFT 27 -# define GEN6_SF_TRIFAN_PROVOKE_SHIFT 25 -# define GEN6_SF_LINE_AA_MODE_MANHATTAN (0 << 14) -# define GEN6_SF_LINE_AA_MODE_TRUE (1 << 14) -# define GEN6_SF_VERTEX_SUBPIXEL_8BITS (0 << 12) -# define GEN6_SF_VERTEX_SUBPIXEL_4BITS (1 << 12) -# define GEN6_SF_USE_STATE_POINT_WIDTH (1 << 11) -# define GEN6_SF_POINT_WIDTH_SHIFT 0 /* U8.3 */ -/* DW5: depth offset constant */ -/* DW6: depth offset scale */ -/* DW7: depth offset clamp */ -/* DW8 */ -# define ATTRIBUTE_1_OVERRIDE_W (1 << 31) -# define ATTRIBUTE_1_OVERRIDE_Z (1 << 30) -# define ATTRIBUTE_1_OVERRIDE_Y (1 << 29) -# define ATTRIBUTE_1_OVERRIDE_X (1 << 28) -# define ATTRIBUTE_1_CONST_SOURCE_SHIFT 25 -# define ATTRIBUTE_1_SWIZZLE_SHIFT 22 -# define ATTRIBUTE_1_SOURCE_SHIFT 16 -# define ATTRIBUTE_0_OVERRIDE_W (1 << 15) -# define ATTRIBUTE_0_OVERRIDE_Z (1 << 14) -# define ATTRIBUTE_0_OVERRIDE_Y (1 << 13) -# define ATTRIBUTE_0_OVERRIDE_X (1 << 12) -# define ATTRIBUTE_0_CONST_SOURCE_SHIFT 9 -# define ATTRIBUTE_0_SWIZZLE_SHIFT 6 -# define ATTRIBUTE_0_SOURCE_SHIFT 0 - -# define ATTRIBUTE_SWIZZLE_INPUTATTR 0 -# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1 -# define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2 -# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3 -# define ATTRIBUTE_SWIZZLE_SHIFT 6 - -/* DW16: Point sprite texture coordinate enables */ -/* DW17: Constant interpolation enables */ -/* DW18: attr 0-7 wrap shortest enables */ -/* DW19: attr 8-16 wrap shortest enables */ - -/* On GEN7, many fields of 3DSTATE_SF were split out into a new command: - * 3DSTATE_SBE. The remaining fields live in different DWords, but retain - * the same bit-offset. The only new field: - */ -/* GEN7/DW1: */ -# define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12 -/* GEN7/DW2: */ -# define HSW_SF_LINE_STIPPLE_ENABLE 14 - -#define _3DSTATE_SBE 0x781F /* GEN7+ */ -/* DW1 */ -# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) -# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22 -# define GEN7_SBE_SWIZZLE_ENABLE (1 << 21) -# define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20) -# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 -# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 -/* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */ -/* DW10: Point sprite texture coordinate enables */ -/* DW11: Constant interpolation enables */ -/* DW12: attr 0-7 wrap shortest enables */ -/* DW13: attr 8-16 wrap shortest enables */ - -enum brw_wm_barycentric_interp_mode { - BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC = 0, - BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC = 1, - BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC = 2, - BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC = 3, - BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC = 4, - BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC = 5, - BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT = 6 -}; -#define BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS \ - ((1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC) | \ - (1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC) | \ - (1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC)) - -#define _3DSTATE_WM 0x7814 /* GEN6+ */ -/* DW1: kernel pointer */ -/* DW2 */ -# define GEN6_WM_SPF_MODE (1 << 31) -# define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30) -# define GEN6_WM_SAMPLER_COUNT_SHIFT 27 -# define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 -# define GEN6_WM_FLOATING_POINT_MODE_IEEE_754 (0 << 16) -# define GEN6_WM_FLOATING_POINT_MODE_ALT (1 << 16) -/* DW3: scratch space */ -/* DW4 */ -# define GEN6_WM_STATISTICS_ENABLE (1 << 31) -# define GEN6_WM_DEPTH_CLEAR (1 << 30) -# define GEN6_WM_DEPTH_RESOLVE (1 << 28) -# define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) -# define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16 -# define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8 -# define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0 -/* DW5 */ -# define GEN6_WM_MAX_THREADS_SHIFT 25 -# define GEN6_WM_KILL_ENABLE (1 << 22) -# define GEN6_WM_COMPUTED_DEPTH (1 << 21) -# define GEN6_WM_USES_SOURCE_DEPTH (1 << 20) -# define GEN6_WM_DISPATCH_ENABLE (1 << 19) -# define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16) -# define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16) -# define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16) -# define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16) -# define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14) -# define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14) -# define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14) -# define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14) -# define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13) -# define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 11) -# define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9) -# define GEN6_WM_USES_SOURCE_W (1 << 8) -# define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7) -# define GEN6_WM_32_DISPATCH_ENABLE (1 << 2) -# define GEN6_WM_16_DISPATCH_ENABLE (1 << 1) -# define GEN6_WM_8_DISPATCH_ENABLE (1 << 0) -/* DW6 */ -# define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20 -# define GEN6_WM_POSOFFSET_NONE (0 << 18) -# define GEN6_WM_POSOFFSET_CENTROID (2 << 18) -# define GEN6_WM_POSOFFSET_SAMPLE (3 << 18) -# define GEN6_WM_POSITION_ZW_PIXEL (0 << 16) -# define GEN6_WM_POSITION_ZW_CENTROID (2 << 16) -# define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16) -# define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) -# define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) -# define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) -# define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) -# define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) -# define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) -# define GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 10 -# define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9) -# define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1) -# define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1) -# define GEN6_WM_MSRAST_ON_PIXEL (2 << 1) -# define GEN6_WM_MSRAST_ON_PATTERN (3 << 1) -# define GEN6_WM_MSDISPMODE_PERSAMPLE (0 << 0) -# define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0) -/* DW7: kernel 1 pointer */ -/* DW8: kernel 2 pointer */ - -#define _3DSTATE_CONSTANT_VS 0x7815 /* GEN6+ */ -#define _3DSTATE_CONSTANT_GS 0x7816 /* GEN6+ */ -#define _3DSTATE_CONSTANT_PS 0x7817 /* GEN6+ */ -# define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15) -# define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14) -# define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13) -# define GEN6_CONSTANT_BUFFER_0_ENABLE (1 << 12) - -#define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */ -#define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */ - -#define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */ -/* DW1 */ -# define SO_FUNCTION_ENABLE (1 << 31) -# define SO_RENDERING_DISABLE (1 << 30) -/* This selects which incoming rendering stream goes down the pipeline. The - * rendering stream is 0 if not defined by special cases in the GS state. - */ -# define SO_RENDER_STREAM_SELECT_SHIFT 27 -# define SO_RENDER_STREAM_SELECT_MASK INTEL_MASK(28, 27) -/* Controls reordering of TRISTRIP_* elements in stream output (not rendering). - */ -# define SO_REORDER_TRAILING (1 << 26) -/* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */ -# define SO_STATISTICS_ENABLE (1 << 25) -# define SO_BUFFER_ENABLE(n) (1 << (8 + (n))) -/* DW2 */ -# define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT 29 -# define SO_STREAM_3_VERTEX_READ_OFFSET_MASK INTEL_MASK(29, 29) -# define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT 24 -# define SO_STREAM_3_VERTEX_READ_LENGTH_MASK INTEL_MASK(28, 24) -# define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT 21 -# define SO_STREAM_2_VERTEX_READ_OFFSET_MASK INTEL_MASK(21, 21) -# define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT 16 -# define SO_STREAM_2_VERTEX_READ_LENGTH_MASK INTEL_MASK(20, 16) -# define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT 13 -# define SO_STREAM_1_VERTEX_READ_OFFSET_MASK INTEL_MASK(13, 13) -# define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT 8 -# define SO_STREAM_1_VERTEX_READ_LENGTH_MASK INTEL_MASK(12, 8) -# define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT 5 -# define SO_STREAM_0_VERTEX_READ_OFFSET_MASK INTEL_MASK(5, 5) -# define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT 0 -# define SO_STREAM_0_VERTEX_READ_LENGTH_MASK INTEL_MASK(4, 0) - -/* 3DSTATE_WM for Gen7 */ -/* DW1 */ -# define GEN7_WM_STATISTICS_ENABLE (1 << 31) -# define GEN7_WM_DEPTH_CLEAR (1 << 30) -# define GEN7_WM_DISPATCH_ENABLE (1 << 29) -# define GEN7_WM_DEPTH_RESOLVE (1 << 28) -# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) -# define GEN7_WM_KILL_ENABLE (1 << 25) -# define GEN7_WM_PSCDEPTH_OFF (0 << 23) -# define GEN7_WM_PSCDEPTH_ON (1 << 23) -# define GEN7_WM_PSCDEPTH_ON_GE (2 << 23) -# define GEN7_WM_PSCDEPTH_ON_LE (3 << 23) -# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) -# define GEN7_WM_USES_SOURCE_W (1 << 19) -# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) -# define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) -# define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17) -# define GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 11 -# define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10) -# define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8) -# define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8) -# define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8) -# define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8) -# define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6) -# define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6) -# define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6) -# define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6) -# define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4) -# define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3) -# define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2) -# define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0) -# define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0) -# define GEN7_WM_MSRAST_ON_PIXEL (2 << 0) -# define GEN7_WM_MSRAST_ON_PATTERN (3 << 0) -/* DW2 */ -# define GEN7_WM_MSDISPMODE_PERSAMPLE (0 << 31) -# define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31) - -#define _3DSTATE_PS 0x7820 /* GEN7+ */ -/* DW1: kernel pointer */ -/* DW2 */ -# define GEN7_PS_SPF_MODE (1 << 31) -# define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) -# define GEN7_PS_SAMPLER_COUNT_SHIFT 27 -# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 -# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) -# define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) -/* DW3: scratch space */ -/* DW4 */ -# define IVB_PS_MAX_THREADS_SHIFT 24 -# define HSW_PS_MAX_THREADS_SHIFT 23 -# define HSW_PS_SAMPLE_MASK_SHIFT 12 -# define HSW_PS_SAMPLE_MASK_MASK INTEL_MASK(19, 12) -# define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) -# define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) -# define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) -# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7) -# define GEN7_PS_POSOFFSET_NONE (0 << 3) -# define GEN7_PS_POSOFFSET_CENTROID (2 << 3) -# define GEN7_PS_POSOFFSET_SAMPLE (3 << 3) -# define GEN7_PS_32_DISPATCH_ENABLE (1 << 2) -# define GEN7_PS_16_DISPATCH_ENABLE (1 << 1) -# define GEN7_PS_8_DISPATCH_ENABLE (1 << 0) -/* DW5 */ -# define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16 -# define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8 -# define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0 -/* DW6: kernel 1 pointer */ -/* DW7: kernel 2 pointer */ - -#define _3DSTATE_SAMPLE_MASK 0x7818 /* GEN6+ */ - -#define _3DSTATE_DRAWING_RECTANGLE 0x7900 -#define _3DSTATE_BLEND_CONSTANT_COLOR 0x7901 -#define _3DSTATE_CHROMA_KEY 0x7904 -#define _3DSTATE_DEPTH_BUFFER 0x7905 /* GEN4-6 */ -#define _3DSTATE_POLY_STIPPLE_OFFSET 0x7906 -#define _3DSTATE_POLY_STIPPLE_PATTERN 0x7907 -#define _3DSTATE_LINE_STIPPLE_PATTERN 0x7908 -#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909 -#define _3DSTATE_AA_LINE_PARAMETERS 0x790a /* G45+ */ - -#define _3DSTATE_GS_SVB_INDEX 0x790b /* CTG+ */ -/* DW1 */ -# define SVB_INDEX_SHIFT 29 -# define SVB_LOAD_INTERNAL_VERTEX_COUNT (1 << 0) /* SNB+ */ -/* DW2: SVB index */ -/* DW3: SVB maximum index */ - -#define _3DSTATE_MULTISAMPLE 0x790d /* GEN6+ */ -/* DW1 */ -# define MS_PIXEL_LOCATION_CENTER (0 << 4) -# define MS_PIXEL_LOCATION_UPPER_LEFT (1 << 4) -# define MS_NUMSAMPLES_1 (0 << 1) -# define MS_NUMSAMPLES_4 (2 << 1) -# define MS_NUMSAMPLES_8 (3 << 1) - -#define _3DSTATE_STENCIL_BUFFER 0x790e /* ILK, SNB */ -#define _3DSTATE_HIER_DEPTH_BUFFER 0x790f /* ILK, SNB */ - -#define GEN7_3DSTATE_CLEAR_PARAMS 0x7804 -#define GEN7_3DSTATE_DEPTH_BUFFER 0x7805 -#define GEN7_3DSTATE_STENCIL_BUFFER 0x7806 -# define HSW_STENCIL_ENABLED (1 << 31) -#define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807 - -#define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */ -# define GEN5_DEPTH_CLEAR_VALID (1 << 15) -/* DW1: depth clear value */ -/* DW2 */ -# define GEN7_DEPTH_CLEAR_VALID (1 << 0) - -#define _3DSTATE_SO_DECL_LIST 0x7917 /* GEN7+ */ -/* DW1 */ -# define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT 12 -# define SO_STREAM_TO_BUFFER_SELECTS_3_MASK INTEL_MASK(15, 12) -# define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT 8 -# define SO_STREAM_TO_BUFFER_SELECTS_2_MASK INTEL_MASK(11, 8) -# define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT 4 -# define SO_STREAM_TO_BUFFER_SELECTS_1_MASK INTEL_MASK(7, 4) -# define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT 0 -# define SO_STREAM_TO_BUFFER_SELECTS_0_MASK INTEL_MASK(3, 0) -/* DW2 */ -# define SO_NUM_ENTRIES_3_SHIFT 24 -# define SO_NUM_ENTRIES_3_MASK INTEL_MASK(31, 24) -# define SO_NUM_ENTRIES_2_SHIFT 16 -# define SO_NUM_ENTRIES_2_MASK INTEL_MASK(23, 16) -# define SO_NUM_ENTRIES_1_SHIFT 8 -# define SO_NUM_ENTRIES_1_MASK INTEL_MASK(15, 8) -# define SO_NUM_ENTRIES_0_SHIFT 0 -# define SO_NUM_ENTRIES_0_MASK INTEL_MASK(7, 0) - -/* SO_DECL DW0 */ -# define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT 12 -# define SO_DECL_OUTPUT_BUFFER_SLOT_MASK INTEL_MASK(13, 12) -# define SO_DECL_HOLE_FLAG (1 << 11) -# define SO_DECL_REGISTER_INDEX_SHIFT 4 -# define SO_DECL_REGISTER_INDEX_MASK INTEL_MASK(9, 4) -# define SO_DECL_COMPONENT_MASK_SHIFT 0 -# define SO_DECL_COMPONENT_MASK_MASK INTEL_MASK(3, 0) - -#define _3DSTATE_SO_BUFFER 0x7918 /* GEN7+ */ -/* DW1 */ -# define SO_BUFFER_INDEX_SHIFT 29 -# define SO_BUFFER_INDEX_MASK INTEL_MASK(30, 29) -# define SO_BUFFER_PITCH_SHIFT 0 -# define SO_BUFFER_PITCH_MASK INTEL_MASK(11, 0) -/* DW2: start address */ -/* DW3: end address. */ - -#define CMD_PIPE_CONTROL 0x7a00 - -#define CMD_MI_FLUSH 0x0200 - - -/* Bitfields for the URB_WRITE message, DW2 of message header: */ -#define URB_WRITE_PRIM_END 0x1 -#define URB_WRITE_PRIM_START 0x2 -#define URB_WRITE_PRIM_TYPE_SHIFT 2 - - -/* Maximum number of entries that can be addressed using a binding table - * pointer of type SURFTYPE_BUFFER - */ -#define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27) - -#endif diff --git a/src/gallium/drivers/ilo/include/brw_structs.h b/src/gallium/drivers/ilo/include/brw_structs.h deleted file mode 100644 index 07f8d3aca7d..00000000000 --- a/src/gallium/drivers/ilo/include/brw_structs.h +++ /dev/null @@ -1,1453 +0,0 @@ -/* - Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics to - develop this 3D driver. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial - portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - **********************************************************************/ - /* - * Authors: - * Keith Whitwell <[email protected]> - */ - - -#ifndef BRW_STRUCTS_H -#define BRW_STRUCTS_H - -/* These seem to be passed around as function args, so it works out - * better to keep them as #defines: - */ -#define BRW_FLUSH_READ_CACHE 0x1 -#define BRW_FLUSH_STATE_CACHE 0x2 -#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 -#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 - -struct brw_urb_fence -{ - struct - { - GLuint length:8; - GLuint vs_realloc:1; - GLuint gs_realloc:1; - GLuint clp_realloc:1; - GLuint sf_realloc:1; - GLuint vfe_realloc:1; - GLuint cs_realloc:1; - GLuint pad:2; - GLuint opcode:16; - } header; - - struct - { - GLuint vs_fence:10; - GLuint gs_fence:10; - GLuint clp_fence:10; - GLuint pad:2; - } bits0; - - struct - { - GLuint sf_fence:10; - GLuint vf_fence:10; - GLuint cs_fence:11; - GLuint pad:1; - } bits1; -}; - -/* State structs for the various fixed function units: - */ - - -struct thread0 -{ - GLuint pad0:1; - GLuint grf_reg_count:3; - GLuint pad1:2; - GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */ -}; - -struct thread1 -{ - GLuint ext_halt_exception_enable:1; - GLuint sw_exception_enable:1; - GLuint mask_stack_exception_enable:1; - GLuint timeout_exception_enable:1; - GLuint illegal_op_exception_enable:1; - GLuint pad0:3; - GLuint depth_coef_urb_read_offset:6; /* WM only */ - GLuint pad1:2; - GLuint floating_point_mode:1; - GLuint thread_priority:1; - GLuint binding_table_entry_count:8; - GLuint pad3:5; - GLuint single_program_flow:1; -}; - -struct thread2 -{ - GLuint per_thread_scratch_space:4; - GLuint pad0:6; - GLuint scratch_space_base_pointer:22; -}; - - -struct thread3 -{ - GLuint dispatch_grf_start_reg:4; - GLuint urb_entry_read_offset:6; - GLuint pad0:1; - GLuint urb_entry_read_length:6; - GLuint pad1:1; - GLuint const_urb_entry_read_offset:6; - GLuint pad2:1; - GLuint const_urb_entry_read_length:6; - GLuint pad3:1; -}; - - - -struct brw_clip_unit_state -{ - struct thread0 thread0; - struct - { - GLuint pad0:7; - GLuint sw_exception_enable:1; - GLuint pad1:3; - GLuint mask_stack_exception_enable:1; - GLuint pad2:1; - GLuint illegal_op_exception_enable:1; - GLuint pad3:2; - GLuint floating_point_mode:1; - GLuint thread_priority:1; - GLuint binding_table_entry_count:8; - GLuint pad4:5; - GLuint single_program_flow:1; - } thread1; - - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:9; - GLuint gs_output_stats:1; /* not always */ - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:5; /* may be less */ - GLuint pad3:2; - } thread4; - - struct - { - GLuint pad0:13; - GLuint clip_mode:3; - GLuint userclip_enable_flags:8; - GLuint userclip_must_clip:1; - GLuint negative_w_clip_test:1; - GLuint guard_band_enable:1; - GLuint viewport_z_clip_enable:1; - GLuint viewport_xy_clip_enable:1; - GLuint vertex_position_space:1; - GLuint api_mode:1; - GLuint pad2:1; - } clip5; - - struct - { - GLuint pad0:5; - GLuint clipper_viewport_state_ptr:27; - } clip6; - - - GLfloat viewport_xmin; - GLfloat viewport_xmax; - GLfloat viewport_ymin; - GLfloat viewport_ymax; -}; - -struct gen6_blend_state -{ - struct { - GLuint dest_blend_factor:5; - GLuint source_blend_factor:5; - GLuint pad3:1; - GLuint blend_func:3; - GLuint pad2:1; - GLuint ia_dest_blend_factor:5; - GLuint ia_source_blend_factor:5; - GLuint pad1:1; - GLuint ia_blend_func:3; - GLuint pad0:1; - GLuint ia_blend_enable:1; - GLuint blend_enable:1; - } blend0; - - struct { - GLuint post_blend_clamp_enable:1; - GLuint pre_blend_clamp_enable:1; - GLuint clamp_range:2; - GLuint pad0:4; - GLuint x_dither_offset:2; - GLuint y_dither_offset:2; - GLuint dither_enable:1; - GLuint alpha_test_func:3; - GLuint alpha_test_enable:1; - GLuint pad1:1; - GLuint logic_op_func:4; - GLuint logic_op_enable:1; - GLuint pad2:1; - GLuint write_disable_b:1; - GLuint write_disable_g:1; - GLuint write_disable_r:1; - GLuint write_disable_a:1; - GLuint pad3:1; - GLuint alpha_to_coverage_dither:1; - GLuint alpha_to_one:1; - GLuint alpha_to_coverage:1; - } blend1; -}; - -struct gen6_color_calc_state -{ - struct { - GLuint alpha_test_format:1; - GLuint pad0:14; - GLuint round_disable:1; - GLuint bf_stencil_ref:8; - GLuint stencil_ref:8; - } cc0; - - union { - GLfloat alpha_ref_f; - struct { - GLuint ui:8; - GLuint pad0:24; - } alpha_ref_fi; - } cc1; - - GLfloat constant_r; - GLfloat constant_g; - GLfloat constant_b; - GLfloat constant_a; -}; - -struct gen6_depth_stencil_state -{ - struct { - GLuint pad0:3; - GLuint bf_stencil_pass_depth_pass_op:3; - GLuint bf_stencil_pass_depth_fail_op:3; - GLuint bf_stencil_fail_op:3; - GLuint bf_stencil_func:3; - GLuint bf_stencil_enable:1; - GLuint pad1:2; - GLuint stencil_write_enable:1; - GLuint stencil_pass_depth_pass_op:3; - GLuint stencil_pass_depth_fail_op:3; - GLuint stencil_fail_op:3; - GLuint stencil_func:3; - GLuint stencil_enable:1; - } ds0; - - struct { - GLuint bf_stencil_write_mask:8; - GLuint bf_stencil_test_mask:8; - GLuint stencil_write_mask:8; - GLuint stencil_test_mask:8; - } ds1; - - struct { - GLuint pad0:26; - GLuint depth_write_enable:1; - GLuint depth_test_func:3; - GLuint pad1:1; - GLuint depth_test_enable:1; - } ds2; -}; - -struct brw_cc_unit_state -{ - struct - { - GLuint pad0:3; - GLuint bf_stencil_pass_depth_pass_op:3; - GLuint bf_stencil_pass_depth_fail_op:3; - GLuint bf_stencil_fail_op:3; - GLuint bf_stencil_func:3; - GLuint bf_stencil_enable:1; - GLuint pad1:2; - GLuint stencil_write_enable:1; - GLuint stencil_pass_depth_pass_op:3; - GLuint stencil_pass_depth_fail_op:3; - GLuint stencil_fail_op:3; - GLuint stencil_func:3; - GLuint stencil_enable:1; - } cc0; - - - struct - { - GLuint bf_stencil_ref:8; - GLuint stencil_write_mask:8; - GLuint stencil_test_mask:8; - GLuint stencil_ref:8; - } cc1; - - - struct - { - GLuint logicop_enable:1; - GLuint pad0:10; - GLuint depth_write_enable:1; - GLuint depth_test_function:3; - GLuint depth_test:1; - GLuint bf_stencil_write_mask:8; - GLuint bf_stencil_test_mask:8; - } cc2; - - - struct - { - GLuint pad0:8; - GLuint alpha_test_func:3; - GLuint alpha_test:1; - GLuint blend_enable:1; - GLuint ia_blend_enable:1; - GLuint pad1:1; - GLuint alpha_test_format:1; - GLuint pad2:16; - } cc3; - - struct - { - GLuint pad0:5; - GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ - } cc4; - - struct - { - GLuint pad0:2; - GLuint ia_dest_blend_factor:5; - GLuint ia_src_blend_factor:5; - GLuint ia_blend_function:3; - GLuint statistics_enable:1; - GLuint logicop_func:4; - GLuint pad1:11; - GLuint dither_enable:1; - } cc5; - - struct - { - GLuint clamp_post_alpha_blend:1; - GLuint clamp_pre_alpha_blend:1; - GLuint clamp_range:2; - GLuint pad0:11; - GLuint y_dither_offset:2; - GLuint x_dither_offset:2; - GLuint dest_blend_factor:5; - GLuint src_blend_factor:5; - GLuint blend_function:3; - } cc6; - - struct { - union { - GLfloat f; - GLubyte ub[4]; - } alpha_ref; - } cc7; -}; - -struct brw_sf_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:10; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:6; - GLuint pad3:1; - } thread4; - - struct - { - GLuint front_winding:1; - GLuint viewport_transform:1; - GLuint pad0:3; - GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ - } sf5; - - struct - { - GLuint pad0:9; - GLuint dest_org_vbias:4; - GLuint dest_org_hbias:4; - GLuint scissor:1; - GLuint disable_2x2_trifilter:1; - GLuint disable_zero_pix_trifilter:1; - GLuint point_rast_rule:2; - GLuint line_endcap_aa_region_width:2; - GLuint line_width:4; - GLuint fast_scissor_disable:1; - GLuint cull_mode:2; - GLuint aa_enable:1; - } sf6; - - struct - { - GLuint point_size:11; - GLuint use_point_size_state:1; - GLuint subpixel_precision:1; - GLuint sprite_point:1; - GLuint pad0:10; - GLuint aa_line_distance_mode:1; - GLuint trifan_pv:2; - GLuint linestrip_pv:2; - GLuint tristrip_pv:2; - GLuint line_last_pixel_enable:1; - } sf7; - -}; - -struct gen6_scissor_rect -{ - GLuint xmin:16; - GLuint ymin:16; - GLuint xmax:16; - GLuint ymax:16; -}; - -struct brw_gs_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:8; - GLuint rendering_enable:1; /* for Ironlake */ - GLuint pad4:1; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:5; - GLuint pad3:2; - } thread4; - - struct - { - GLuint sampler_count:3; - GLuint pad0:2; - GLuint sampler_state_pointer:27; - } gs5; - - - struct - { - GLuint max_vp_index:4; - GLuint pad0:12; - GLuint svbi_post_inc_value:10; - GLuint pad1:1; - GLuint svbi_post_inc_enable:1; - GLuint svbi_payload:1; - GLuint discard_adjaceny:1; - GLuint reorder_enable:1; - GLuint pad2:1; - } gs6; -}; - - -struct brw_vs_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:10; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:6; - GLuint pad3:1; - } thread4; - - struct - { - GLuint sampler_count:3; - GLuint pad0:2; - GLuint sampler_state_pointer:27; - } vs5; - - struct - { - GLuint vs_enable:1; - GLuint vert_cache_disable:1; - GLuint pad0:30; - } vs6; -}; - - -struct brw_wm_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct { - GLuint stats_enable:1; - GLuint depth_buffer_clear:1; - GLuint sampler_count:3; - GLuint sampler_state_pointer:27; - } wm4; - - struct - { - GLuint enable_8_pix:1; - GLuint enable_16_pix:1; - GLuint enable_32_pix:1; - GLuint enable_con_32_pix:1; - GLuint enable_con_64_pix:1; - GLuint pad0:1; - - /* These next four bits are for Ironlake+ */ - GLuint fast_span_coverage_enable:1; - GLuint depth_buffer_clear:1; - GLuint depth_buffer_resolve_enable:1; - GLuint hierarchical_depth_buffer_resolve_enable:1; - - GLuint legacy_global_depth_bias:1; - GLuint line_stipple:1; - GLuint depth_offset:1; - GLuint polygon_stipple:1; - GLuint line_aa_region_width:2; - GLuint line_endcap_aa_region_width:2; - GLuint early_depth_test:1; - GLuint thread_dispatch_enable:1; - GLuint program_uses_depth:1; - GLuint program_computes_depth:1; - GLuint program_uses_killpixel:1; - GLuint legacy_line_rast: 1; - GLuint transposed_urb_read_enable:1; - GLuint max_threads:7; - } wm5; - - GLfloat global_depth_offset_constant; - GLfloat global_depth_offset_scale; - - /* for Ironlake only */ - struct { - GLuint pad0:1; - GLuint grf_reg_count_1:3; - GLuint pad1:2; - GLuint kernel_start_pointer_1:26; - } wm8; - - struct { - GLuint pad0:1; - GLuint grf_reg_count_2:3; - GLuint pad1:2; - GLuint kernel_start_pointer_2:26; - } wm9; - - struct { - GLuint pad0:1; - GLuint grf_reg_count_3:3; - GLuint pad1:2; - GLuint kernel_start_pointer_3:26; - } wm10; -}; - -struct brw_sampler_default_color { - GLfloat color[4]; -}; - -struct gen5_sampler_default_color { - uint8_t ub[4]; - float f[4]; - uint16_t hf[4]; - uint16_t us[4]; - int16_t s[4]; - uint8_t b[4]; -}; - -struct brw_sampler_state -{ - - struct - { - GLuint shadow_function:3; - GLuint lod_bias:11; - GLuint min_filter:3; - GLuint mag_filter:3; - GLuint mip_filter:2; - GLuint base_level:5; - GLuint min_mag_neq:1; - GLuint lod_preclamp:1; - GLuint default_color_mode:1; - GLuint pad0:1; - GLuint disable:1; - } ss0; - - struct - { - GLuint r_wrap_mode:3; - GLuint t_wrap_mode:3; - GLuint s_wrap_mode:3; - GLuint cube_control_mode:1; - GLuint pad:2; - GLuint max_lod:10; - GLuint min_lod:10; - } ss1; - - - struct - { - GLuint pad:5; - GLuint default_color_pointer:27; - } ss2; - - struct - { - GLuint non_normalized_coord:1; - GLuint pad:12; - GLuint address_round:6; - GLuint max_aniso:3; - GLuint chroma_key_mode:1; - GLuint chroma_key_index:2; - GLuint chroma_key_enable:1; - GLuint monochrome_filter_width:3; - GLuint monochrome_filter_height:3; - } ss3; -}; - -struct gen7_sampler_state -{ - struct - { - GLuint aniso_algorithm:1; - GLuint lod_bias:13; - GLuint min_filter:3; - GLuint mag_filter:3; - GLuint mip_filter:2; - GLuint base_level:5; - GLuint pad1:1; - GLuint lod_preclamp:1; - GLuint default_color_mode:1; - GLuint pad0:1; - GLuint disable:1; - } ss0; - - struct - { - GLuint cube_control_mode:1; - GLuint shadow_function:3; - GLuint pad:4; - GLuint max_lod:12; - GLuint min_lod:12; - } ss1; - - struct - { - GLuint pad:5; - GLuint default_color_pointer:27; - } ss2; - - struct - { - GLuint r_wrap_mode:3; - GLuint t_wrap_mode:3; - GLuint s_wrap_mode:3; - GLuint pad:1; - GLuint non_normalized_coord:1; - GLuint trilinear_quality:2; - GLuint address_round:6; - GLuint max_aniso:3; - GLuint chroma_key_mode:1; - GLuint chroma_key_index:2; - GLuint chroma_key_enable:1; - GLuint pad0:6; - } ss3; -}; - -struct brw_clipper_viewport -{ - GLfloat xmin; - GLfloat xmax; - GLfloat ymin; - GLfloat ymax; -}; - -struct brw_cc_viewport -{ - GLfloat min_depth; - GLfloat max_depth; -}; - -struct brw_sf_viewport -{ - struct { - GLfloat m00; - GLfloat m11; - GLfloat m22; - GLfloat m30; - GLfloat m31; - GLfloat m32; - } viewport; - - /* scissor coordinates are inclusive */ - struct { - GLshort xmin; - GLshort ymin; - GLshort xmax; - GLshort ymax; - } scissor; -}; - -struct gen6_sf_viewport { - GLfloat m00; - GLfloat m11; - GLfloat m22; - GLfloat m30; - GLfloat m31; - GLfloat m32; -}; - -struct gen7_sf_clip_viewport { - struct { - GLfloat m00; - GLfloat m11; - GLfloat m22; - GLfloat m30; - GLfloat m31; - GLfloat m32; - } viewport; - - GLuint pad0[2]; - - struct { - GLfloat xmin; - GLfloat xmax; - GLfloat ymin; - GLfloat ymax; - } guardband; - - GLfloat pad1[4]; -}; - -struct brw_vertex_element_state -{ - struct - { - GLuint src_offset:11; - GLuint pad:5; - GLuint src_format:9; - GLuint pad0:1; - GLuint valid:1; - GLuint vertex_buffer_index:5; - } ve0; - - struct - { - GLuint dst_offset:8; - GLuint pad:8; - GLuint vfcomponent3:4; - GLuint vfcomponent2:4; - GLuint vfcomponent1:4; - GLuint vfcomponent0:4; - } ve1; -}; - -struct brw_urb_immediate { - GLuint opcode:4; - GLuint offset:6; - GLuint swizzle_control:2; - GLuint pad:1; - GLuint allocate:1; - GLuint used:1; - GLuint complete:1; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; -}; - -/* Instruction format for the execution units: - */ - -struct brw_instruction -{ - struct - { - GLuint opcode:7; - GLuint pad:1; - GLuint access_mode:1; - GLuint mask_control:1; - GLuint dependency_control:2; - GLuint compression_control:2; /* gen6: quarter control */ - GLuint thread_control:2; - GLuint predicate_control:4; - GLuint predicate_inverse:1; - GLuint execution_size:3; - /** - * Conditional Modifier for most instructions. On Gen6+, this is also - * used for the SEND instruction's Message Target/SFID. - */ - GLuint destreg__conditionalmod:4; - GLuint acc_wr_control:1; - GLuint cmpt_control:1; - GLuint debug_control:1; - GLuint saturate:1; - } header; - - union { - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; - GLuint src1_reg_type:3; - GLuint nibctrl:1; /* gen7+ */ - GLuint dest_subreg_nr:5; - GLuint dest_reg_nr:8; - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } da1; - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; /* 0x00000c00 */ - GLuint src1_reg_type:3; /* 0x00007000 */ - GLuint nibctrl:1; /* gen7+ */ - GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ - GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } ia1; - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; - GLuint src1_reg_type:3; - GLuint nibctrl:1; /* gen7+ */ - GLuint dest_writemask:4; - GLuint dest_subreg_nr:1; - GLuint dest_reg_nr:8; - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } da16; - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; - GLuint src1_reg_type:3; - GLuint nibctrl:1; /* gen7+ */ - GLuint dest_writemask:4; - GLint dest_indirect_offset:6; - GLuint dest_subreg_nr:3; - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } ia16; - - struct { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; - GLuint src1_reg_type:3; - GLuint pad:1; - - GLint jump_count:16; - } branch_gen6; - - struct { - GLuint dest_reg_file:1; /* gen6, not gen7+ */ - GLuint flag_subreg_num:1; - GLuint flag_reg_nr:1; /* gen7+ */ - GLuint pad0:1; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src2_abs:1; - GLuint src2_negate:1; - GLuint src_type:2; /* gen7+ */ - GLuint dst_type:2; /* gen7+ */ - GLuint pad1:1; - GLuint nibctrl:1; /* gen7+ */ - GLuint pad2:1; - GLuint dest_writemask:4; - GLuint dest_subreg_nr:3; - GLuint dest_reg_nr:8; - } da3src; - - uint32_t ud; - } bits1; - - - union { - struct - { - GLuint src0_subreg_nr:5; - GLuint src0_reg_nr:8; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_horiz_stride:2; - GLuint src0_width:3; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; /* gen7+ */ - GLuint pad:5; - } da1; - - struct - { - GLint src0_indirect_offset:10; - GLuint src0_subreg_nr:3; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_horiz_stride:2; - GLuint src0_width:3; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; /* gen7+ */ - GLuint pad:5; - } ia1; - - struct - { - GLuint src0_swz_x:2; - GLuint src0_swz_y:2; - GLuint src0_subreg_nr:1; - GLuint src0_reg_nr:8; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_swz_z:2; - GLuint src0_swz_w:2; - GLuint pad0:1; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; /* gen7+ */ - GLuint pad1:5; - } da16; - - struct - { - GLuint src0_swz_x:2; - GLuint src0_swz_y:2; - GLint src0_indirect_offset:6; - GLuint src0_subreg_nr:3; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_swz_z:2; - GLuint src0_swz_w:2; - GLuint pad0:1; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; /* gen7+ */ - GLuint pad1:5; - } ia16; - - /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction. - * - * Does not apply to Gen6+. The SFID/message target moved to bits - * 27:24 of the header (destreg__conditionalmod); EOT is in bits3. - */ - struct - { - GLuint pad:26; - GLuint end_of_thread:1; - GLuint pad1:1; - GLuint sfid:4; - } send_gen5; /* for Ironlake only */ - - struct { - GLuint src0_rep_ctrl:1; - GLuint src0_swizzle:8; - GLuint src0_subreg_nr:3; - GLuint src0_reg_nr:8; - GLuint pad0:1; - GLuint src1_rep_ctrl:1; - GLuint src1_swizzle:8; - GLuint src1_subreg_nr_low:2; - } da3src; - - uint32_t ud; - } bits2; - - union - { - struct - { - GLuint src1_subreg_nr:5; - GLuint src1_reg_nr:8; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_horiz_stride:2; - GLuint src1_width:3; - GLuint src1_vert_stride:4; - GLuint pad0:7; - } da1; - - struct - { - GLuint src1_swz_x:2; - GLuint src1_swz_y:2; - GLuint src1_subreg_nr:1; - GLuint src1_reg_nr:8; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_swz_z:2; - GLuint src1_swz_w:2; - GLuint pad1:1; - GLuint src1_vert_stride:4; - GLuint pad2:7; - } da16; - - struct - { - GLint src1_indirect_offset:10; - GLuint src1_subreg_nr:3; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_horiz_stride:2; - GLuint src1_width:3; - GLuint src1_vert_stride:4; - GLuint pad1:7; - } ia1; - - struct - { - GLuint src1_swz_x:2; - GLuint src1_swz_y:2; - GLint src1_indirect_offset:6; - GLuint src1_subreg_nr:3; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint pad0:1; - GLuint src1_swz_z:2; - GLuint src1_swz_w:2; - GLuint pad1:1; - GLuint src1_vert_stride:4; - GLuint pad2:7; - } ia16; - - - struct - { - GLint jump_count:16; /* note: signed */ - GLuint pop_count:4; - GLuint pad0:12; - } if_else; - - /* This is also used for gen7 IF/ELSE instructions */ - struct - { - /* Signed jump distance to the ip to jump to if all channels - * are disabled after the break or continue. It should point - * to the end of the innermost control flow block, as that's - * where some channel could get re-enabled. - */ - int jip:16; - - /* Signed jump distance to the location to resume execution - * of this channel if it's enabled for the break or continue. - */ - int uip:16; - } break_cont; - - /** - * \defgroup SEND instructions / Message Descriptors - * - * @{ - */ - - /** - * Generic Message Descriptor for Gen4 SEND instructions. The structs - * below expand function_control to something specific for their - * message. Due to struct packing issues, they duplicate these bits. - * - * See the G45 PRM, Volume 4, Table 14-15. - */ - struct { - GLuint function_control:16; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } generic; - - /** - * Generic Message Descriptor for Gen5-7 SEND instructions. - * - * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most - * of the information on the SEND instruction is missing from the public - * Ironlake PRM.) - * - * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies. - * According to the SEND instruction description: - * "The MSb of the message description, the EOT field, always comes from - * bit 127 of the instruction word"...which is bit 31 of this field. - */ - struct { - GLuint function_control:19; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } generic_gen5; - - /** G45 PRM, Volume 4, Section 6.1.1.1 */ - struct { - GLuint function:4; - GLuint int_type:1; - GLuint precision:1; - GLuint saturate:1; - GLuint data_type:1; - GLuint pad0:8; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } math; - - /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */ - struct { - GLuint function:4; - GLuint int_type:1; - GLuint precision:1; - GLuint saturate:1; - GLuint data_type:1; - GLuint snapshot:1; - GLuint pad0:10; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } math_gen5; - - /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */ - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint return_format:2; - GLuint msg_type:2; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } sampler; - - /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */ - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint msg_type:4; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } sampler_g4x; - - /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */ - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint msg_type:4; - GLuint simd_mode:2; - GLuint pad0:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } sampler_gen5; - - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint msg_type:5; - GLuint simd_mode:2; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } sampler_gen7; - - struct brw_urb_immediate urb; - - struct { - GLuint opcode:4; - GLuint offset:6; - GLuint swizzle_control:2; - GLuint pad:1; - GLuint allocate:1; - GLuint used:1; - GLuint complete:1; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } urb_gen5; - - struct { - GLuint opcode:3; - GLuint offset:11; - GLuint swizzle_control:1; - GLuint complete:1; - GLuint per_slot_offset:1; - GLuint pad0:2; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } urb_gen7; - - /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:4; - GLuint msg_type:2; - GLuint target_cache:2; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } dp_read; - - /** G45 PRM, Volume 4, Section 5.10.1.1.2 */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint msg_type:3; - GLuint target_cache:2; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } dp_read_g4x; - - /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint msg_type:3; - GLuint target_cache:2; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_read_gen5; - - /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint last_render_target:1; - GLuint msg_type:3; - GLuint send_commit_msg:1; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } dp_write; - - /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint last_render_target:1; - GLuint msg_type:3; - GLuint send_commit_msg:1; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_write_gen5; - - /** - * Message for the Sandybridge Sampler Cache or Constant Cache Data Port. - * - * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1. - **/ - struct { - GLuint binding_table_index:8; - GLuint msg_control:5; - GLuint msg_type:3; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } gen6_dp_sampler_const_cache; - - /** - * Message for the Sandybridge Render Cache Data Port. - * - * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1, - * Section 3.9.2.1.1: Message Descriptor. - * - * "Slot Group Select" and "Last Render Target" are part of the - * 5-bit message control for Render Target Write messages. See - * Section 3.9.9.2.1 of the same volume. - */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint slot_group_select:1; - GLuint last_render_target:1; - GLuint msg_type:4; - GLuint send_commit_msg:1; - GLuint pad0:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } gen6_dp; - - /** - * Message for any of the Gen7 Data Port caches. - * - * Most fields are defined in BSpec volume 5c.2 Data Port / Messages / - * Data Port Messages / Message Descriptor. Once again, "Slot Group - * Select" and "Last Render Target" are part of the 6-bit message - * control for Render Target Writes. - */ - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint slot_group_select:1; - GLuint last_render_target:1; - GLuint msg_control_pad:1; - GLuint msg_type:4; - GLuint pad1:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad2:2; - GLuint end_of_thread:1; - } gen7_dp; - /** @} */ - - struct { - GLuint src1_subreg_nr_high:1; - GLuint src1_reg_nr:8; - GLuint pad0:1; - GLuint src2_rep_ctrl:1; - GLuint src2_swizzle:8; - GLuint src2_subreg_nr:3; - GLuint src2_reg_nr:8; - GLuint pad1:2; - } da3src; - - GLint d; - GLuint ud; - float f; - } bits3; -}; - -struct brw_compact_instruction { - struct { - unsigned opcode:7; /* 0- 6 */ - unsigned debug_control:1; /* 7- 7 */ - unsigned control_index:5; /* 8-12 */ - unsigned data_type_index:5; /* 13-17 */ - unsigned sub_reg_index:5; /* 18-22 */ - unsigned acc_wr_control:1; /* 23-23 */ - unsigned conditionalmod:4; /* 24-27 */ - unsigned flag_subreg_nr:1; /* 28-28 */ - unsigned cmpt_ctrl:1; /* 29-29 */ - unsigned src0_index:2; /* 30-31 */ - } dw0; - - struct { - unsigned src0_index:3; /* 32-24 */ - unsigned src1_index:5; /* 35-39 */ - unsigned dst_reg_nr:8; /* 40-47 */ - unsigned src0_reg_nr:8; /* 48-55 */ - unsigned src1_reg_nr:8; /* 56-63 */ - } dw1; -}; - -#endif diff --git a/src/gallium/drivers/ilo/shader/toy_compiler_disasm.c b/src/gallium/drivers/ilo/shader/toy_compiler_disasm.c index 1028940fbc4..a40d0cdb84f 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler_disasm.c +++ b/src/gallium/drivers/ilo/shader/toy_compiler_disasm.c @@ -1,1385 +1,1472 @@ /* - * Copyright © 2008 Keith Packard + * Mesa 3-D graphics library * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. + * Copyright (C) 2014 LunarG, Inc. * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chia-I Wu <[email protected]> */ #include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <getopt.h> -#include <unistd.h> -#include <stdarg.h> - -typedef short GLshort; -typedef int GLint; -typedef unsigned char GLubyte; -typedef unsigned int GLuint; -typedef float GLfloat; -#include <stdint.h> -#include "brw_defines.h" -#include "brw_structs.h" -static int brw_disasm (FILE *file, struct brw_instruction *inst, int gen); - +#include "genhw/genhw.h" #include "toy_compiler.h" -void -toy_compiler_disassemble(const struct ilo_dev_info *dev, - const void *kernel, int size, - bool dump_hex) -{ - const struct brw_instruction *instructions = kernel; - int i; - - for (i = 0; i < size / sizeof(*instructions); i++) { - if (dump_hex) { - const uint32_t *dwords = (const uint32_t *) &instructions[i]; - ilo_printf("0x%08x 0x%08x 0x%08x 0x%08x ", - dwords[3], dwords[2], dwords[1], dwords[0]); - } +#define DISASM_PRINTER_BUFFER_SIZE 256 +#define DISASM_PRINTER_COLUMN_WIDTH 16 - brw_disasm(stderr, (struct brw_instruction *) &instructions[i], - ILO_GEN_GET_MAJOR(dev->gen)); - } -} +#define READ(dw, field) (((dw) & field ## __MASK) >> field ## __SHIFT) -static const struct opcode_desc { - char *name; - int nsrc; - int ndst; -} opcode_descs[128] = { - [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 }, - - [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 }, - - [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, - - [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 }, -}; -static const struct opcode_desc *opcode = opcode_descs; - -static const char * const conditional_modifier[16] = { - [BRW_CONDITIONAL_NONE] = "", - [BRW_CONDITIONAL_Z] = ".e", - [BRW_CONDITIONAL_NZ] = ".ne", - [BRW_CONDITIONAL_G] = ".g", - [BRW_CONDITIONAL_GE] = ".ge", - [BRW_CONDITIONAL_L] = ".l", - [BRW_CONDITIONAL_LE] = ".le", - [BRW_CONDITIONAL_R] = ".r", - [BRW_CONDITIONAL_O] = ".o", - [BRW_CONDITIONAL_U] = ".u", +struct disasm_printer { + char buf[DISASM_PRINTER_BUFFER_SIZE]; + int len; }; -static const char * const negate[2] = { - [0] = "", - [1] = "-", -}; +struct disasm_operand { + unsigned file:2; + unsigned type:3; -static const char * const _abs[2] = { - [0] = "", - [1] = "(abs)", + unsigned addr_mode:1; + unsigned reg:8; + unsigned subreg:5; + unsigned addr_subreg:3; + unsigned addr_imm:10; }; -static const char * const vert_stride[16] = { - [0] = "0", - [1] = "1", - [2] = "2", - [3] = "4", - [4] = "8", - [5] = "16", - [6] = "32", - [15] = "VxH", -}; +struct disasm_dst_operand { + struct disasm_operand base; -static const char * const width[8] = { - [0] = "1", - [1] = "2", - [2] = "4", - [3] = "8", - [4] = "16", + unsigned horz_stride:2; + unsigned writemask:4; }; -static const char * const horiz_stride[4] = { - [0] = "0", - [1] = "1", - [2] = "2", - [3] = "4" +struct disasm_src_operand { + struct disasm_operand base; + + unsigned vert_stride:4; + unsigned width:3; + unsigned horz_stride:2; + unsigned swizzle_x:2; + unsigned swizzle_y:2; + unsigned swizzle_z:2; + unsigned swizzle_w:2; + unsigned negate:1; + unsigned absolute:1; }; -static const char * const chan_sel[4] = { - [0] = "x", - [1] = "y", - [2] = "z", - [3] = "w", +struct disasm_inst { + const struct ilo_dev_info *dev; + + unsigned has_jip:1; + unsigned has_uip:1; + + unsigned opcode:7; + unsigned access_mode:1; + unsigned mask_ctrl:1; + unsigned dep_ctrl:2; + unsigned qtr_ctrl:2; + unsigned thread_ctrl:2; + unsigned pred_ctrl:4; + unsigned pred_inv:1; + unsigned exec_size:3; + + unsigned cond_modifier:4; + unsigned sfid:4; + unsigned fc:4; + + unsigned acc_wr_ctrl:1; + unsigned cmpt_ctrl:1; + unsigned debug_ctrl:1; + unsigned saturate:1; + + unsigned nib_ctrl:1; + + unsigned flag_reg:1; + unsigned flag_subreg:1; + + struct disasm_dst_operand dst; + struct disasm_src_operand src0; + struct disasm_src_operand src1; + union { + struct disasm_src_operand src2; + uint32_t imm32; + } u; }; -static const char * const debug_ctrl[2] = { - [0] = "", - [1] = ".breakpoint" +static const struct { + const char *name; + int src_count; +} disasm_opcode_table[128] = { + [GEN6_OPCODE_ILLEGAL] = { "illegal", 0 }, + [GEN6_OPCODE_MOV] = { "mov", 1 }, + [GEN6_OPCODE_SEL] = { "sel", 2 }, + [GEN6_OPCODE_MOVI] = { "movi", 1 }, + [GEN6_OPCODE_NOT] = { "not", 1 }, + [GEN6_OPCODE_AND] = { "and", 2 }, + [GEN6_OPCODE_OR] = { "or", 2 }, + [GEN6_OPCODE_XOR] = { "xor", 2 }, + [GEN6_OPCODE_SHR] = { "shr", 2 }, + [GEN6_OPCODE_SHL] = { "shl", 2 }, + [GEN6_OPCODE_DIM] = { "dim", 1 }, + [GEN6_OPCODE_ASR] = { "asr", 2 }, + [GEN6_OPCODE_CMP] = { "cmp", 2 }, + [GEN6_OPCODE_CMPN] = { "cmpn", 2 }, + [GEN7_OPCODE_CSEL] = { "csel", 3 }, + [GEN7_OPCODE_F32TO16] = { "f32to16", 1 }, + [GEN7_OPCODE_F16TO32] = { "f16to32", 1 }, + [GEN7_OPCODE_BFREV] = { "bfrev", 1 }, + [GEN7_OPCODE_BFE] = { "bfe", 3 }, + [GEN7_OPCODE_BFI1] = { "bfi1", 2 }, + [GEN7_OPCODE_BFI2] = { "bfi2", 3 }, + [GEN6_OPCODE_JMPI] = { "jmpi", 1 }, + [GEN7_OPCODE_BRD] = { "brd", 1 }, + [GEN6_OPCODE_IF] = { "if", 2 }, + [GEN7_OPCODE_BRC] = { "brc", 1 }, + [GEN6_OPCODE_ELSE] = { "else", 1 }, + [GEN6_OPCODE_ENDIF] = { "endif", 0 }, + [GEN6_OPCODE_CASE] = { "case", 2 }, + [GEN6_OPCODE_WHILE] = { "while", 1 }, + [GEN6_OPCODE_BREAK] = { "break", 1 }, + [GEN6_OPCODE_CONT] = { "cont", 1 }, + [GEN6_OPCODE_HALT] = { "halt", 1 }, + [GEN75_OPCODE_CALLA] = { "calla", 1 }, + [GEN6_OPCODE_CALL] = { "call", 1 }, + [GEN6_OPCODE_RETURN] = { "return", 1 }, + [GEN6_OPCODE_WAIT] = { "wait", 1 }, + [GEN6_OPCODE_SEND] = { "send", 1 }, + [GEN6_OPCODE_SENDC] = { "sendc", 1 }, + [GEN6_OPCODE_MATH] = { "math", 2 }, + [GEN6_OPCODE_ADD] = { "add", 2 }, + [GEN6_OPCODE_MUL] = { "mul", 2 }, + [GEN6_OPCODE_AVG] = { "avg", 2 }, + [GEN6_OPCODE_FRC] = { "frc", 1 }, + [GEN6_OPCODE_RNDU] = { "rndu", 1 }, + [GEN6_OPCODE_RNDD] = { "rndd", 1 }, + [GEN6_OPCODE_RNDE] = { "rnde", 1 }, + [GEN6_OPCODE_RNDZ] = { "rndz", 1 }, + [GEN6_OPCODE_MAC] = { "mac", 2 }, + [GEN6_OPCODE_MACH] = { "mach", 2 }, + [GEN6_OPCODE_LZD] = { "lzd", 1 }, + [GEN7_OPCODE_FBH] = { "fbh", 1 }, + [GEN7_OPCODE_FBL] = { "fbl", 1 }, + [GEN7_OPCODE_CBIT] = { "cbit", 1 }, + [GEN7_OPCODE_ADDC] = { "addc", 2 }, + [GEN7_OPCODE_SUBB] = { "subb", 2 }, + [GEN6_OPCODE_SAD2] = { "sad2", 2 }, + [GEN6_OPCODE_SADA2] = { "sada2", 2 }, + [GEN6_OPCODE_DP4] = { "dp4", 2 }, + [GEN6_OPCODE_DPH] = { "dph", 2 }, + [GEN6_OPCODE_DP3] = { "dp3", 2 }, + [GEN6_OPCODE_DP2] = { "dp2", 2 }, + [GEN6_OPCODE_LINE] = { "line", 2 }, + [GEN6_OPCODE_PLN] = { "pln", 2 }, + [GEN6_OPCODE_MAD] = { "mad", 3 }, + [GEN6_OPCODE_LRP] = { "lrp", 3 }, + [GEN6_OPCODE_NOP] = { "nop", 0 }, }; -static const char * const saturate[2] = { - [0] = "", - [1] = ".sat" -}; +static void +disasm_inst_decode_dw0_gen6(struct disasm_inst *inst, uint32_t dw0) +{ + inst->opcode = READ(dw0, GEN6_INST_OPCODE); + + switch (inst->opcode) { + case GEN6_OPCODE_IF: + inst->has_jip = true; + inst->has_uip = (inst->dev->gen >= ILO_GEN(7)); + break; + case GEN6_OPCODE_BREAK: + case GEN6_OPCODE_CONT: + case GEN6_OPCODE_HALT: + inst->has_uip = true; + /* fall through */ + case GEN6_OPCODE_JMPI: + case GEN7_OPCODE_BRD: + case GEN7_OPCODE_BRC: + case GEN6_OPCODE_ELSE: + case GEN6_OPCODE_ENDIF: + case GEN6_OPCODE_CASE: + case GEN6_OPCODE_WHILE: + case GEN75_OPCODE_CALLA: + case GEN6_OPCODE_CALL: + case GEN6_OPCODE_RETURN: + inst->has_jip = true; + break; + default: + break; + } -static const char * const accwr[2] = { - [0] = "", - [1] = "AccWrEnable" -}; + inst->access_mode = READ(dw0, GEN6_INST_ACCESSMODE); + inst->mask_ctrl = READ(dw0, GEN6_INST_MASKCTRL); + inst->dep_ctrl = READ(dw0, GEN6_INST_DEPCTRL); + inst->qtr_ctrl = READ(dw0, GEN6_INST_QTRCTRL); + inst->thread_ctrl = READ(dw0, GEN6_INST_THREADCTRL); + inst->pred_ctrl = READ(dw0, GEN6_INST_PREDCTRL); + + inst->pred_inv = (bool) (dw0 & GEN6_INST_PREDINV); + + inst->exec_size = READ(dw0, GEN6_INST_EXECSIZE); + + switch (inst->opcode) { + case GEN6_OPCODE_SEND: + case GEN6_OPCODE_SENDC: + inst->sfid = READ(dw0, GEN6_INST_SFID); + break; + case GEN6_OPCODE_MATH: + inst->fc = READ(dw0, GEN6_INST_FC); + break; + default: + inst->cond_modifier = READ(dw0, GEN6_INST_CONDMODIFIER); + break; + } -static const char * const wectrl[2] = { - [0] = "WE_normal", - [1] = "WE_all" -}; + inst->acc_wr_ctrl = (bool) (dw0 & GEN6_INST_ACCWRCTRL); + inst->cmpt_ctrl = (bool) (dw0 & GEN6_INST_CMPTCTRL); + inst->debug_ctrl = (bool) (dw0 & GEN6_INST_DEBUGCTRL); + inst->saturate = (bool) (dw0 & GEN6_INST_SATURATE); +} -static const char * const exec_size[8] = { - [0] = "1", - [1] = "2", - [2] = "4", - [3] = "8", - [4] = "16", - [5] = "32" -}; +static bool +disasm_inst_jip_in_dw1_high_gen6(const struct disasm_inst *inst) +{ + return (inst->dev->gen == ILO_GEN(6) && inst->has_jip && !inst->has_uip); +} -static const char * const pred_inv[2] = { - [0] = "+", - [1] = "-" -}; +static void +disasm_inst_decode_dw1_gen6(struct disasm_inst *inst, uint32_t dw1) +{ + inst->dst.base.file = READ(dw1, GEN6_INST_DST_FILE); + inst->dst.base.type = READ(dw1, GEN6_INST_DST_TYPE); + inst->src0.base.file = READ(dw1, GEN6_INST_SRC0_FILE); + inst->src0.base.type = READ(dw1, GEN6_INST_SRC0_TYPE); + inst->src1.base.file = READ(dw1, GEN6_INST_SRC1_FILE); + inst->src1.base.type = READ(dw1, GEN6_INST_SRC1_TYPE); + + if (inst->dev->gen >= ILO_GEN(7)) + inst->nib_ctrl = (bool) (dw1 & GEN7_INST_NIBCTRL); + + if (disasm_inst_jip_in_dw1_high_gen6(inst)) { + inst->u.imm32 = dw1 >> 16; + return; + } -static const char * const pred_ctrl_align16[16] = { - [1] = "", - [2] = ".x", - [3] = ".y", - [4] = ".z", - [5] = ".w", - [6] = ".any4h", - [7] = ".all4h", -}; + inst->dst.base.addr_mode = READ(dw1, GEN6_INST_DST_ADDRMODE); -static const char * const pred_ctrl_align1[16] = { - [1] = "", - [2] = ".anyv", - [3] = ".allv", - [4] = ".any2h", - [5] = ".all2h", - [6] = ".any4h", - [7] = ".all4h", - [8] = ".any8h", - [9] = ".all8h", - [10] = ".any16h", - [11] = ".all16h", -}; + if (inst->dst.base.addr_mode == GEN6_ADDRMODE_DIRECT) { + inst->dst.base.reg = READ(dw1, GEN6_INST_DST_REG); -static const char * const thread_ctrl[4] = { - [0] = "", - [2] = "switch" -}; + if (inst->access_mode == GEN6_ALIGN_1) { + inst->dst.base.subreg = READ(dw1, GEN6_INST_DST_SUBREG); + } else { + inst->dst.base.subreg = READ(dw1, GEN6_INST_DST_SUBREG_ALIGN16) << + GEN6_INST_DST_SUBREG_ALIGN16__SHR; + } + } else { + inst->dst.base.addr_subreg = READ(dw1, GEN6_INST_DST_ADDR_SUBREG); + + if (inst->access_mode == GEN6_ALIGN_1) { + inst->dst.base.addr_imm = READ(dw1, GEN6_INST_DST_ADDR_IMM); + } else { + inst->dst.base.addr_imm = READ(dw1, GEN6_INST_DST_ADDR_IMM_ALIGN16) << + GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR; + } + } -static const char * const compr_ctrl[4] = { - [0] = "", - [1] = "sechalf", - [2] = "compr", - [3] = "compr4", -}; + inst->dst.horz_stride = READ(dw1, GEN6_INST_DST_HORZSTRIDE); -static const char * const dep_ctrl[4] = { - [0] = "", - [1] = "NoDDClr", - [2] = "NoDDChk", - [3] = "NoDDClr,NoDDChk", -}; + if (inst->access_mode == GEN6_ALIGN_1) + inst->dst.writemask = 0xf; + else + inst->dst.writemask = READ(dw1, GEN6_INST_DST_WRITEMASK); +} -static const char * const mask_ctrl[4] = { - [0] = "", - [1] = "nomask", -}; +static void +disasm_inst_decode_dw2_dw3_gen6(struct disasm_inst *inst, + uint32_t dw2, uint32_t dw3) +{ + int count, i; -static const char * const access_mode[2] = { - [0] = "align1", - [1] = "align16", -}; + if (inst->dev->gen >= ILO_GEN(7)) + inst->flag_reg = READ(dw2, GEN7_INST_FLAG_REG); -static const char * const reg_encoding[8] = { - [0] = "UD", - [1] = "D", - [2] = "UW", - [3] = "W", - [4] = "UB", - [5] = "B", - [7] = "F" -}; + inst->flag_subreg = READ(dw2, GEN6_INST_FLAG_SUBREG); -const int reg_type_size[8] = { - [0] = 4, - [1] = 4, - [2] = 2, - [3] = 2, - [4] = 1, - [5] = 1, - [7] = 4 -}; + if (inst->src0.base.file == GEN6_FILE_IMM || + inst->src1.base.file == GEN6_FILE_IMM) { + count = 1; + if (!disasm_inst_jip_in_dw1_high_gen6(inst)) + inst->u.imm32 = dw3; + } else { + count = 2; + } -static const char * const reg_file[4] = { - [0] = "A", - [1] = "g", - [2] = "m", - [3] = "imm", -}; + for (i = 0; i < count; i++) { + struct disasm_src_operand *src = (i == 0) ? &inst->src0 : &inst->src1; + const uint32_t dw = (i == 0) ? dw2 : dw3; + + src->base.addr_mode = READ(dw, GEN6_INST_SRC_ADDRMODE); + + if (src->base.addr_mode == GEN6_ADDRMODE_DIRECT) { + src->base.reg = READ(dw, GEN6_INST_SRC_REG); + + if (inst->access_mode == GEN6_ALIGN_1) { + src->base.subreg = READ(dw, GEN6_INST_SRC_SUBREG); + } else { + src->base.subreg = READ(dw, GEN6_INST_SRC_SUBREG_ALIGN16) << + GEN6_INST_SRC_SUBREG_ALIGN16__SHR; + } + } else { + src->base.addr_subreg = READ(dw, GEN6_INST_SRC_ADDR_SUBREG); + + if (inst->access_mode == GEN6_ALIGN_1) { + src->base.addr_imm = READ(dw, GEN6_INST_SRC_ADDR_IMM); + } else { + src->base.addr_imm = READ(dw, GEN6_INST_SRC_ADDR_IMM_ALIGN16) << + GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR; + } + } -static const char * const writemask[16] = { - [0x0] = ".", - [0x1] = ".x", - [0x2] = ".y", - [0x3] = ".xy", - [0x4] = ".z", - [0x5] = ".xz", - [0x6] = ".yz", - [0x7] = ".xyz", - [0x8] = ".w", - [0x9] = ".xw", - [0xa] = ".yw", - [0xb] = ".xyw", - [0xc] = ".zw", - [0xd] = ".xzw", - [0xe] = ".yzw", - [0xf] = "", -}; + src->vert_stride = READ(dw, GEN6_INST_SRC_VERTSTRIDE); -static const char * const end_of_thread[2] = { - [0] = "", - [1] = "EOT" -}; + if (inst->access_mode == GEN6_ALIGN_1) { + src->width = READ(dw, GEN6_INST_SRC_WIDTH); + src->horz_stride = READ(dw, GEN6_INST_SRC_HORZSTRIDE); -static const char * const target_function[16] = { - [BRW_SFID_NULL] = "null", - [BRW_SFID_MATH] = "math", - [BRW_SFID_SAMPLER] = "sampler", - [BRW_SFID_MESSAGE_GATEWAY] = "gateway", - [BRW_SFID_DATAPORT_READ] = "read", - [BRW_SFID_DATAPORT_WRITE] = "write", - [BRW_SFID_URB] = "urb", - [BRW_SFID_THREAD_SPAWNER] = "thread_spawner" -}; + src->swizzle_x = GEN6_SWIZZLE_X; + src->swizzle_y = GEN6_SWIZZLE_Y; + src->swizzle_z = GEN6_SWIZZLE_Z; + src->swizzle_w = GEN6_SWIZZLE_W; + } else { + src->width = GEN6_WIDTH_4; + src->horz_stride = GEN6_HORZSTRIDE_1; -static const char * const target_function_gen6[16] = { - [BRW_SFID_NULL] = "null", - [BRW_SFID_MATH] = "math", - [BRW_SFID_SAMPLER] = "sampler", - [BRW_SFID_MESSAGE_GATEWAY] = "gateway", - [BRW_SFID_URB] = "urb", - [BRW_SFID_THREAD_SPAWNER] = "thread_spawner", - [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler", - [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render", - [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const", - [GEN7_SFID_DATAPORT_DATA_CACHE] = "data" -}; + src->swizzle_x = READ(dw, GEN6_INST_SRC_SWIZZLE_X); + src->swizzle_y = READ(dw, GEN6_INST_SRC_SWIZZLE_Y); + src->swizzle_z = READ(dw, GEN6_INST_SRC_SWIZZLE_Z); + src->swizzle_w = READ(dw, GEN6_INST_SRC_SWIZZLE_W); + } -static const char * const dp_rc_msg_type_gen6[16] = { - [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read", - [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read", - [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read", - [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read", - [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read", - [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read", - [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write", - [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write", - [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write", - [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write", - [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write", - [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write", - [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write", - [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write", -}; + src->negate = (bool) (dw & GEN6_INST_SRC_NEGATE); + src->absolute = (bool) (dw & GEN6_INST_SRC_ABSOLUTE); + } +} -static const char * const math_function[16] = { - [BRW_MATH_FUNCTION_INV] = "inv", - [BRW_MATH_FUNCTION_LOG] = "log", - [BRW_MATH_FUNCTION_EXP] = "exp", - [BRW_MATH_FUNCTION_SQRT] = "sqrt", - [BRW_MATH_FUNCTION_RSQ] = "rsq", - [BRW_MATH_FUNCTION_SIN] = "sin", - [BRW_MATH_FUNCTION_COS] = "cos", - [BRW_MATH_FUNCTION_SINCOS] = "sincos", - [BRW_MATH_FUNCTION_FDIV] = "fdiv", - [BRW_MATH_FUNCTION_POW] = "pow", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv", - [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod", -}; +static void +disasm_inst_decode_3src_dw1_gen6(struct disasm_inst *inst, uint32_t dw1) +{ + static unsigned type_mapping[4] = { + [GEN7_TYPE_F_3SRC] = GEN6_TYPE_F, + [GEN7_TYPE_D_3SRC] = GEN6_TYPE_D, + [GEN7_TYPE_UD_3SRC] = GEN6_TYPE_UD, + [GEN7_TYPE_DF_3SRC] = GEN7_TYPE_DF, + }; + + inst->flag_subreg = READ(dw1, GEN6_3SRC_FLAG_SUBREG); + + if (inst->dev->gen >= ILO_GEN(7)) { + inst->nib_ctrl = (bool) (dw1 & GEN7_3SRC_NIBCTRL); + inst->flag_reg = READ(dw1, GEN7_3SRC_FLAG_REG); + + inst->dst.base.file = GEN6_FILE_GRF; + inst->dst.base.type = READ(dw1, GEN7_3SRC_DST_TYPE); + inst->dst.base.type = type_mapping[inst->dst.base.type]; + + inst->src0.base.type = READ(dw1, GEN7_3SRC_SRC_TYPE); + inst->src0.base.type = type_mapping[inst->src0.base.type]; + + inst->src1.base.type = inst->src0.base.type; + inst->u.src2.base.type = inst->src0.base.type; + } else { + inst->dst.base.file = (dw1 & GEN6_3SRC_DST_FILE_MRF) ? + GEN6_FILE_MRF: GEN6_FILE_GRF; + inst->dst.base.type = GEN6_TYPE_F; + + inst->src0.base.type = GEN6_TYPE_F; + inst->src1.base.type = GEN6_TYPE_F; + inst->u.src2.base.type = GEN6_TYPE_F; + } -static const char * const math_saturate[2] = { - [0] = "", - [1] = "sat" -}; + inst->dst.base.addr_mode = GEN6_ADDRMODE_DIRECT; + inst->dst.base.reg = READ(dw1, GEN6_3SRC_DST_REG); + inst->dst.base.subreg = READ(dw1, GEN6_3SRC_DST_SUBREG) << + GEN6_3SRC_DST_SUBREG__SHR; + + inst->dst.horz_stride = GEN6_HORZSTRIDE_1; + inst->dst.writemask = READ(dw1, GEN6_3SRC_DST_WRITEMASK); + + inst->src0.base.file = GEN6_FILE_GRF; + inst->src0.negate = (bool) (dw1 & GEN6_3SRC_SRC0_NEGATE); + inst->src0.absolute = (bool) (dw1 & GEN6_3SRC_SRC0_ABSOLUTE); + inst->src1.base.file = GEN6_FILE_GRF; + inst->src1.negate = (bool) (dw1 & GEN6_3SRC_SRC1_NEGATE); + inst->src1.absolute = (bool) (dw1 & GEN6_3SRC_SRC1_ABSOLUTE); + inst->u.src2.base.file = GEN6_FILE_GRF; + inst->u.src2.negate = (bool) (dw1 & GEN6_3SRC_SRC2_NEGATE); + inst->u.src2.absolute = (bool) (dw1 & GEN6_3SRC_SRC2_ABSOLUTE); +} -static const char * const math_signed[2] = { - [0] = "", - [1] = "signed" -}; +static void +disasm_inst_decode_3src_dw2_dw3_gen6(struct disasm_inst *inst, + uint32_t dw2, uint32_t dw3) +{ + const uint64_t qw = (uint64_t) dw3 << 32 | dw2; + int i; -static const char * const math_scalar[2] = { - [0] = "", - [1] = "scalar" -}; + for (i = 0; i < 3; i++) { + struct disasm_src_operand *src = (i == 0) ? &inst->src0 : + (i == 1) ? &inst->src1 : + &inst->u.src2; + const uint32_t dw = (i == 0) ? READ(qw, GEN6_3SRC_SRC_0) : + (i == 1) ? READ(qw, GEN6_3SRC_SRC_1) : + READ(qw, GEN6_3SRC_SRC_2); + + src->base.addr_mode = GEN6_ADDRMODE_DIRECT; + src->base.reg = READ(dw, GEN6_3SRC_SRC_REG); + src->base.subreg = READ(dw, GEN6_3SRC_SRC_SUBREG) << + GEN6_3SRC_SRC_SUBREG__SHR; + + if (dw & GEN6_3SRC_SRC_REPCTRL) { + src->vert_stride = GEN6_VERTSTRIDE_0; + src->width = GEN6_WIDTH_1; + src->horz_stride = GEN6_HORZSTRIDE_0; + } else { + src->vert_stride = GEN6_VERTSTRIDE_4; + src->width = GEN6_WIDTH_4; + src->horz_stride = GEN6_HORZSTRIDE_1; + } -static const char * const math_precision[2] = { - [0] = "", - [1] = "partial_precision" -}; + src->swizzle_x = READ(dw, GEN6_3SRC_SRC_SWIZZLE_X); + src->swizzle_y = READ(dw, GEN6_3SRC_SRC_SWIZZLE_Y); + src->swizzle_z = READ(dw, GEN6_3SRC_SRC_SWIZZLE_Z); + src->swizzle_w = READ(dw, GEN6_3SRC_SRC_SWIZZLE_W); + } +} -static const char * const urb_opcode[2] = { - [0] = "urb_write", - [1] = "ff_sync", -}; +/* + * When GEN6_INST_CMPTCTRL of DW0 is set, the instruction has 64 bits and is + * in EU_INSTRUCTION_COMPACT_TWO_SRC form. We should have expanded it to its + * original form. + * + * Depending on the opcode, the 128-bits instruction is in one of the + * following forms + * + * - EU_INSTRUCTION_BASIC_ONE_SRC + * - EU_INSTRUCTION_BASIC_TWO_SRC + * - EU_INSTRUCTION_BASIC_THREE_SRC + * - EU_INSTRUCTION_BRANCH_CONDITIONAL + * - EU_INSTRUCTION_BRANCH_ONE_SRC + * - EU_INSTRUCTION_BRANCH_TWO_SRC + * - EU_INSTRUCTION_ILLEGAL + * - EU_INSTRUCTION_MATH + * - EU_INSTRUCTION_NOP + * - EU_INSTRUCTION_SEND + * + * In EU_INSTRUCTION_BASIC_ONE_SRC form, + * + * - DW0 is EU_INSTRUCTION_HEADER + * - DW1 is EU_INSTRUCTION_OPERAND_CONTROLS + * - DW2 is Source 0 and EU_INSTRUCTION_FLAGS + * - DW3 is reserved unless Source 0 is an immediate + * + * All other forms except EU_INSTRUCTION_BASIC_THREE_SRC are quite compatible + * with EU_INSTRUCTION_BASIC_ONE_SRC. + */ +static void +disasm_inst_decode(struct disasm_inst *inst, + const uint32_t *dw) +{ + assert(!(dw[0] & GEN6_INST_CMPTCTRL)); + + disasm_inst_decode_dw0_gen6(inst, dw[0]); + + switch (inst->opcode) { + case GEN7_OPCODE_CSEL: + case GEN7_OPCODE_BFE: + case GEN7_OPCODE_BFI2: + case GEN6_OPCODE_MAD: + case GEN6_OPCODE_LRP: + disasm_inst_decode_3src_dw1_gen6(inst, dw[1]); + disasm_inst_decode_3src_dw2_dw3_gen6(inst, dw[2], dw[3]); + break; + default: + disasm_inst_decode_dw1_gen6(inst, dw[1]); + disasm_inst_decode_dw2_dw3_gen6(inst, dw[2], dw[3]); + break; + } +} -static const char * const urb_swizzle[4] = { - [BRW_URB_SWIZZLE_NONE] = "", - [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave", - [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose", -}; +static const char * +disasm_inst_opcode(const struct disasm_inst *inst) +{ + return (disasm_opcode_table[inst->opcode].name) ? + disasm_opcode_table[inst->opcode].name : "BAD"; +} -static const char * const urb_allocate[2] = { - [0] = "", - [1] = "allocate" -}; +static const char * +disasm_inst_pred_ctrl(const struct disasm_inst *inst) +{ + if (inst->access_mode == GEN6_ALIGN_1) { + switch (inst->pred_ctrl) { + case GEN6_PREDCTRL_NORMAL: return ""; + case GEN6_PREDCTRL_ANYV: return ".anyv"; + case GEN6_PREDCTRL_ALLV: return ".allv"; + case GEN6_PREDCTRL_ANY2H: return ".any2h"; + case GEN6_PREDCTRL_ALL2H: return ".all2h"; + case GEN6_PREDCTRL_ANY4H: return ".any4h"; + case GEN6_PREDCTRL_ALL4H: return ".all4h"; + case GEN6_PREDCTRL_ANY8H: return ".any8h"; + case GEN6_PREDCTRL_ALL8H: return ".all8h"; + case GEN6_PREDCTRL_ANY16H: return ".any16h"; + case GEN6_PREDCTRL_ALL16H: return ".all16h"; + case GEN7_PREDCTRL_ANY32H: return ".any32h"; + case GEN7_PREDCTRL_ALL32H: return ".all32h"; + default: return ".BAD"; + } + } else { + switch (inst->pred_ctrl) { + case GEN6_PREDCTRL_NORMAL: return ""; + case GEN6_PREDCTRL_X: return ".x"; + case GEN6_PREDCTRL_Y: return ".y"; + case GEN6_PREDCTRL_Z: return ".z"; + case GEN6_PREDCTRL_W: return ".w"; + default: return ".BAD"; + } + } +} -static const char * const urb_used[2] = { - [0] = "", - [1] = "used" -}; +static char +disasm_inst_pred_inv(const struct disasm_inst *inst) +{ + return (inst->pred_inv) ? '-' : '+'; +} -static const char * const urb_complete[2] = { - [0] = "", - [1] = "complete" -}; +static const char * +disasm_inst_exec_size(const struct disasm_inst *inst) +{ + switch (inst->exec_size) { + case GEN6_EXECSIZE_1: return "1"; + case GEN6_EXECSIZE_2: return "2"; + case GEN6_EXECSIZE_4: return "4"; + case GEN6_EXECSIZE_8: return "8"; + case GEN6_EXECSIZE_16: return "16"; + case GEN6_EXECSIZE_32: return "32"; + default: return "BAD"; + } +} -static const char * const sampler_target_format[4] = { - [0] = "F", - [2] = "UD", - [3] = "D" -}; +static const char * +disasm_inst_fc(const struct disasm_inst *inst) +{ + assert(inst->opcode == GEN6_OPCODE_MATH); + + switch (inst->fc) { + case GEN6_MATH_INV: return "inv"; + case GEN6_MATH_LOG: return "log"; + case GEN6_MATH_EXP: return "exp"; + case GEN6_MATH_SQRT: return "sqrt"; + case GEN6_MATH_RSQ: return "rsq"; + case GEN6_MATH_SIN: return "sin"; + case GEN6_MATH_COS: return "cos"; + case GEN6_MATH_FDIV: return "fdiv"; + case GEN6_MATH_POW: return "pow"; + case GEN6_MATH_INT_DIV: return "int_div"; + case GEN6_MATH_INT_DIV_QUOTIENT: return "int_div_quotient"; + case GEN6_MATH_INT_DIV_REMAINDER: return "int_div_remainder"; + default: return "BAD"; + } +} +static const char * +disasm_inst_sfid(const struct disasm_inst *inst) +{ + assert(inst->opcode == GEN6_OPCODE_SEND || + inst->opcode == GEN6_OPCODE_SENDC); + + switch (inst->sfid) { + case GEN6_SFID_NULL: return "null"; + case GEN6_SFID_SAMPLER: return "sampler"; + case GEN6_SFID_GATEWAY: return "gateway"; + case GEN6_SFID_DP_SAMPLER: return "dp sampler"; + case GEN6_SFID_DP_RC: return "dp render"; + case GEN6_SFID_URB: return "urb"; + case GEN6_SFID_SPAWNER: return "spawner"; + case GEN6_SFID_VME: return "vme"; + case GEN6_SFID_DP_CC: return "dp const"; + case GEN7_SFID_DP_DC0: return "dp data 0"; + case GEN7_SFID_PI: return "pixel interp"; + case GEN75_SFID_DP_DC1: return "dp data 1"; + default: return "BAD"; + } +} -static int column; +static const char * +disasm_inst_cond_modifier(const struct disasm_inst *inst) +{ + switch (inst->cond_modifier) { + case GEN6_COND_NONE: return ""; + case GEN6_COND_Z: return ".z"; + case GEN6_COND_NZ: return ".nz"; + case GEN6_COND_G: return ".g"; + case GEN6_COND_GE: return ".ge"; + case GEN6_COND_L: return ".l"; + case GEN6_COND_LE: return ".le"; + case GEN6_COND_O: return ".o"; + case GEN6_COND_U: return ".u"; + default: return ".BAD"; + } +} -static int string (FILE *file, const char *string) +static const char * +disasm_inst_debug_ctrl(const struct disasm_inst *inst) { - fputs (string, file); - column += strlen (string); - return 0; + return (inst->debug_ctrl) ? ".breakpoint" : ""; } -static int format (FILE *f, const char *format, ...) +static const char * +disasm_inst_saturate(const struct disasm_inst *inst) { - char buf[1024]; - va_list args; - va_start (args, format); - - vsnprintf (buf, sizeof (buf) - 1, format, args); - va_end (args); - string (f, buf); - return 0; + return (inst->saturate) ? ".sat" : ""; } -static int newline (FILE *f) +static const char * +disasm_inst_flag_reg(const struct disasm_inst *inst) { - putc ('\n', f); - column = 0; - return 0; + static const char *flag_names[2][2] = { + { "f0", "f0.1" }, + { "f1.0", "f1.1" }, + }; + + return (inst->flag_reg <= 1 && inst->flag_subreg <= 1) ? + flag_names[inst->flag_reg][inst->flag_subreg] : "fBAD"; } -static int pad (FILE *f, int c) +static const char * +disasm_inst_access_mode(const struct disasm_inst *inst) { - do - string (f, " "); - while (column < c); - return 0; + switch (inst->access_mode) { + case GEN6_ALIGN_1: return " align1"; + case GEN6_ALIGN_16: return " align16"; + default: return " alignBAD"; + } } -static int control (FILE *file, const char *name, const char * const ctrl[], - GLuint id, int *space) +static const char * +disasm_inst_mask_ctrl(const struct disasm_inst *inst) { - if (!ctrl[id]) { - fprintf (file, "*** invalid %s value %d ", - name, id); - return 1; - } - if (ctrl[id][0]) - { - if (space && *space) - string (file, " "); - string (file, ctrl[id]); - if (space) - *space = 1; - } - return 0; + switch (inst->mask_ctrl) { + case GEN6_MASKCTRL_NORMAL: return ""; + case GEN6_MASKCTRL_NOMASK: return " WE_all"; + default: return " WE_BAD"; + } } -static int print_opcode (FILE *file, int id) +static const char * +disasm_inst_dep_ctrl(const struct disasm_inst *inst) { - if (!opcode[id].name) { - format (file, "*** invalid opcode value %d ", id); - return 1; - } - string (file, opcode[id].name); - return 0; + switch (inst->dep_ctrl) { + case GEN6_DEPCTRL_NORMAL: return ""; + case GEN6_DEPCTRL_NODDCLR: return " NoDDClr"; + case GEN6_DEPCTRL_NODDCHK: return " NoDDChk"; + case GEN6_DEPCTRL_NEITHER: return " NoDDClr,NoDDChk"; + default: return " NoDDBAD"; + } } -static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr) +static const char * +disasm_inst_qtr_ctrl(const struct disasm_inst *inst) { - int err = 0; - - /* Clear the Compr4 instruction compression bit. */ - if (_reg_file == BRW_MESSAGE_REGISTER_FILE) - _reg_nr &= ~(1 << 7); - - if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { - switch (_reg_nr & 0xf0) { - case BRW_ARF_NULL: - string (file, "null"); - return -1; - case BRW_ARF_ADDRESS: - format (file, "a%d", _reg_nr & 0x0f); - break; - case BRW_ARF_ACCUMULATOR: - format (file, "acc%d", _reg_nr & 0x0f); - break; - case BRW_ARF_FLAG: - format (file, "f%d", _reg_nr & 0x0f); - break; - case BRW_ARF_MASK: - format (file, "mask%d", _reg_nr & 0x0f); - break; - case BRW_ARF_MASK_STACK: - format (file, "msd%d", _reg_nr & 0x0f); - break; - case BRW_ARF_STATE: - format (file, "sr%d", _reg_nr & 0x0f); - break; - case BRW_ARF_CONTROL: - format (file, "cr%d", _reg_nr & 0x0f); - break; - case BRW_ARF_NOTIFICATION_COUNT: - format (file, "n%d", _reg_nr & 0x0f); - break; - case BRW_ARF_IP: - string (file, "ip"); - return -1; - break; - default: - format (file, "ARF%d", _reg_nr); - break; - } - } else { - err |= control (file, "src reg file", reg_file, _reg_file, NULL); - format (file, "%d", _reg_nr); - } - return err; + switch (inst->exec_size) { + case GEN6_EXECSIZE_8: + switch (inst->qtr_ctrl) { + case GEN6_QTRCTRL_1Q: return " 1Q"; + case GEN6_QTRCTRL_2Q: return " 2Q"; + case GEN6_QTRCTRL_3Q: return " 3Q"; + case GEN6_QTRCTRL_4Q: return " 4Q"; + default: return " BADQ"; + } + break; + case GEN6_EXECSIZE_16: + switch (inst->qtr_ctrl) { + case GEN6_QTRCTRL_1H: return " 1H"; + case GEN6_QTRCTRL_2H: return " 2H"; + default: return " BADH"; + } + break; + default: + return ""; + } + } -static int dest (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_thread_ctrl(const struct disasm_inst *inst) { - int err = 0; - - if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT) - { - err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr); - if (err == -1) - return 0; - if (inst->bits1.da1.dest_subreg_nr) - format (file, ".%d", inst->bits1.da1.dest_subreg_nr / - reg_type_size[inst->bits1.da1.dest_reg_type]); - string (file, "<"); - err |= control (file, "horiz stride", horiz_stride, inst->bits1.da1.dest_horiz_stride, NULL); - string (file, ">"); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL); - } - else - { - string (file, "g[a0"); - if (inst->bits1.ia1.dest_subreg_nr) - format (file, ".%d", inst->bits1.ia1.dest_subreg_nr / - reg_type_size[inst->bits1.ia1.dest_reg_type]); - if (inst->bits1.ia1.dest_indirect_offset) - format (file, " %d", inst->bits1.ia1.dest_indirect_offset); - string (file, "]<"); - err |= control (file, "horiz stride", horiz_stride, inst->bits1.ia1.dest_horiz_stride, NULL); - string (file, ">"); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL); - } - } - else - { - if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) - { - err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr); - if (err == -1) - return 0; - if (inst->bits1.da16.dest_subreg_nr) - format (file, ".%d", inst->bits1.da16.dest_subreg_nr / - reg_type_size[inst->bits1.da16.dest_reg_type]); - string (file, "<1>"); - err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL); - } - else - { - err = 1; - string (file, "Indirect align16 address mode not supported"); - } - } - - return 0; + switch (inst->thread_ctrl) { + case GEN6_THREADCTRL_NORMAL: return ""; + case GEN6_THREADCTRL_ATOMIC: return " atomic"; + case GEN6_THREADCTRL_SWITCH: return " switch"; + default: return " BAD"; + } } -static int dest_3src (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_acc_wr_ctrl(const struct disasm_inst *inst) { - int err = 0; - uint32_t reg_file; - - if (inst->bits1.da3src.dest_reg_file) - reg_file = BRW_MESSAGE_REGISTER_FILE; - else - reg_file = BRW_GENERAL_REGISTER_FILE; - - err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr); - if (err == -1) - return 0; - if (inst->bits1.da3src.dest_subreg_nr) - format (file, ".%d", inst->bits1.da3src.dest_subreg_nr); - string (file, "<1>"); - err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL); - err |= control (file, "dest reg encoding", reg_encoding, BRW_REGISTER_TYPE_F, NULL); - - return 0; + return (inst->acc_wr_ctrl) ? " AccWrEnable" : ""; } -static int src_align1_region (FILE *file, - GLuint _vert_stride, GLuint _width, GLuint _horiz_stride) +static const char * +disasm_inst_cmpt_ctrl(const struct disasm_inst *inst) { - int err = 0; - string (file, "<"); - err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); - string (file, ","); - err |= control (file, "width", width, _width, NULL); - string (file, ","); - err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL); - string (file, ">"); - return err; + return (inst->cmpt_ctrl) ? " compacted" : ""; } -static int src_da1 (FILE *file, GLuint type, GLuint _reg_file, - GLuint _vert_stride, GLuint _width, GLuint _horiz_stride, - GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate) +static const char * +disasm_inst_eot(const struct disasm_inst *inst) { - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - err |= reg (file, _reg_file, reg_num); - if (err == -1) - return 0; - if (sub_reg_num) - format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */ - src_align1_region (file, _vert_stride, _width, _horiz_stride); - err |= control (file, "src reg encoding", reg_encoding, type, NULL); - return err; + if (inst->opcode == GEN6_OPCODE_SEND || + inst->opcode == GEN6_OPCODE_SENDC) + return (inst->u.imm32 & GEN6_MSG_EOT) ? " EOT" : ""; + else + return ""; } -static int src_ia1 (FILE *file, - GLuint type, - GLuint _reg_file, - GLint _addr_imm, - GLuint _addr_subreg_nr, - GLuint _negate, - GLuint __abs, - GLuint _addr_mode, - GLuint _horiz_stride, - GLuint _width, - GLuint _vert_stride) +static const char * +disasm_inst_file(const struct disasm_inst *inst, + const struct disasm_operand *operand, + bool *multi_regs) { - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - string (file, "g[a0"); - if (_addr_subreg_nr) - format (file, ".%d", _addr_subreg_nr); - if (_addr_imm) - format (file, " %d", _addr_imm); - string (file, "]"); - src_align1_region (file, _vert_stride, _width, _horiz_stride); - err |= control (file, "src reg encoding", reg_encoding, type, NULL); - return err; + switch (operand->file) { + case GEN6_FILE_ARF: + switch (operand->reg & 0xf0) { + case GEN6_ARF_NULL: *multi_regs = false; return "null"; + case GEN6_ARF_A0: *multi_regs = true; return "a"; + case GEN6_ARF_ACC0: *multi_regs = true; return "acc"; + case GEN6_ARF_F0: *multi_regs = true; return "f"; + case GEN6_ARF_SR0: *multi_regs = true; return "sr"; + case GEN6_ARF_CR0: *multi_regs = true; return "cr"; + case GEN6_ARF_N0: *multi_regs = true; return "n"; + case GEN6_ARF_IP: *multi_regs = false; return "ip"; + case GEN6_ARF_TDR: *multi_regs = false; return "tdr"; + case GEN7_ARF_TM0: *multi_regs = true; return "tm"; + default: *multi_regs = false; return "BAD"; + } + break; + case GEN6_FILE_GRF: *multi_regs = true; return "g"; + case GEN6_FILE_MRF: *multi_regs = true; return "m"; + case GEN6_FILE_IMM: *multi_regs = true; return ""; + default: *multi_regs = false; return "BAD"; + } } -static int src_da16 (FILE *file, - GLuint _reg_type, - GLuint _reg_file, - GLuint _vert_stride, - GLuint _reg_nr, - GLuint _subreg_nr, - GLuint __abs, - GLuint _negate, - GLuint swz_x, - GLuint swz_y, - GLuint swz_z, - GLuint swz_w) +static const char * +disasm_inst_type(const struct disasm_inst *inst, + const struct disasm_operand *operand) { - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - err |= reg (file, _reg_file, _reg_nr); - if (err == -1) - return 0; - if (_subreg_nr) - /* bit4 for subreg number byte addressing. Make this same meaning as - in da1 case, so output looks consistent. */ - format (file, ".%d", 16 / reg_type_size[_reg_type]); - string (file, "<"); - err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); - string (file, ",4,1>"); - /* - * Three kinds of swizzle display: - * identity - nothing printed - * 1->all - print the single channel - * 1->1 - print the mapping - */ - if (swz_x == BRW_CHANNEL_X && - swz_y == BRW_CHANNEL_Y && - swz_z == BRW_CHANNEL_Z && - swz_w == BRW_CHANNEL_W) - { - ; - } - else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - } - else - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - err |= control (file, "channel select", chan_sel, swz_y, NULL); - err |= control (file, "channel select", chan_sel, swz_z, NULL); - err |= control (file, "channel select", chan_sel, swz_w, NULL); - } - err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL); - return err; + if (operand->file == GEN6_FILE_IMM) { + switch (operand->type) { + case GEN6_TYPE_UD: return "UD"; + case GEN6_TYPE_D: return "D"; + case GEN6_TYPE_UW: return "UW"; + case GEN6_TYPE_W: return "W"; + case GEN6_TYPE_UV_IMM: return "UV"; + case GEN6_TYPE_VF_IMM: return "VF"; + case GEN6_TYPE_V_IMM: return "V"; + case GEN6_TYPE_F: return "F"; + default: return "BAD"; + } + } else { + switch (operand->type) { + case GEN6_TYPE_UD: return "UD"; + case GEN6_TYPE_D: return "D"; + case GEN6_TYPE_UW: return "UW"; + case GEN6_TYPE_W: return "W"; + case GEN6_TYPE_UB: return "UB"; + case GEN6_TYPE_B: return "B"; + case GEN7_TYPE_DF: return "DF"; + case GEN6_TYPE_F: return "F"; + default: return "BAD"; + } + } } -static int src0_3src (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_vert_stride(const struct disasm_inst *inst, unsigned vert_stride) { - int err = 0; - GLuint swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3; - GLuint swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3; - GLuint swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3; - GLuint swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3; - - err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL); - err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL); - - err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr); - if (err == -1) - return 0; - if (inst->bits2.da3src.src0_subreg_nr) - format (file, ".%d", inst->bits2.da3src.src0_subreg_nr); - string (file, "<4,1,1>"); - err |= control (file, "src da16 reg type", reg_encoding, - BRW_REGISTER_TYPE_F, NULL); - /* - * Three kinds of swizzle display: - * identity - nothing printed - * 1->all - print the single channel - * 1->1 - print the mapping - */ - if (swz_x == BRW_CHANNEL_X && - swz_y == BRW_CHANNEL_Y && - swz_z == BRW_CHANNEL_Z && - swz_w == BRW_CHANNEL_W) - { - ; - } - else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - } - else - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - err |= control (file, "channel select", chan_sel, swz_y, NULL); - err |= control (file, "channel select", chan_sel, swz_z, NULL); - err |= control (file, "channel select", chan_sel, swz_w, NULL); - } - return err; + switch (vert_stride) { + case GEN6_VERTSTRIDE_0: return "0"; + case GEN6_VERTSTRIDE_1: return "1"; + case GEN6_VERTSTRIDE_2: return "2"; + case GEN6_VERTSTRIDE_4: return "4"; + case GEN6_VERTSTRIDE_8: return "8"; + case GEN6_VERTSTRIDE_16: return "16"; + case GEN6_VERTSTRIDE_32: return "32"; + case GEN6_VERTSTRIDE_VXH: return "VxH"; + default: return "BAD"; + } } -static int src1_3src (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_width(const struct disasm_inst *inst, unsigned width) { - int err = 0; - GLuint swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3; - GLuint swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3; - GLuint swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3; - GLuint swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3; - GLuint src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low | - (inst->bits3.da3src.src1_subreg_nr_high << 2)); - - err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate, - NULL); - err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL); - - err |= reg (file, BRW_GENERAL_REGISTER_FILE, - inst->bits3.da3src.src1_reg_nr); - if (err == -1) - return 0; - if (src1_subreg_nr) - format (file, ".%d", src1_subreg_nr); - string (file, "<4,1,1>"); - err |= control (file, "src da16 reg type", reg_encoding, - BRW_REGISTER_TYPE_F, NULL); - /* - * Three kinds of swizzle display: - * identity - nothing printed - * 1->all - print the single channel - * 1->1 - print the mapping - */ - if (swz_x == BRW_CHANNEL_X && - swz_y == BRW_CHANNEL_Y && - swz_z == BRW_CHANNEL_Z && - swz_w == BRW_CHANNEL_W) - { - ; - } - else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - } - else - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - err |= control (file, "channel select", chan_sel, swz_y, NULL); - err |= control (file, "channel select", chan_sel, swz_z, NULL); - err |= control (file, "channel select", chan_sel, swz_w, NULL); - } - return err; + switch (width) { + case GEN6_WIDTH_1: return "1"; + case GEN6_WIDTH_2: return "2"; + case GEN6_WIDTH_4: return "4"; + case GEN6_WIDTH_8: return "8"; + case GEN6_WIDTH_16: return "16"; + default: return "BAD"; + } } +static const char * +disasm_inst_horz_stride(const struct disasm_inst *inst, unsigned horz_stride) +{ + switch (horz_stride) { + case GEN6_HORZSTRIDE_0: return "0"; + case GEN6_HORZSTRIDE_1: return "1"; + case GEN6_HORZSTRIDE_2: return "2"; + case GEN6_HORZSTRIDE_4: return "4"; + default: return "BAD"; + } +} -static int src2_3src (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_writemask(const struct disasm_inst *inst, unsigned writemask) { - int err = 0; - GLuint swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3; - GLuint swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3; - GLuint swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3; - GLuint swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3; - - err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate, - NULL); - err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL); - - err |= reg (file, BRW_GENERAL_REGISTER_FILE, - inst->bits3.da3src.src2_reg_nr); - if (err == -1) - return 0; - if (inst->bits3.da3src.src2_subreg_nr) - format (file, ".%d", inst->bits3.da3src.src2_subreg_nr); - string (file, "<4,1,1>"); - err |= control (file, "src da16 reg type", reg_encoding, - BRW_REGISTER_TYPE_F, NULL); - /* - * Three kinds of swizzle display: - * identity - nothing printed - * 1->all - print the single channel - * 1->1 - print the mapping - */ - if (swz_x == BRW_CHANNEL_X && - swz_y == BRW_CHANNEL_Y && - swz_z == BRW_CHANNEL_Z && - swz_w == BRW_CHANNEL_W) - { - ; - } - else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - } - else - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - err |= control (file, "channel select", chan_sel, swz_y, NULL); - err |= control (file, "channel select", chan_sel, swz_z, NULL); - err |= control (file, "channel select", chan_sel, swz_w, NULL); - } - return err; + switch (writemask) { + case 0x0: return "."; + case 0x1: return ".x"; + case 0x2: return ".y"; + case 0x3: return ".xy"; + case 0x4: return ".z"; + case 0x5: return ".xz"; + case 0x6: return ".yz"; + case 0x7: return ".xyz"; + case 0x8: return ".w"; + case 0x9: return ".xw"; + case 0xa: return ".yw"; + case 0xb: return ".xyw"; + case 0xc: return ".zw"; + case 0xd: return ".xzw"; + case 0xe: return ".yzw"; + case 0xf: return ""; + default: return ".BAD"; + } } -static int imm (FILE *file, GLuint type, struct brw_instruction *inst) { - switch (type) { - case BRW_REGISTER_TYPE_UD: - format (file, "0x%08xUD", inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_D: - format (file, "%dD", inst->bits3.d); - break; - case BRW_REGISTER_TYPE_UW: - format (file, "0x%04xUW", (uint16_t) inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_W: - format (file, "%dW", (int16_t) inst->bits3.d); - break; - case BRW_REGISTER_TYPE_UB: - format (file, "0x%02xUB", (int8_t) inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_VF: - format (file, "Vector Float"); - break; - case BRW_REGISTER_TYPE_V: - format (file, "0x%08xV", inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_F: - format (file, "%-gF", inst->bits3.f); - } - return 0; +static const char * +disasm_inst_negate(const struct disasm_inst *inst, bool negate) +{ + return (negate) ? "-" : ""; } -static int src0 (FILE *file, struct brw_instruction *inst) +static const char * +disasm_inst_absolute(const struct disasm_inst *inst, bool absolute) { - if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) - return imm (file, inst->bits1.da1.src0_reg_type, - inst); - else if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da1 (file, - inst->bits1.da1.src0_reg_type, - inst->bits1.da1.src0_reg_file, - inst->bits2.da1.src0_vert_stride, - inst->bits2.da1.src0_width, - inst->bits2.da1.src0_horiz_stride, - inst->bits2.da1.src0_reg_nr, - inst->bits2.da1.src0_subreg_nr, - inst->bits2.da1.src0_abs, - inst->bits2.da1.src0_negate); - } - else - { - return src_ia1 (file, - inst->bits1.ia1.src0_reg_type, - inst->bits1.ia1.src0_reg_file, - inst->bits2.ia1.src0_indirect_offset, - inst->bits2.ia1.src0_subreg_nr, - inst->bits2.ia1.src0_negate, - inst->bits2.ia1.src0_abs, - inst->bits2.ia1.src0_address_mode, - inst->bits2.ia1.src0_horiz_stride, - inst->bits2.ia1.src0_width, - inst->bits2.ia1.src0_vert_stride); - } - } - else - { - if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da16 (file, - inst->bits1.da16.src0_reg_type, - inst->bits1.da16.src0_reg_file, - inst->bits2.da16.src0_vert_stride, - inst->bits2.da16.src0_reg_nr, - inst->bits2.da16.src0_subreg_nr, - inst->bits2.da16.src0_abs, - inst->bits2.da16.src0_negate, - inst->bits2.da16.src0_swz_x, - inst->bits2.da16.src0_swz_y, - inst->bits2.da16.src0_swz_z, - inst->bits2.da16.src0_swz_w); - } - else - { - string (file, "Indirect align16 address mode not supported"); - return 1; - } - } + return (absolute) ? "(abs)" : ""; } -static int src1 (FILE *file, struct brw_instruction *inst) +static bool +disasm_inst_is_null(const struct disasm_inst *inst, + const struct disasm_operand *operand) { - if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE) - return imm (file, inst->bits1.da1.src1_reg_type, - inst); - else if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da1 (file, - inst->bits1.da1.src1_reg_type, - inst->bits1.da1.src1_reg_file, - inst->bits3.da1.src1_vert_stride, - inst->bits3.da1.src1_width, - inst->bits3.da1.src1_horiz_stride, - inst->bits3.da1.src1_reg_nr, - inst->bits3.da1.src1_subreg_nr, - inst->bits3.da1.src1_abs, - inst->bits3.da1.src1_negate); - } - else - { - return src_ia1 (file, - inst->bits1.ia1.src1_reg_type, - inst->bits1.ia1.src1_reg_file, - inst->bits3.ia1.src1_indirect_offset, - inst->bits3.ia1.src1_subreg_nr, - inst->bits3.ia1.src1_negate, - inst->bits3.ia1.src1_abs, - inst->bits3.ia1.src1_address_mode, - inst->bits3.ia1.src1_horiz_stride, - inst->bits3.ia1.src1_width, - inst->bits3.ia1.src1_vert_stride); - } - } - else - { - if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da16 (file, - inst->bits1.da16.src1_reg_type, - inst->bits1.da16.src1_reg_file, - inst->bits3.da16.src1_vert_stride, - inst->bits3.da16.src1_reg_nr, - inst->bits3.da16.src1_subreg_nr, - inst->bits3.da16.src1_abs, - inst->bits3.da16.src1_negate, - inst->bits3.da16.src1_swz_x, - inst->bits3.da16.src1_swz_y, - inst->bits3.da16.src1_swz_z, - inst->bits3.da16.src1_swz_w); - } - else - { - string (file, "Indirect align16 address mode not supported"); - return 1; - } - } + return (operand->file == GEN6_FILE_ARF && operand->reg == GEN6_ARF_NULL); } -int esize[6] = { - [0] = 1, - [1] = 2, - [2] = 4, - [3] = 8, - [4] = 16, - [5] = 32, -}; +static int +disasm_inst_type_size(const struct disasm_inst *inst, + const struct disasm_operand *operand) +{ + assert(operand->file != GEN6_FILE_IMM); + + switch (operand->type) { + case GEN6_TYPE_UD: return 4; + case GEN6_TYPE_D: return 4; + case GEN6_TYPE_UW: return 2; + case GEN6_TYPE_W: return 2; + case GEN6_TYPE_UB: return 1; + case GEN6_TYPE_B: return 1; + case GEN7_TYPE_DF: return 8; + case GEN6_TYPE_F: return 4; + default: return 1; + } +} -static int qtr_ctrl(FILE *file, struct brw_instruction *inst) +static void +disasm_printer_reset(struct disasm_printer *printer) { - int qtr_ctl = inst->header.compression_control; - int exec_size = esize[inst->header.execution_size]; - - if (exec_size == 8) { - switch (qtr_ctl) { - case 0: - string (file, " 1Q"); - break; - case 1: - string (file, " 2Q"); - break; - case 2: - string (file, " 3Q"); - break; - case 3: - string (file, " 4Q"); - break; - } - } else if (exec_size == 16){ - if (qtr_ctl < 2) - string (file, " 1H"); - else - string (file, " 2H"); - } - return 0; + printer->buf[0] = '\0'; + printer->len = 0; } -int brw_disasm (FILE *file, struct brw_instruction *inst, int gen) +static const char * +disasm_printer_get_string(struct disasm_printer *printer) { - int err = 0; - int space = 0; - - if (inst->header.predicate_control) { - string (file, "("); - err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); - format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0); - if (inst->bits2.da1.flag_subreg_nr) - format (file, ".%d", inst->bits2.da1.flag_subreg_nr); - if (inst->header.access_mode == BRW_ALIGN_1) - err |= control (file, "predicate control align1", pred_ctrl_align1, - inst->header.predicate_control, NULL); - else - err |= control (file, "predicate control align16", pred_ctrl_align16, - inst->header.predicate_control, NULL); - string (file, ") "); - } - - err |= print_opcode (file, inst->header.opcode); - err |= control (file, "saturate", saturate, inst->header.saturate, NULL); - err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL); - - if (inst->header.opcode == BRW_OPCODE_MATH) { - string (file, " "); - err |= control (file, "function", math_function, - inst->header.destreg__conditionalmod, NULL); - } else if (inst->header.opcode != BRW_OPCODE_SEND && - inst->header.opcode != BRW_OPCODE_SENDC) { - err |= control (file, "conditional modifier", conditional_modifier, - inst->header.destreg__conditionalmod, NULL); - - /* If we're using the conditional modifier, print which flags reg is - * used for it. Note that on gen6+, the embedded-condition SEL and - * control flow doesn't update flags. - */ - if (inst->header.destreg__conditionalmod && - (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL && - inst->header.opcode != BRW_OPCODE_IF && - inst->header.opcode != BRW_OPCODE_WHILE))) { - format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0); - if (inst->bits2.da1.flag_subreg_nr) - format (file, ".%d", inst->bits2.da1.flag_subreg_nr); - } - } - - if (inst->header.opcode != BRW_OPCODE_NOP) { - string (file, "("); - err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL); - string (file, ")"); - } - - if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6) - format (file, " %d", inst->header.destreg__conditionalmod); - - if (opcode[inst->header.opcode].nsrc == 3) { - pad (file, 16); - err |= dest_3src (file, inst); - - pad (file, 32); - err |= src0_3src (file, inst); - - pad (file, 48); - err |= src1_3src (file, inst); - - pad (file, 64); - err |= src2_3src (file, inst); - } else { - if (opcode[inst->header.opcode].ndst > 0) { - pad (file, 16); - err |= dest (file, inst); - } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE || - inst->header.opcode == BRW_OPCODE_ENDIF || - inst->header.opcode == BRW_OPCODE_WHILE)) { - format (file, " %d", inst->bits3.break_cont.jip); - } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF || - inst->header.opcode == BRW_OPCODE_ELSE || - inst->header.opcode == BRW_OPCODE_ENDIF || - inst->header.opcode == BRW_OPCODE_WHILE)) { - format (file, " %d", inst->bits1.branch_gen6.jump_count); - } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK || - inst->header.opcode == BRW_OPCODE_CONTINUE || - inst->header.opcode == BRW_OPCODE_HALT)) || - (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) { - format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip); - } else if (inst->header.opcode == BRW_OPCODE_JMPI) { - format (file, " %d", inst->bits3.d); - } - - if (opcode[inst->header.opcode].nsrc > 0) { - pad (file, 32); - err |= src0 (file, inst); - } - if (opcode[inst->header.opcode].nsrc > 1) { - pad (file, 48); - err |= src1 (file, inst); - } - } - - if (inst->header.opcode == BRW_OPCODE_SEND || - inst->header.opcode == BRW_OPCODE_SENDC) { - enum brw_message_target target; - - if (gen >= 6) - target = inst->header.destreg__conditionalmod; - else if (gen == 5) - target = inst->bits2.send_gen5.sfid; - else - target = inst->bits3.generic.msg_target; - - newline (file); - pad (file, 16); - space = 0; - - if (gen >= 6) { - err |= control (file, "target function", target_function_gen6, - target, &space); - } else { - err |= control (file, "target function", target_function, - target, &space); - } - - switch (target) { - case BRW_SFID_MATH: - err |= control (file, "math function", math_function, - inst->bits3.math.function, &space); - err |= control (file, "math saturate", math_saturate, - inst->bits3.math.saturate, &space); - err |= control (file, "math signed", math_signed, - inst->bits3.math.int_type, &space); - err |= control (file, "math scalar", math_scalar, - inst->bits3.math.data_type, &space); - err |= control (file, "math precision", math_precision, - inst->bits3.math.precision, &space); - break; - case BRW_SFID_SAMPLER: - if (gen >= 7) { - format (file, " (%d, %d, %d, %d)", - inst->bits3.sampler_gen7.binding_table_index, - inst->bits3.sampler_gen7.sampler, - inst->bits3.sampler_gen7.msg_type, - inst->bits3.sampler_gen7.simd_mode); - } else if (gen >= 5) { - format (file, " (%d, %d, %d, %d)", - inst->bits3.sampler_gen5.binding_table_index, - inst->bits3.sampler_gen5.sampler, - inst->bits3.sampler_gen5.msg_type, - inst->bits3.sampler_gen5.simd_mode); - } else if (0 /* FINISHME: is_g4x */) { - format (file, " (%d, %d)", - inst->bits3.sampler_g4x.binding_table_index, - inst->bits3.sampler_g4x.sampler); - } else { - format (file, " (%d, %d, ", - inst->bits3.sampler.binding_table_index, - inst->bits3.sampler.sampler); - err |= control (file, "sampler target format", - sampler_target_format, - inst->bits3.sampler.return_format, NULL); - string (file, ")"); - } - break; - case BRW_SFID_DATAPORT_READ: - if (gen >= 6) { - format (file, " (%d, %d, %d, %d)", - inst->bits3.gen6_dp.binding_table_index, - inst->bits3.gen6_dp.msg_control, - inst->bits3.gen6_dp.msg_type, - inst->bits3.gen6_dp.send_commit_msg); - } else if (gen >= 5 /* FINISHME: || is_g4x */) { - format (file, " (%d, %d, %d)", - inst->bits3.dp_read_gen5.binding_table_index, - inst->bits3.dp_read_gen5.msg_control, - inst->bits3.dp_read_gen5.msg_type); - } else { - format (file, " (%d, %d, %d)", - inst->bits3.dp_read.binding_table_index, - inst->bits3.dp_read.msg_control, - inst->bits3.dp_read.msg_type); - } - break; - - case BRW_SFID_DATAPORT_WRITE: - if (gen >= 7) { - format (file, " ("); - - err |= control (file, "DP rc message type", - dp_rc_msg_type_gen6, - inst->bits3.gen7_dp.msg_type, &space); - - format (file, ", %d, %d, %d)", - inst->bits3.gen7_dp.binding_table_index, - inst->bits3.gen7_dp.msg_control, - inst->bits3.gen7_dp.msg_type); - } else if (gen == 6) { - format (file, " ("); - - err |= control (file, "DP rc message type", - dp_rc_msg_type_gen6, - inst->bits3.gen6_dp.msg_type, &space); - - format (file, ", %d, %d, %d, %d)", - inst->bits3.gen6_dp.binding_table_index, - inst->bits3.gen6_dp.msg_control, - inst->bits3.gen6_dp.msg_type, - inst->bits3.gen6_dp.send_commit_msg); - } else { - format (file, " (%d, %d, %d, %d)", - inst->bits3.dp_write.binding_table_index, - (inst->bits3.dp_write.last_render_target << 3) | - inst->bits3.dp_write.msg_control, - inst->bits3.dp_write.msg_type, - inst->bits3.dp_write.send_commit_msg); - } - break; - - case BRW_SFID_URB: - if (gen >= 5) { - format (file, " %d", inst->bits3.urb_gen5.offset); - } else { - format (file, " %d", inst->bits3.urb.offset); - } - - space = 1; - if (gen >= 5) { - err |= control (file, "urb opcode", urb_opcode, - inst->bits3.urb_gen5.opcode, &space); - } - err |= control (file, "urb swizzle", urb_swizzle, - inst->bits3.urb.swizzle_control, &space); - err |= control (file, "urb allocate", urb_allocate, - inst->bits3.urb.allocate, &space); - err |= control (file, "urb used", urb_used, - inst->bits3.urb.used, &space); - err |= control (file, "urb complete", urb_complete, - inst->bits3.urb.complete, &space); - break; - case BRW_SFID_THREAD_SPAWNER: - break; - case GEN7_SFID_DATAPORT_DATA_CACHE: - format (file, " (%d, %d, %d)", - inst->bits3.gen7_dp.binding_table_index, - inst->bits3.gen7_dp.msg_control, - inst->bits3.gen7_dp.msg_type); - break; - - - default: - format (file, "unsupported target %d", target); - break; - } - if (space) - string (file, " "); - if (gen >= 5) { - format (file, "mlen %d", - inst->bits3.generic_gen5.msg_length); - format (file, " rlen %d", - inst->bits3.generic_gen5.response_length); - } else { - format (file, "mlen %d", - inst->bits3.generic.msg_length); - format (file, " rlen %d", - inst->bits3.generic.response_length); - } - } - pad (file, 64); - if (inst->header.opcode != BRW_OPCODE_NOP) { - string (file, "{"); - space = 1; - err |= control(file, "access mode", access_mode, inst->header.access_mode, &space); - if (gen >= 6) - err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space); - else - err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space); - err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space); - - if (gen >= 6) - err |= qtr_ctrl (file, inst); - else { - if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED && - opcode[inst->header.opcode].ndst > 0 && - inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE && - inst->bits1.da1.dest_reg_nr & (1 << 7)) { - format (file, " compr4"); - } else { - err |= control (file, "compression control", compr_ctrl, - inst->header.compression_control, &space); - } - } - - err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space); - if (gen >= 6) - err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space); - if (inst->header.opcode == BRW_OPCODE_SEND || - inst->header.opcode == BRW_OPCODE_SENDC) - err |= control (file, "end of thread", end_of_thread, - inst->bits3.generic.end_of_thread, &space); - if (space) - string (file, " "); - string (file, "}"); - } - string (file, ";"); - newline (file); - return err; + return printer->buf; +} + +static void _util_printf_format(2, 3) +disasm_printer_add(struct disasm_printer *printer, const char *format, ...) +{ + const size_t avail = sizeof(printer->buf) - printer->len; + va_list ap; + int written; + + va_start(ap, format); + written = vsnprintf(printer->buf + printer->len, avail, format, ap); + va_end(ap); + + /* truncated */ + if (written < 0 || written >= avail) { + memcpy(printer->buf + sizeof(printer->buf) - 4, "...", 4); + printer->len = sizeof(printer->buf) - 1; + } else { + printer->len += written; + } +} + +/** + * Pad to the specified column. + */ +static void +disasm_printer_column(struct disasm_printer *printer, int col) +{ + int len = DISASM_PRINTER_COLUMN_WIDTH * col; + + if (len <= printer->len) { + if (!printer->len) + return; + + /* at least one space */ + len = printer->len + 1; + } + + if (len >= sizeof(printer->buf)) { + len = sizeof(printer->buf) - 1; + + if (len <= printer->len) + return; + } + + memset(printer->buf + printer->len, ' ', len - printer->len); + printer->len = len; + printer->buf[printer->len] = '\0'; +} + +static void +disasm_printer_add_op(struct disasm_printer *printer, + const struct disasm_inst *inst) +{ + if (inst->pred_ctrl != GEN6_PREDCTRL_NONE) { + disasm_printer_add(printer, "(%c%s%s) ", + disasm_inst_pred_inv(inst), + disasm_inst_flag_reg(inst), + disasm_inst_pred_ctrl(inst)); + } + + disasm_printer_add(printer, "%s%s%s%s", + disasm_inst_opcode(inst), + disasm_inst_saturate(inst), + disasm_inst_debug_ctrl(inst), + disasm_inst_cond_modifier(inst)); + + if (inst->cond_modifier != GEN6_COND_NONE) { + switch (inst->opcode) { + case GEN6_OPCODE_SEL: + case GEN6_OPCODE_IF: + case GEN6_OPCODE_WHILE: + /* these do not update flag registers */ + break; + default: + disasm_printer_add(printer, ".%s", disasm_inst_flag_reg(inst)); + break; + } + } + + if (inst->opcode == GEN6_OPCODE_MATH) + disasm_printer_add(printer, " %s", disasm_inst_fc(inst)); + if (inst->opcode != GEN6_OPCODE_NOP) + disasm_printer_add(printer, "(%s)", disasm_inst_exec_size(inst)); +} + +static void +disasm_printer_add_operand(struct disasm_printer *printer, + const struct disasm_inst *inst, + const struct disasm_operand *operand) +{ + const char *name; + bool multi_regs; + + name = disasm_inst_file(inst, operand, &multi_regs); + if (!multi_regs) { + disasm_printer_add(printer, name); + return; + } + + if (operand->file == GEN6_FILE_IMM) { + switch (operand->type) { + case GEN6_TYPE_UD: + disasm_printer_add(printer, "0x%08xUD", inst->u.imm32); + break; + case GEN6_TYPE_D: + disasm_printer_add(printer, "%dD", inst->u.imm32); + break; + case GEN6_TYPE_UW: + disasm_printer_add(printer, "0x%04xUW", (uint16_t) inst->u.imm32); + break; + case GEN6_TYPE_W: + disasm_printer_add(printer, "%dW", (int16_t) inst->u.imm32); + break; + case GEN6_TYPE_UV_IMM: + disasm_printer_add(printer, "0x%08xUV", inst->u.imm32); + break; + case GEN6_TYPE_VF_IMM: + disasm_printer_add(printer, "Vector Float"); + break; + case GEN6_TYPE_V_IMM: + disasm_printer_add(printer, "0x%08xV", inst->u.imm32); + break; + case GEN6_TYPE_F: + disasm_printer_add(printer, "%-gF", uif(inst->u.imm32)); + break; + default: + disasm_printer_add(printer, "BAD"); + break; + } + + return; + } + + if (operand->addr_mode == GEN6_ADDRMODE_DIRECT) { + unsigned reg, subreg; + + reg = operand->reg; + if (operand->file == GEN6_FILE_ARF) + reg &= 0xf; + + subreg = operand->subreg / disasm_inst_type_size(inst, operand); + + if (subreg) + disasm_printer_add(printer, "%s%d.%d", name, reg, subreg); + else + disasm_printer_add(printer, "%s%d", name, reg); + } else { + disasm_printer_add(printer, "%s[a0.%d %d]", + name, operand->addr_subreg, operand->addr_imm); + } +} + +static void +disasm_printer_add_dst(struct disasm_printer *printer, + const struct disasm_inst *inst, + const struct disasm_dst_operand *dst) +{ + disasm_printer_add_operand(printer, inst, &dst->base); + + /* dst is an immediate when in EU_INSTRUCTION_BRANCH_CONDITIONAL form */ + if (disasm_inst_is_null(inst, &dst->base) || + dst->base.file == GEN6_FILE_IMM) + return; + + disasm_printer_add(printer, "<%s>%s%s", + disasm_inst_horz_stride(inst, dst->horz_stride), + disasm_inst_writemask(inst, dst->writemask), + disasm_inst_type(inst, &dst->base)); +} + +static void +disasm_printer_add_src(struct disasm_printer *printer, + const struct disasm_inst *inst, + const struct disasm_src_operand *src) +{ + static const char swizzle_chars[4] = { 'x', 'y', 'z', 'w' }; + char swizzle[5]; + + disasm_printer_add(printer, "%s%s", + disasm_inst_negate(inst, src->negate), + disasm_inst_absolute(inst, src->absolute)); + + disasm_printer_add_operand(printer, inst, &src->base); + + if (disasm_inst_is_null(inst, &src->base) || + src->base.file == GEN6_FILE_IMM) + return; + + if (src->swizzle_x == 0 && src->swizzle_y == 1 && + src->swizzle_z == 2 && src->swizzle_w == 3) { + swizzle[0] = '\0'; + } else if (src->swizzle_x == src->swizzle_y && + src->swizzle_x == src->swizzle_z && + src->swizzle_x == src->swizzle_w) { + swizzle[0] = swizzle_chars[src->swizzle_x]; + swizzle[1] = '\0'; + } else { + swizzle[0] = swizzle_chars[src->swizzle_x]; + swizzle[1] = swizzle_chars[src->swizzle_y]; + swizzle[2] = swizzle_chars[src->swizzle_z]; + swizzle[3] = swizzle_chars[src->swizzle_w]; + swizzle[4] = '\0'; + } + + disasm_printer_add(printer, "<%s,%s,%s>%s%s", + disasm_inst_vert_stride(inst, src->vert_stride), + disasm_inst_width(inst, src->width), + disasm_inst_horz_stride(inst, src->horz_stride), + swizzle, + disasm_inst_type(inst, &src->base)); +} + +static void +disasm_printer_add_ctrl(struct disasm_printer *printer, + const struct disasm_inst *inst) +{ + if (inst->opcode == GEN6_OPCODE_NOP) { + disasm_printer_add(printer, ";"); + return; + } + + disasm_printer_add(printer, "{%s%s%s%s%s%s%s%s };", + disasm_inst_access_mode(inst), + disasm_inst_mask_ctrl(inst), + disasm_inst_dep_ctrl(inst), + disasm_inst_qtr_ctrl(inst), + disasm_inst_cmpt_ctrl(inst), + disasm_inst_thread_ctrl(inst), + disasm_inst_acc_wr_ctrl(inst), + disasm_inst_eot(inst)); +} + +static void +disasm_printer_add_mdesc_sampler(struct disasm_printer *printer, + const struct disasm_inst *inst, + uint32_t mdesc) +{ + int op, simd; + + if (inst->dev->gen >= ILO_GEN(7)) { + op = READ(mdesc, GEN7_MSG_SAMPLER_OP); + simd = READ(mdesc, GEN7_MSG_SAMPLER_SIMD); + } { + op = READ(mdesc, GEN6_MSG_SAMPLER_OP); + simd = READ(mdesc, GEN6_MSG_SAMPLER_SIMD); + } + + disasm_printer_add(printer, " (%d, %d, %d, %d)", + READ(mdesc, GEN6_MSG_SAMPLER_SURFACE), + READ(mdesc, GEN6_MSG_SAMPLER_INDEX), + op, simd); +} + +static void +disasm_printer_add_mdesc_urb(struct disasm_printer *printer, + const struct disasm_inst *inst, + uint32_t mdesc) +{ + const char *op; + int offset; + bool interleaved, complete, allocate, used; + + if (inst->dev->gen >= ILO_GEN(7)) { + switch (READ(mdesc, GEN7_MSG_URB_OP)) { + case GEN7_MSG_URB_WRITE_HWORD: op = "write HWord"; break; + case GEN7_MSG_URB_WRITE_OWORD: op = "write OWord"; break; + case GEN7_MSG_URB_READ_HWORD: op = "read HWord"; break; + case GEN7_MSG_URB_READ_OWORD: op = "read OWord"; break; + case GEN7_MSG_URB_ATOMIC_MOV: op = "atomic mov"; break; + case GEN7_MSG_URB_ATOMIC_INC: op = "atomic inc"; break; + default: op = "BAD"; break; + } + + offset = READ(mdesc, GEN7_MSG_URB_GLOBAL_OFFSET); + interleaved = mdesc & GEN7_MSG_URB_INTERLEAVED; + complete = mdesc & GEN7_MSG_URB_COMPLETE; + + allocate = false; + used = false; + } else { + switch (READ(mdesc, GEN6_MSG_URB_OP)) { + case GEN6_MSG_URB_WRITE: op = "urb_write"; break; + case GEN6_MSG_URB_FF_SYNC: op = "ff_sync"; break; + default: op = "BAD"; break; + } + + offset = READ(mdesc, GEN6_MSG_URB_OFFSET); + interleaved = mdesc & GEN6_MSG_URB_INTERLEAVED; + complete = mdesc & GEN6_MSG_URB_COMPLETE; + + allocate = mdesc & GEN6_MSG_URB_ALLOCATE; + used = mdesc & GEN6_MSG_URB_USED; + } + + disasm_printer_add(printer, " %d %s%s%s%s%s", offset, op, + (interleaved) ? " interleave" : "", + (allocate) ? " allocate" : "", + (used) ? " used" : "", + (complete) ? " complete" : ""); +} + +static void +disasm_printer_add_mdesc_dp_sampler(struct disasm_printer *printer, + const struct disasm_inst *inst, + uint32_t mdesc) +{ + const int op = (inst->dev->gen >= ILO_GEN(7)) ? + READ(mdesc, GEN7_MSG_DP_OP) : READ(mdesc, GEN6_MSG_DP_OP); + const bool write_commit = (inst->dev->gen == ILO_GEN(6)) ? + (mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT) : 0; + + disasm_printer_add(printer, " (%d, %d, %d, %d)", + READ(mdesc, GEN6_MSG_DP_SURFACE), + READ(mdesc, GEN6_MSG_DP_OWORD_BLOCK_SIZE), + op, write_commit); +} + +static void +disasm_printer_add_mdesc_dp_rc(struct disasm_printer *printer, + const struct disasm_inst *inst, + uint32_t mdesc) +{ + const int op = (inst->dev->gen >= ILO_GEN(7)) ? + READ(mdesc, GEN7_MSG_DP_OP) : READ(mdesc, GEN6_MSG_DP_OP); + const char *str; + bool is_rt_write; + + if (inst->dev->gen >= ILO_GEN(7.5)) { + switch (op) { + case GEN75_MSG_DP_RC_MEDIA_BLOCK_READ: str = "media block read"; break; + case GEN75_MSG_DP_RC_MEMORY_FENCE: str = "memory fence"; break; + case GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE: str = "media block write"; break; + case GEN75_MSG_DP_RC_RT_WRITE: str = "RT write"; break; + default: str = "BAD"; break; + } + + is_rt_write = (op == GEN75_MSG_DP_RC_RT_WRITE); + } else if (inst->dev->gen >= ILO_GEN(7)) { + switch (op) { + case GEN7_MSG_DP_RC_MEDIA_BLOCK_READ: str = "media block read"; break; + case GEN7_MSG_DP_RC_TYPED_SURFACE_READ: str = "typed surface read"; break; + case GEN7_MSG_DP_RC_TYPED_ATOMIC_OP: str = "typed atomic op"; break; + case GEN7_MSG_DP_RC_MEMORY_FENCE: str = "memory fence"; break; + case GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE: str = "media block write"; break; + case GEN7_MSG_DP_RC_RT_WRITE: str = "RT write"; break; + case GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE: str = "typed surface write"; break; + default: str = "BAD"; break; + } + + is_rt_write = (op == GEN7_MSG_DP_RC_RT_WRITE); + } else { + switch (op) { + case GEN6_MSG_DP_OWORD_BLOCK_READ: str = "OWORD block read"; break; + case GEN6_MSG_DP_RT_UNORM_READ: str = "RT UNORM read"; break; + case GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ: str = "OWORD dual block read"; break; + case GEN6_MSG_DP_MEDIA_BLOCK_READ: str = "media block read"; break; + case GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ: str = "unaligned OWORD block read"; break; + case GEN6_MSG_DP_DWORD_SCATTERED_READ: str = "DWORD scattered read"; break; + case GEN6_MSG_DP_DWORD_ATOMIC_WRITE: str = "DWORD atomic write"; break; + case GEN6_MSG_DP_OWORD_BLOCK_WRITE: str = "OWORD block write"; break; + case GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE: str = "OWORD dual block_write"; break; + case GEN6_MSG_DP_MEDIA_BLOCK_WRITE: str = "media block write"; break; + case GEN6_MSG_DP_DWORD_SCATTERED_WRITE: str = "DWORD scattered write"; break; + case GEN6_MSG_DP_RT_WRITE: str = "RT write"; break; + case GEN6_MSG_DP_SVB_WRITE: str = "SVB write"; break; + case GEN6_MSG_DP_RT_UNORM_WRITE: str = "RT UNORM write"; break; + default: str = "BAD"; break; + } + + is_rt_write = (op == GEN6_MSG_DP_RT_WRITE); + } + + disasm_printer_add(printer, " %s", str); + + if (is_rt_write) { + switch (mdesc & GEN6_MSG_DP_RT_MODE__MASK) { + case GEN6_MSG_DP_RT_MODE_SIMD16: str = "SIMD16"; break; + case GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA: str = "SIMD16/RepData"; break; + case GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO: str = "SIMD8/DualSrcLow"; break; + case GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI: str = "SIMD8/DualSrcHigh"; break; + case GEN6_MSG_DP_RT_MODE_SIMD8_LO: str = "SIMD8"; break; + case GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR: str = "SIMD8/ImageWrite"; break; + default: str = "BAD"; break; + } + + disasm_printer_add(printer, " %s%s%s%s", str, + (mdesc & GEN6_MSG_DP_SLOTGRP_HI) ? " Hi" : "", + (mdesc & GEN6_MSG_DP_RT_LAST) ? " LastRT" : "", + (inst->dev->gen == ILO_GEN(6) && + (mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT)) ? " WriteCommit" : ""); + } + + disasm_printer_add(printer, " Surface = %d", + READ(mdesc, GEN6_MSG_DP_SURFACE)); +} + +static void +disasm_printer_add_mdesc(struct disasm_printer *printer, + const struct disasm_inst *inst) +{ + const uint32_t mdesc = inst->u.imm32; + + assert(inst->opcode == GEN6_OPCODE_SEND || + inst->opcode == GEN6_OPCODE_SENDC); + assert(inst->src1.base.file == GEN6_FILE_IMM); + + disasm_printer_add(printer, " %s", disasm_inst_sfid(inst)); + + switch (inst->sfid) { + case GEN6_SFID_SAMPLER: + disasm_printer_add_mdesc_sampler(printer, inst, mdesc); + break; + case GEN6_SFID_DP_SAMPLER: + disasm_printer_add_mdesc_dp_sampler(printer, inst, mdesc); + break; + case GEN6_SFID_DP_RC: + disasm_printer_add_mdesc_dp_rc(printer, inst, mdesc); + break; + case GEN6_SFID_URB: + disasm_printer_add_mdesc_urb(printer, inst, mdesc); + break; + case GEN6_SFID_DP_CC: + case GEN7_SFID_DP_DC0: + case GEN7_SFID_PI: + case GEN75_SFID_DP_DC1: + default: + break; + } + + disasm_printer_add(printer, " mlen %d rlen %d", + READ(mdesc, GEN6_MSG_MLEN), + READ(mdesc, GEN6_MSG_RLEN)); +} + +static void +disasm_printer_print_inst(struct disasm_printer *printer, + const struct disasm_inst *inst) +{ + int col = 0; + + disasm_printer_reset(printer); + + disasm_printer_column(printer, col++); + disasm_printer_add_op(printer, inst); + + if (inst->has_jip || inst->has_uip) { + if (inst->has_jip) { + disasm_printer_column(printer, col++); + disasm_printer_add(printer, "JIP: %d", (int16_t) inst->u.imm32); + } + + if (inst->has_uip) { + disasm_printer_column(printer, col++); + disasm_printer_add(printer, "UIP: %d", + (int16_t) (inst->u.imm32 >> 16)); + } + } else { + const int src_count = disasm_opcode_table[inst->opcode].src_count; + const struct disasm_src_operand *src[3]; + int i; + + /* get src operands */ + switch (src_count) { + case 3: + src[2] = &inst->u.src2; + case 2: + src[1] = &inst->src1; + case 1: + src[0] = &inst->src0; + case 0: + default: + break; + } + + if (src_count) { + disasm_printer_column(printer, col++); + disasm_printer_add_dst(printer, inst, &inst->dst); + + for (i = 0; i < src_count; i++) { + disasm_printer_column(printer, col++); + disasm_printer_add_src(printer, inst, src[i]); + } + } + } + + if (inst->opcode == GEN6_OPCODE_SEND || + inst->opcode == GEN6_OPCODE_SENDC) { + /* start a new line */ + ilo_printf("%s\n", disasm_printer_get_string(printer)); + disasm_printer_reset(printer); + col = 0; + + disasm_printer_column(printer, col++); + + disasm_printer_column(printer, col++); + disasm_printer_add_mdesc(printer, inst); + } + + if (col < 4) + col = 4; + + disasm_printer_column(printer, col++); + disasm_printer_add_ctrl(printer, inst); + + ilo_printf("%s\n", disasm_printer_get_string(printer)); +} + +void +toy_compiler_disassemble(const struct ilo_dev_info *dev, + const void *kernel, int size, + bool dump_hex) +{ + const uint32_t *cur = (const uint32_t *) kernel; + const uint32_t *end = cur + size / sizeof(*cur); + struct disasm_printer printer; + + disasm_printer_reset(&printer); + + while (cur < end) { + struct disasm_inst inst; + const bool compacted = (cur[0] & GEN6_INST_CMPTCTRL); + const uint32_t *dw = cur; + uint32_t temp[4]; + + cur += (compacted) ? 2 : 4; + /* incomplete instruction */ + if (cur > end) + break; + + if (compacted) { + /* no compaction support yet */ + memset(temp, 0, sizeof(temp)); + dw = temp; + } + + if (dump_hex) { + ilo_printf("0x%08x 0x%08x 0x%08x 0x%08x ", + dw[0], dw[1], dw[2], dw[3]); + } + + memset(&inst, 0, sizeof(inst)); + inst.dev = dev; + disasm_inst_decode(&inst, dw); + inst.cmpt_ctrl = compacted; + + disasm_printer_print_inst(&printer, &inst); + } } |