diff options
| author | Chia-I Wu <[email protected]> | 2015-05-15 10:39:05 +0800 |
|---|---|---|
| committer | Chia-I Wu <[email protected]> | 2015-06-14 15:43:20 +0800 |
| commit | 9da9cf729ff74684902cbb4b53b5cccd442df28e (patch) | |
| tree | 3135e12d4e217f0261f7bdff5f0c951f170708e5 /src/gallium/drivers/ilo/ilo_state.c | |
| parent | 1885ac490834e70d831b5b4a287c272b4148761c (diff) | |
ilo: fix "Render Cache Read Write Mode"
It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
Diffstat (limited to 'src/gallium/drivers/ilo/ilo_state.c')
| -rw-r--r-- | src/gallium/drivers/ilo/ilo_state.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/gallium/drivers/ilo/ilo_state.c b/src/gallium/drivers/ilo/ilo_state.c index b1bd49a0b6c..7627fcf7c96 100644 --- a/src/gallium/drivers/ilo/ilo_state.c +++ b/src/gallium/drivers/ilo/ilo_state.c @@ -112,7 +112,7 @@ finalize_cbuf_state(struct ilo_context *ilo, ilo_buffer(cbuf->cso[i].resource), offset, cbuf->cso[i].user_buffer_size, util_format_get_blocksize(elem_format), elem_format, - false, false, &cbuf->cso[i].surface); + false, &cbuf->cso[i].surface); ilo->state_vector.dirty |= ILO_DIRTY_CBUF; } @@ -683,7 +683,7 @@ ilo_set_constant_buffer(struct pipe_context *pipe, ilo_buffer(buf[i].buffer), buf[i].buffer_offset, buf[i].buffer_size, util_format_get_blocksize(elem_format), elem_format, - false, false, &cso->surface); + false, &cso->surface); cso->user_buffer = NULL; cso->user_buffer_size = 0; @@ -1007,7 +1007,7 @@ ilo_create_sampler_view(struct pipe_context *pipe, ilo_gpe_init_view_surface_for_buffer(dev, ilo_buffer(res), first_elem * elem_size, num_elems * elem_size, - elem_size, templ->format, false, false, &view->surface); + elem_size, templ->format, false, &view->surface); } else { struct ilo_texture *tex = ilo_texture(res); @@ -1066,10 +1066,6 @@ ilo_create_surface(struct pipe_context *pipe, /* relax this? */ assert(tex->base.target != PIPE_BUFFER); - /* - * classic i965 sets render_cache_rw for constant buffers and sol - * surfaces but not render buffers. Why? - */ ilo_gpe_init_view_surface_for_image(dev, &tex->image, tex->base.target, templ->format, templ->u.tex.level, 1, |