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authorChia-I Wu <[email protected]>2014-04-13 00:33:00 +0800
committerChia-I Wu <[email protected]>2014-04-14 20:45:03 +0800
commit01e3e82a56310932667c60bcca9cc9fdfd8b87c4 (patch)
treed298945bbcdd31cae3df0f0b66af715c63f03e05 /src/gallium/drivers/ilo/ilo_screen.c
parentd75a8799fded5f8cd7ae4b20d935ff8a088dc122 (diff)
ilo: add genhw headers
All except genhw.h are generated by https://github.com/olvaffe/envytools/. intel_chipset.h is deprecated.
Diffstat (limited to 'src/gallium/drivers/ilo/ilo_screen.c')
-rw-r--r--src/gallium/drivers/ilo/ilo_screen.c157
1 files changed, 41 insertions, 116 deletions
diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
index 4bea564e6a0..8c2e04e220d 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -28,8 +28,7 @@
#include "util/u_format_s3tc.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
-#include "intel_chipset.h"
-#include "intel_reg.h" /* for TIMESTAMP */
+#include "genhw/genhw.h" /* for TIMESTAMP */
#include "intel_winsys.h"
#include "ilo_context.h"
@@ -457,89 +456,39 @@ static const char *
ilo_get_name(struct pipe_screen *screen)
{
struct ilo_screen *is = ilo_screen(screen);
- const char *chipset;
-
- /* stolen from classic i965 */
- switch (is->dev.devid) {
- case PCI_CHIP_SANDYBRIDGE_GT1:
- case PCI_CHIP_SANDYBRIDGE_GT2:
- case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
- chipset = "Intel(R) Sandybridge Desktop";
- break;
- case PCI_CHIP_SANDYBRIDGE_M_GT1:
- case PCI_CHIP_SANDYBRIDGE_M_GT2:
- case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
- chipset = "Intel(R) Sandybridge Mobile";
- break;
- case PCI_CHIP_SANDYBRIDGE_S:
- chipset = "Intel(R) Sandybridge Server";
- break;
- case PCI_CHIP_IVYBRIDGE_GT1:
- case PCI_CHIP_IVYBRIDGE_GT2:
- chipset = "Intel(R) Ivybridge Desktop";
- break;
- case PCI_CHIP_IVYBRIDGE_M_GT1:
- case PCI_CHIP_IVYBRIDGE_M_GT2:
- chipset = "Intel(R) Ivybridge Mobile";
- break;
- case PCI_CHIP_IVYBRIDGE_S_GT1:
- case PCI_CHIP_IVYBRIDGE_S_GT2:
- chipset = "Intel(R) Ivybridge Server";
- break;
- case PCI_CHIP_BAYTRAIL_M_1:
- case PCI_CHIP_BAYTRAIL_M_2:
- case PCI_CHIP_BAYTRAIL_M_3:
- case PCI_CHIP_BAYTRAIL_M_4:
- case PCI_CHIP_BAYTRAIL_D:
+ const char *chipset = NULL;
+
+ if (gen_is_vlv(is->dev.devid)) {
chipset = "Intel(R) Bay Trail";
- break;
- case PCI_CHIP_HASWELL_GT1:
- case PCI_CHIP_HASWELL_GT2:
- case PCI_CHIP_HASWELL_GT3:
- case PCI_CHIP_HASWELL_SDV_GT1:
- case PCI_CHIP_HASWELL_SDV_GT2:
- case PCI_CHIP_HASWELL_SDV_GT3:
- case PCI_CHIP_HASWELL_ULT_GT1:
- case PCI_CHIP_HASWELL_ULT_GT2:
- case PCI_CHIP_HASWELL_ULT_GT3:
- case PCI_CHIP_HASWELL_CRW_GT1:
- case PCI_CHIP_HASWELL_CRW_GT2:
- case PCI_CHIP_HASWELL_CRW_GT3:
- chipset = "Intel(R) Haswell Desktop";
- break;
- case PCI_CHIP_HASWELL_M_GT1:
- case PCI_CHIP_HASWELL_M_GT2:
- case PCI_CHIP_HASWELL_M_GT3:
- case PCI_CHIP_HASWELL_SDV_M_GT1:
- case PCI_CHIP_HASWELL_SDV_M_GT2:
- case PCI_CHIP_HASWELL_SDV_M_GT3:
- case PCI_CHIP_HASWELL_ULT_M_GT1:
- case PCI_CHIP_HASWELL_ULT_M_GT2:
- case PCI_CHIP_HASWELL_ULT_M_GT3:
- case PCI_CHIP_HASWELL_CRW_M_GT1:
- case PCI_CHIP_HASWELL_CRW_M_GT2:
- case PCI_CHIP_HASWELL_CRW_M_GT3:
- chipset = "Intel(R) Haswell Mobile";
- break;
- case PCI_CHIP_HASWELL_S_GT1:
- case PCI_CHIP_HASWELL_S_GT2:
- case PCI_CHIP_HASWELL_S_GT3:
- case PCI_CHIP_HASWELL_SDV_S_GT1:
- case PCI_CHIP_HASWELL_SDV_S_GT2:
- case PCI_CHIP_HASWELL_SDV_S_GT3:
- case PCI_CHIP_HASWELL_ULT_S_GT1:
- case PCI_CHIP_HASWELL_ULT_S_GT2:
- case PCI_CHIP_HASWELL_ULT_S_GT3:
- case PCI_CHIP_HASWELL_CRW_S_GT1:
- case PCI_CHIP_HASWELL_CRW_S_GT2:
- case PCI_CHIP_HASWELL_CRW_S_GT3:
- chipset = "Intel(R) Haswell Server";
- break;
- default:
- chipset = "Unknown Intel Chipset";
- break;
+ }
+ else if (gen_is_hsw(is->dev.devid)) {
+ if (gen_is_desktop(is->dev.devid))
+ chipset = "Intel(R) Haswell Desktop";
+ else if (gen_is_mobile(is->dev.devid))
+ chipset = "Intel(R) Haswell Mobile";
+ else if (gen_is_server(is->dev.devid))
+ chipset = "Intel(R) Haswell Server";
+ }
+ else if (gen_is_ivb(is->dev.devid)) {
+ if (gen_is_desktop(is->dev.devid))
+ chipset = "Intel(R) Ivybridge Desktop";
+ else if (gen_is_mobile(is->dev.devid))
+ chipset = "Intel(R) Ivybridge Mobile";
+ else if (gen_is_server(is->dev.devid))
+ chipset = "Intel(R) Ivybridge Server";
+ }
+ else if (gen_is_snb(is->dev.devid)) {
+ if (gen_is_desktop(is->dev.devid))
+ chipset = "Intel(R) Sandybridge Desktop";
+ else if (gen_is_mobile(is->dev.devid))
+ chipset = "Intel(R) Sandybridge Mobile";
+ else if (gen_is_server(is->dev.devid))
+ chipset = "Intel(R) Sandybridge Server";
}
+ if (!chipset)
+ chipset = "Unknown Intel Chipset";
+
return chipset;
}
@@ -698,45 +647,21 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
* 256k 8096 4096"
*/
- if (IS_HASWELL(info->devid)) {
+ if (gen_is_hsw(info->devid)) {
dev->gen = ILO_GEN(7.5);
-
- if (IS_HSW_GT3(info->devid)) {
- dev->gt = 3;
- dev->urb_size = 512 * 1024;
- }
- else if (IS_HSW_GT2(info->devid)) {
- dev->gt = 2;
- dev->urb_size = 256 * 1024;
- }
- else {
- dev->gt = 1;
- dev->urb_size = 128 * 1024;
- }
+ dev->gt = gen_get_hsw_gt(info->devid);
+ dev->urb_size = ((dev->gt == 3) ? 512 :
+ (dev->gt == 2) ? 256 : 128) * 1024;
}
- else if (IS_GEN7(info->devid)) {
+ else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
dev->gen = ILO_GEN(7);
-
- if (IS_IVB_GT2(info->devid)) {
- dev->gt = 2;
- dev->urb_size = 256 * 1024;
- }
- else {
- dev->gt = 1;
- dev->urb_size = 128 * 1024;
- }
+ dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
+ dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
}
- else if (IS_GEN6(info->devid)) {
+ else if (gen_is_snb(info->devid)) {
dev->gen = ILO_GEN(6);
-
- if (IS_SNB_GT2(info->devid)) {
- dev->gt = 2;
- dev->urb_size = 64 * 1024;
- }
- else {
- dev->gt = 1;
- dev->urb_size = 32 * 1024;
- }
+ dev->gt = gen_get_snb_gt(info->devid);
+ dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
}
else {
ilo_err("unknown GPU generation\n");