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authorChia-I Wu <[email protected]>2014-09-25 12:32:21 +0800
committerChia-I Wu <[email protected]>2014-09-26 21:15:55 +0800
commit7fc74153166ea59d72083f9a09e9ddb966a23985 (patch)
treeea77a898c0848296f670f9a3179f336811c2f783 /src/gallium/drivers/ilo/ilo_render.c
parent0afc17ea4986288c3ca3359242585997a11a1255 (diff)
ilo: simplify ilo_render_get_query_len()
For all supported query types, we always emit a PIPE_CONTROL. Call ilo_render_get_flush_len() for simplicity and clarity. Signed-off-by: Chia-I Wu <[email protected]>
Diffstat (limited to 'src/gallium/drivers/ilo/ilo_render.c')
-rw-r--r--src/gallium/drivers/ilo/ilo_render.c37
1 files changed, 12 insertions, 25 deletions
diff --git a/src/gallium/drivers/ilo/ilo_render.c b/src/gallium/drivers/ilo/ilo_render.c
index 3dea7c6a0fa..2995ee8346f 100644
--- a/src/gallium/drivers/ilo/ilo_render.c
+++ b/src/gallium/drivers/ilo/ilo_render.c
@@ -238,41 +238,28 @@ ilo_render_get_query_len(const struct ilo_render *render,
ILO_DEV_ASSERT(render->dev, 6, 7.5);
+ /* always a flush or a variant of flush */
+ len = ilo_render_get_flush_len(render);
+
switch (query_type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
- len = GEN6_PIPE_CONTROL__SIZE;
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- len *= 3;
- break;
case PIPE_QUERY_TIMESTAMP:
case PIPE_QUERY_TIME_ELAPSED:
- len = GEN6_PIPE_CONTROL__SIZE;
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- len *= 2;
+ /* no reg */
break;
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_PRIMITIVES_EMITTED:
- len = GEN6_PIPE_CONTROL__SIZE;
- if (ilo_dev_gen(render->dev) == ILO_GEN(6))
- len *= 3;
-
len += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2;
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
- if (ilo_dev_gen(render->dev) >= ILO_GEN(7)) {
- const int num_regs = 10;
- const int num_pads = 1;
-
- len = GEN6_PIPE_CONTROL__SIZE +
- GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
- GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
- } else {
- const int num_regs = 8;
- const int num_pads = 3;
-
- len = GEN6_PIPE_CONTROL__SIZE * 3 +
- GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
- GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
+ {
+ const int num_regs =
+ (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ? 10 : 8;
+ const int num_pads =
+ (ilo_dev_gen(render->dev) >= ILO_GEN(7)) ? 1 : 3;
+
+ len += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
+ GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
}
break;
default: