ilo: replace intel_tiling_mode by gen_surface_tiling

The former is used by the kernel driver to set up fence registers and to pass
tiling info across processes.  It lacks INTEL_TILING_W, which made our code
less expressive.

1 files changed, 42 insertions, 44 deletions

diff --git a/src/gallium/drivers/ilo/ilo_layout.c b/src/gallium/drivers/ilo/ilo_layout.c
index 0b639b2ef17..8f83ccb3a08 100644
--- a/src/gallium/drivers/ilo/ilo_layout.c
+++ b/src/gallium/drivers/ilo/ilo_layout.c
@@ -28,10 +28,10 @@
 #include "ilo_layout.h"
 
 enum {
-   LAYOUT_TILING_NONE = 1 << INTEL_TILING_NONE,
-   LAYOUT_TILING_X = 1 << INTEL_TILING_X,
-   LAYOUT_TILING_Y = 1 << INTEL_TILING_Y,
-   LAYOUT_TILING_W = 1 << (INTEL_TILING_Y + 1),
+   LAYOUT_TILING_NONE = 1 << GEN6_TILING_NONE,
+   LAYOUT_TILING_X = 1 << GEN6_TILING_X,
+   LAYOUT_TILING_Y = 1 << GEN6_TILING_Y,
+   LAYOUT_TILING_W = 1 << GEN8_TILING_W,
 
    LAYOUT_TILING_ALL = (LAYOUT_TILING_NONE |
                         LAYOUT_TILING_X |
@@ -427,7 +427,7 @@ layout_init_alignments(struct ilo_layout *layout,
          (templ->nr_samples > 1) ||
          (ilo_dev_gen(params->dev) >= ILO_GEN(8)) ||
          (ilo_dev_gen(params->dev) >= ILO_GEN(7) &&
-          layout->tiling == INTEL_TILING_Y &&
+          layout->tiling == GEN6_TILING_Y &&
           (templ->bind & PIPE_BIND_RENDER_TARGET));
 
       if (ilo_dev_gen(params->dev) >= ILO_GEN(7) &&
@@ -460,7 +460,8 @@ layout_get_valid_tilings(const struct ilo_layout *layout,
 {
    const struct pipe_resource *templ = params->templ;
    const enum pipe_format format = layout->format;
-   unsigned valid_tilings = LAYOUT_TILING_ALL;
+   /* W-tiling is too restrictive */
+   unsigned valid_tilings = LAYOUT_TILING_ALL & ~LAYOUT_TILING_W;
 
    /*
     * From the Sandy Bridge PRM, volume 1 part 2, page 32:
@@ -495,7 +496,8 @@ layout_get_valid_tilings(const struct ilo_layout *layout,
    if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
       switch (format) {
       case PIPE_FORMAT_S8_UINT:
-         valid_tilings &= LAYOUT_TILING_W;
+         /* this is the only case LAYOUT_TILING_W is valid */
+         valid_tilings = LAYOUT_TILING_W;
          break;
       default:
          valid_tilings &= LAYOUT_TILING_Y;
@@ -545,10 +547,6 @@ layout_init_tiling(struct ilo_layout *layout,
    const struct pipe_resource *templ = params->templ;
    unsigned valid_tilings = layout_get_valid_tilings(layout, params);
 
-   /* no hardware support for W-tile */
-   if (valid_tilings & LAYOUT_TILING_W)
-      valid_tilings = (valid_tilings & ~LAYOUT_TILING_W) | LAYOUT_TILING_NONE;
-
    layout->valid_tilings = valid_tilings;
 
    if (templ->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) {
@@ -570,11 +568,13 @@ layout_init_tiling(struct ilo_layout *layout,
 
    /* prefer tiled over linear */
    if (valid_tilings & LAYOUT_TILING_Y)
-      layout->tiling = INTEL_TILING_Y;
+      layout->tiling = GEN6_TILING_Y;
    else if (valid_tilings & LAYOUT_TILING_X)
-      layout->tiling = INTEL_TILING_X;
+      layout->tiling = GEN6_TILING_X;
+   else if (valid_tilings & LAYOUT_TILING_W)
+      layout->tiling = GEN8_TILING_W;
    else
-      layout->tiling = INTEL_TILING_NONE;
+      layout->tiling = GEN6_TILING_NONE;
 }
 
 static void
@@ -755,7 +755,7 @@ layout_want_mcs(struct ilo_layout *layout,
        *        32bpp, 64bpp and 128bpp.
        *      ..."
        */
-      if (layout->tiling != INTEL_TILING_NONE &&
+      if (layout->tiling != GEN6_TILING_NONE &&
           templ->last_level == 0 && templ->array_size == 1) {
          switch (layout->block_size) {
          case 4:
@@ -909,7 +909,7 @@ layout_calculate_bo_size(struct ilo_layout *layout,
        */
       if (ilo_dev_gen(params->dev) >= ILO_GEN(7.5) &&
           (params->templ->bind & PIPE_BIND_SAMPLER_VIEW) &&
-          layout->tiling == INTEL_TILING_NONE) {
+          layout->tiling == GEN6_TILING_NONE) {
          layout->bo_height +=
             (64 + layout->bo_stride - 1) / layout->bo_stride;
       }
@@ -931,33 +931,30 @@ layout_calculate_bo_size(struct ilo_layout *layout,
        * need to check layout->templ->bind.
        */
       switch (layout->tiling) {
-      case INTEL_TILING_X:
+      case GEN6_TILING_X:
          align_w = 512;
          align_h = 8;
          break;
-      case INTEL_TILING_Y:
+      case GEN6_TILING_Y:
          align_w = 128;
          align_h = 32;
          break;
+      case GEN8_TILING_W:
+         /*
+          * From the Sandy Bridge PRM, volume 1 part 2, page 22:
+          *
+          *     "A 4KB tile is subdivided into 8-high by 8-wide array of
+          *      Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
+          *      bytes."
+          */
+         align_w = 64;
+         align_h = 64;
+         break;
       default:
-         if (layout->format == PIPE_FORMAT_S8_UINT) {
-            /*
-             * From the Sandy Bridge PRM, volume 1 part 2, page 22:
-             *
-             *     "A 4KB tile is subdivided into 8-high by 8-wide array of
-             *      Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
-             *      bytes."
-             *
-             * Since we asked for INTEL_TILING_NONE instead of the non-existent
-             * INTEL_TILING_W, we want to align to W tiles here.
-             */
-            align_w = 64;
-            align_h = 64;
-         } else {
-            /* some good enough values */
-            align_w = 64;
-            align_h = 2;
-         }
+         assert(layout->tiling == GEN6_TILING_NONE);
+         /* some good enough values */
+         align_w = 64;
+         align_h = 2;
          break;
       }
 
@@ -965,7 +962,7 @@ layout_calculate_bo_size(struct ilo_layout *layout,
       h = align(h, align_h);
 
       /* make sure the bo is mappable */
-      if (layout->tiling != INTEL_TILING_NONE) {
+      if (layout->tiling != GEN6_TILING_NONE) {
          /*
           * Usually only the first 256MB of the GTT is mappable.
           *
@@ -979,7 +976,7 @@ layout_calculate_bo_size(struct ilo_layout *layout,
           */
          if (mappable_gtt_size / w / 4 < h) {
             if (layout->valid_tilings & LAYOUT_TILING_NONE) {
-               layout->tiling = INTEL_TILING_NONE;
+               layout->tiling = GEN6_TILING_NONE;
                /* MCS support for non-MSRTs is limited to tiled RTs */
                if (layout->aux == ILO_LAYOUT_AUX_MCS &&
                    params->templ->nr_samples <= 1)
@@ -1251,11 +1248,11 @@ layout_calculate_mcs_size(struct ilo_layout *layout,
        * hit out-of-bound access.
        */
       switch (layout->tiling) {
-      case INTEL_TILING_X:
+      case GEN6_TILING_X:
          downscale_x = 64 / layout->block_size;
          downscale_y = 2;
          break;
-      case INTEL_TILING_Y:
+      case GEN6_TILING_Y:
          downscale_x = 32 / layout->block_size;
          downscale_y = 4;
          break;
@@ -1315,7 +1312,7 @@ layout_init_for_transfer(struct ilo_layout *layout,
    layout->walk = ILO_LAYOUT_WALK_LOD;
 
    layout->valid_tilings = LAYOUT_TILING_NONE;
-   layout->tiling = INTEL_TILING_NONE;
+   layout->tiling = GEN6_TILING_NONE;
 
    layout->align_i = layout->block_width;
    layout->align_j = layout->block_height;
@@ -1387,14 +1384,15 @@ void ilo_layout_init(struct ilo_layout *layout,
  */
 bool
 ilo_layout_update_for_imported_bo(struct ilo_layout *layout,
-                                  enum intel_tiling_mode tiling,
+                                  enum gen_surface_tiling tiling,
                                   unsigned bo_stride)
 {
    if (!(layout->valid_tilings & (1 << tiling)))
       return false;
 
-   if ((tiling == INTEL_TILING_X && bo_stride % 512) ||
-       (tiling == INTEL_TILING_Y && bo_stride % 128))
+   if ((tiling == GEN6_TILING_X && bo_stride % 512) ||
+       (tiling == GEN6_TILING_Y && bo_stride % 128) ||
+       (tiling == GEN8_TILING_W && bo_stride % 64))
       return false;
 
    layout->tiling = tiling;