ilo: update genhw headers

Accumulated changes for various renames and additions, including Gen8
definitions.  Some of the dynamic state __SIZE no longer means the size of an
element, but the size of an array of elements.  The changes can be seen in
ilo_render_dynamic.c.

11 files changed, 1604 insertions, 431 deletions

diff --git a/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
index 94d3136fdb0..6d58e024a64 100644
--- a/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -79,30 +79,43 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_BLITTER_BR26_SRC_Y1__SHIFT				16
 #define GEN6_BLITTER_BR26_SRC_X1__MASK				0x0000ffff
 #define GEN6_BLITTER_BR26_SRC_X1__SHIFT				0
-#define GEN6_COLOR_BLT__SIZE					5
+#define GEN6_COLOR_BLT__SIZE					6
 
 
 
 
 
 
-#define GEN6_SRC_COPY_BLT__SIZE					6
 
 
+#define GEN6_SRC_COPY_BLT__SIZE					8
 
 
 
 
 
-#define GEN6_XY_COLOR_BLT__SIZE					6
 
 
 
 
 
 
+#define GEN6_XY_COLOR_BLT__SIZE					7
+
+
+
+
+
+
+
+
+
+#define GEN6_XY_SRC_COPY_BLT__SIZE				10
+
+
+
+
 
-#define GEN6_XY_SRC_COPY_BLT__SIZE				8
 
 
 
diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
index 5a253017089..99f6bbc932f 100644
--- a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -67,6 +67,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_OPCODE_CALLA					0x2b
 #define GEN6_OPCODE_CALL					0x2c
 #define GEN6_OPCODE_RETURN					0x2d
+#define GEN8_OPCODE_GOTO					0x2e
 #define GEN6_OPCODE_WAIT					0x30
 #define GEN6_OPCODE_SEND					0x31
 #define GEN6_OPCODE_SENDC					0x32
@@ -160,6 +161,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MATH_INT_DIV					0xb
 #define GEN6_MATH_INT_DIV_QUOTIENT				0xc
 #define GEN6_MATH_INT_DIV_REMAINDER				0xd
+#define GEN8_MATH_INVM						0xe
+#define GEN8_MATH_RSQRTM					0xf
 #define GEN6_SFID_NULL						0x0
 #define GEN6_SFID_SAMPLER					0x2
 #define GEN6_SFID_GATEWAY					0x3
@@ -184,9 +187,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_TYPE_B						0x5
 #define GEN7_TYPE_DF						0x6
 #define GEN6_TYPE_F						0x7
+#define GEN8_TYPE_UQ						0x8
+#define GEN8_TYPE_Q						0x9
+#define GEN8_TYPE_HF						0xa
 #define GEN6_TYPE_UV_IMM					0x4
 #define GEN6_TYPE_VF_IMM					0x5
 #define GEN6_TYPE_V_IMM						0x6
+#define GEN8_TYPE_DF_IMM					0xa
+#define GEN8_TYPE_HF_IMM					0xb
 #define GEN7_TYPE_F_3SRC					0x0
 #define GEN7_TYPE_D_3SRC					0x1
 #define GEN7_TYPE_UD_3SRC					0x2
@@ -227,6 +235,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INST_SATURATE					(0x1 << 31)
 #define GEN6_INST_DEBUGCTRL					(0x1 << 30)
 #define GEN6_INST_CMPTCTRL					(0x1 << 29)
+#define GEN8_INST_BRANCHCTRL					(0x1 << 28)
 #define GEN6_INST_ACCWRCTRL					(0x1 << 28)
 #define GEN6_INST_CONDMODIFIER__MASK				0x0f000000
 #define GEN6_INST_CONDMODIFIER__SHIFT				24
@@ -247,6 +256,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INST_DEPCTRL__SHIFT				10
 #define GEN6_INST_MASKCTRL__MASK				0x00000200
 #define GEN6_INST_MASKCTRL__SHIFT				9
+#define GEN8_INST_NIBCTRL					(0x1 << 11)
+#define GEN8_INST_DEPCTRL__MASK					0x00000600
+#define GEN8_INST_DEPCTRL__SHIFT				9
 #define GEN6_INST_ACCESSMODE__MASK				0x00000100
 #define GEN6_INST_ACCESSMODE__SHIFT				8
 #define GEN6_INST_OPCODE__MASK					0x0000007f
@@ -263,12 +275,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INST_DST_ADDR_SUBREG__SHIFT			26
 #define GEN6_INST_DST_ADDR_IMM__MASK				0x03ff0000
 #define GEN6_INST_DST_ADDR_IMM__SHIFT				16
+#define GEN8_INST_DST_ADDR_SUBREG__MASK				0x1e000000
+#define GEN8_INST_DST_ADDR_SUBREG__SHIFT			25
+#define GEN8_INST_DST_ADDR_IMM__MASK				0x01ff0000
+#define GEN8_INST_DST_ADDR_IMM__SHIFT				16
 #define GEN6_INST_DST_SUBREG_ALIGN16__MASK			0x00100000
 #define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT			20
 #define GEN6_INST_DST_SUBREG_ALIGN16__SHR			4
 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK			0x03f00000
 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT			20
 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR			4
+#define GEN8_INST_DST_ADDR_IMM_ALIGN16__MASK			0x01f00000
+#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHIFT			20
+#define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR			4
 #define GEN6_INST_DST_WRITEMASK__MASK				0x000f0000
 #define GEN6_INST_DST_WRITEMASK__SHIFT				16
 #define GEN7_INST_NIBCTRL					(0x1 << 15)
@@ -284,10 +303,37 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INST_DST_TYPE__SHIFT				2
 #define GEN6_INST_DST_FILE__MASK				0x00000003
 #define GEN6_INST_DST_FILE__SHIFT				0
+#define GEN8_INST_DST_ADDR_IMM_BIT9__MASK			0x00008000
+#define GEN8_INST_DST_ADDR_IMM_BIT9__SHIFT			15
+#define GEN8_INST_DST_ADDR_IMM_BIT9__SHR			9
+#define GEN8_INST_SRC0_TYPE__MASK				0x00007800
+#define GEN8_INST_SRC0_TYPE__SHIFT				11
+#define GEN8_INST_SRC0_FILE__MASK				0x00000600
+#define GEN8_INST_SRC0_FILE__SHIFT				9
+#define GEN8_INST_DST_TYPE__MASK				0x000001e0
+#define GEN8_INST_DST_TYPE__SHIFT				5
+#define GEN8_INST_DST_FILE__MASK				0x00000018
+#define GEN8_INST_DST_FILE__SHIFT				3
+#define GEN8_INST_MASKCTRL__MASK				0x00000004
+#define GEN8_INST_MASKCTRL__SHIFT				2
+#define GEN8_INST_FLAG_REG__MASK				0x00000002
+#define GEN8_INST_FLAG_REG__SHIFT				1
+#define GEN8_INST_FLAG_SUBREG__MASK				0x00000001
+#define GEN8_INST_FLAG_SUBREG__SHIFT				0
 #define GEN7_INST_FLAG_REG__MASK				0x04000000
 #define GEN7_INST_FLAG_REG__SHIFT				26
 #define GEN6_INST_FLAG_SUBREG__MASK				0x02000000
 #define GEN6_INST_FLAG_SUBREG__SHIFT				25
+#define GEN8_INST_SRC0_ADDR_IMM_BIT9__MASK			0x80000000
+#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHIFT			31
+#define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR			9
+#define GEN8_INST_SRC1_TYPE__MASK				0x78000000
+#define GEN8_INST_SRC1_TYPE__SHIFT				27
+#define GEN8_INST_SRC1_FILE__MASK				0x06000000
+#define GEN8_INST_SRC1_FILE__SHIFT				25
+#define GEN8_INST_SRC1_ADDR_IMM_BIT9__MASK			0x02000000
+#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHIFT			25
+#define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR			9
 #define GEN6_INST_SRC_VERTSTRIDE__MASK				0x01e00000
 #define GEN6_INST_SRC_VERTSTRIDE__SHIFT				21
 #define GEN6_INST_SRC_WIDTH__MASK				0x001c0000
@@ -310,12 +356,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INST_SRC_ADDR_SUBREG__SHIFT			10
 #define GEN6_INST_SRC_ADDR_IMM__MASK				0x000003ff
 #define GEN6_INST_SRC_ADDR_IMM__SHIFT				0
+#define GEN8_INST_SRC_ADDR_SUBREG__MASK				0x00001e00
+#define GEN8_INST_SRC_ADDR_SUBREG__SHIFT			9
+#define GEN8_INST_SRC_ADDR_IMM__MASK				0x000001ff
+#define GEN8_INST_SRC_ADDR_IMM__SHIFT				0
 #define GEN6_INST_SRC_SUBREG_ALIGN16__MASK			0x00000010
 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT			4
 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHR			4
 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK			0x000003f0
 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT			4
 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR			4
+#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__MASK			0x000001f0
+#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHIFT			4
+#define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR			4
 #define GEN6_INST_SRC_SWIZZLE_Y__MASK				0x0000000c
 #define GEN6_INST_SRC_SWIZZLE_Y__SHIFT				2
 #define GEN6_INST_SRC_SWIZZLE_X__MASK				0x00000003
@@ -343,6 +396,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_3SRC_FLAG_SUBREG__MASK				0x00000002
 #define GEN6_3SRC_FLAG_SUBREG__SHIFT				1
 #define GEN6_3SRC_DST_FILE_MRF					(0x1 << 0)
+#define GEN8_3SRC_DST_TYPE__MASK				0x0001c000
+#define GEN8_3SRC_DST_TYPE__SHIFT				14
+#define GEN8_3SRC_SRC_TYPE__MASK				0x00003800
+#define GEN8_3SRC_SRC_TYPE__SHIFT				11
+#define GEN8_3SRC_SRC2_NEGATE					(0x1 << 10)
+#define GEN8_3SRC_SRC2_ABSOLUTE					(0x1 << 9)
+#define GEN8_3SRC_SRC1_NEGATE					(0x1 << 8)
+#define GEN8_3SRC_SRC1_ABSOLUTE					(0x1 << 7)
+#define GEN8_3SRC_SRC0_NEGATE					(0x1 << 6)
+#define GEN8_3SRC_SRC0_ABSOLUTE					(0x1 << 5)
+#define GEN8_3SRC_MASKCTRL__MASK				0x00000004
+#define GEN8_3SRC_MASKCTRL__SHIFT				2
+#define GEN8_3SRC_FLAG_REG__MASK				0x00000002
+#define GEN8_3SRC_FLAG_REG__SHIFT				1
+#define GEN8_3SRC_FLAG_SUBREG__MASK				0x00000001
+#define GEN8_3SRC_FLAG_SUBREG__SHIFT				0
 #define GEN6_3SRC_SRC_REG__MASK					0x000ff000
 #define GEN6_3SRC_SRC_REG__SHIFT				12
 #define GEN6_3SRC_SRC_SUBREG__MASK				0x00000e00
@@ -382,6 +451,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_COMPACT_DEBUGCTRL					(0x1 << 7)
 #define GEN6_COMPACT_OPCODE__MASK				0x0000007f
 #define GEN6_COMPACT_OPCODE__SHIFT				0
+#define GEN8_COMPACT_3SRC_SRC2_REG__MASK		0xfe00000000000000ULL
+#define GEN8_COMPACT_3SRC_SRC2_REG__SHIFT			57
+#define GEN8_COMPACT_3SRC_SRC2_REG__SHR				1
+#define GEN8_COMPACT_3SRC_SRC1_REG__MASK		0x01fc000000000000ULL
+#define GEN8_COMPACT_3SRC_SRC1_REG__SHIFT			50
+#define GEN8_COMPACT_3SRC_SRC1_REG__SHR				1
+#define GEN8_COMPACT_3SRC_SRC0_REG__MASK		0x0003f80000000000ULL
+#define GEN8_COMPACT_3SRC_SRC0_REG__SHIFT			43
+#define GEN8_COMPACT_3SRC_SRC0_REG__SHR				1
+#define GEN8_COMPACT_3SRC_SRC2_SUBREG__MASK		0x0000070000000000ULL
+#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHIFT			40
+#define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHR			2
+#define GEN8_COMPACT_3SRC_SRC1_SUBREG__MASK		0x000000e000000000ULL
+#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHIFT			37
+#define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHR			2
+#define GEN8_COMPACT_3SRC_SRC0_SUBREG__MASK		0x0000001c00000000ULL
+#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHIFT			34
+#define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHR			2
+#define GEN8_COMPACT_3SRC_SRC2_REPCTRL				(0x1ULL << 33)
+#define GEN8_COMPACT_3SRC_SRC1_REPCTRL				(0x1ULL << 32)
+#define GEN8_COMPACT_3SRC_SATURATE				(0x1 << 31)
+#define GEN8_COMPACT_3SRC_DEBUGCTRL				(0x1 << 30)
+#define GEN8_COMPACT_3SRC_CMPTCTRL				(0x1 << 29)
+#define GEN8_COMPACT_3SRC_SRC0_REPCTRL				(0x1 << 28)
+#define GEN8_COMPACT_3SRC_DST_REG__MASK				0x0007f000
+#define GEN8_COMPACT_3SRC_DST_REG__SHIFT			12
+#define GEN8_COMPACT_3SRC_SOURCE_INDEX__MASK			0x00000c00
+#define GEN8_COMPACT_3SRC_SOURCE_INDEX__SHIFT			10
+#define GEN8_COMPACT_3SRC_CONTROL_INDEX__MASK			0x00000300
+#define GEN8_COMPACT_3SRC_CONTROL_INDEX__SHIFT			8
+#define GEN8_COMPACT_3SRC_OPCODE__MASK				0x0000007f
+#define GEN8_COMPACT_3SRC_OPCODE__SHIFT				0
 
 
 
@@ -400,4 +501,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
+
+
 #endif /* GEN_EU_ISA_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
index c82fd346a88..43933f4850b 100644
--- a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -40,7 +40,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MSG_URB_READ_OWORD					0x3
 #define GEN7_MSG_URB_ATOMIC_MOV					0x4
 #define GEN7_MSG_URB_ATOMIC_INC					0x5
+#define GEN8_MSG_URB_SIMD8_WRITE				0x7
+#define GEN7_MSG_PI_SIMD8					0x0
+#define GEN7_MSG_PI_SIMD16					0x1
+#define GEN7_MSG_PI_EVAL_SNAPPED_IMM				0x0
+#define GEN7_MSG_PI_EVAL_SINDEX					0x1
+#define GEN7_MSG_PI_EVAL_CENTROID				0x2
+#define GEN7_MSG_PI_EVAL_SNAPPED				0x3
 #define GEN6_MSG_SAMPLER_SIMD4X2				0x0
+#define GEN9_MSG_SAMPLER_SIMD8D					0x0
 #define GEN6_MSG_SAMPLER_SIMD8					0x1
 #define GEN6_MSG_SAMPLER_SIMD16					0x2
 #define GEN6_MSG_SAMPLER_SIMD32_64				0x3
@@ -62,7 +70,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MSG_SAMPLER_SAMPLE_D_C				0x14
 #define GEN7_MSG_SAMPLER_SAMPLE_LZ				0x18
 #define GEN7_MSG_SAMPLER_SAMPLE_C_LC				0x19
-#define GEN7_MSG_SAMPLER_SAMPLE_LD_LZ				0x1a
+#define GEN7_MSG_SAMPLER_LD_LZ					0x1a
 #define GEN7_MSG_SAMPLER_LD_MCS					0x1d
 #define GEN7_MSG_SAMPLER_LD2DMS					0x1e
 #define GEN7_MSG_SAMPLER_LD2DSS					0x1f
@@ -80,7 +88,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MSG_DP_RT_WRITE					0xc
 #define GEN6_MSG_DP_SVB_WRITE					0xd
 #define GEN6_MSG_DP_RT_UNORM_WRITE				0xe
-#define GEN7_MSG_DP_SAMPLER_OWORD_BLOCK_READ			0x1
+#define GEN7_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ		0x1
 #define GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ			0x4
 #define GEN7_MSG_DP_RC_MEDIA_BLOCK_READ				0x4
 #define GEN7_MSG_DP_RC_TYPED_SURFACE_READ			0x5
@@ -139,6 +147,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP			0xb
 #define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2		0xc
 #define GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE			0xd
+#define GEN7_MSG_DP_AOP_CMPWR8B					0x0
+#define GEN7_MSG_DP_AOP_AND					0x1
+#define GEN7_MSG_DP_AOP_OR					0x2
+#define GEN7_MSG_DP_AOP_XOR					0x3
+#define GEN7_MSG_DP_AOP_MOV					0x4
+#define GEN7_MSG_DP_AOP_INC					0x5
+#define GEN7_MSG_DP_AOP_DEC					0x6
+#define GEN7_MSG_DP_AOP_ADD					0x7
+#define GEN7_MSG_DP_AOP_SUB					0x8
+#define GEN7_MSG_DP_AOP_REVSUB					0x9
+#define GEN7_MSG_DP_AOP_IMAX					0xa
+#define GEN7_MSG_DP_AOP_IMIN					0xb
+#define GEN7_MSG_DP_AOP_UMAX					0xc
+#define GEN7_MSG_DP_AOP_UMIN					0xd
+#define GEN7_MSG_DP_AOP_CMPWR					0xe
+#define GEN7_MSG_DP_AOP_PREDEC					0xf
 #define GEN6_MSG_EOT						(0x1 << 31)
 #define GEN6_MSG_MLEN__MASK					0x1e000000
 #define GEN6_MSG_MLEN__SHIFT					25
@@ -162,6 +186,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MSG_URB_GLOBAL_OFFSET__SHIFT			3
 #define GEN7_MSG_URB_OP__MASK					0x00000007
 #define GEN7_MSG_URB_OP__SHIFT					0
+#define GEN8_MSG_URB_PER_SLOT_OFFSET				(0x1 << 17)
+#define GEN8_MSG_URB_INTERLEAVED				(0x1 << 15)
+#define GEN8_MSG_URB_GLOBAL_OFFSET__MASK			0x00007ff0
+#define GEN8_MSG_URB_GLOBAL_OFFSET__SHIFT			4
+#define GEN8_MSG_URB_OP__MASK					0x0000000f
+#define GEN8_MSG_URB_OP__SHIFT					0
+#define GEN7_MSG_PI_SIMD__MASK					0x00010000
+#define GEN7_MSG_PI_SIMD__SHIFT					16
+#define GEN7_MSG_PI_LINEAR_INTERP				(0x1 << 14)
+#define GEN7_MSG_PI_OP__MASK					0x00003000
+#define GEN7_MSG_PI_OP__SHIFT					12
+#define GEN7_MSG_PI_SLOTGRP_HI					(0x1 << 11)
+#define GEN7_MSG_PI_OFFSET_Y__MASK				0x000000f0
+#define GEN7_MSG_PI_OFFSET_Y__SHIFT				4
+#define GEN7_MSG_PI_OFFSET_X__MASK				0x0000000f
+#define GEN7_MSG_PI_OFFSET_X__SHIFT				0
+#define GEN7_MSG_PI_SAMPLE_INDEX__MASK				0x000000f0
+#define GEN7_MSG_PI_SAMPLE_INDEX__SHIFT				4
 #define GEN6_MSG_SAMPLER_SIMD__MASK				0x00030000
 #define GEN6_MSG_SAMPLER_SIMD__SHIFT				16
 #define GEN6_MSG_SAMPLER_OP__MASK				0x0000f000
@@ -199,17 +241,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_2		(0x2 << 8)
 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_4		(0x3 << 8)
 #define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_8		(0x4 << 8)
+#define GEN7_MSG_DP_OWORD_DUAL_BLOCK_READ_INVALIDATE		(0x1 << 13)
 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__MASK			0x00000300
 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__SHIFT		8
 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1			(0x0 << 8)
 #define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_4			(0x2 << 8)
 #define GEN7_MSG_DP_DWORD_SCATTERED_READ_INVALIDATE		(0x1 << 13)
-#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__MASK			0x00000300
-#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__SHIFT			8
-#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_8			(0x2 << 8)
-#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_16			(0x3 << 8)
+#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__MASK		0x00000300
+#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE__SHIFT		8
+#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_8		(0x2 << 8)
+#define GEN6_MSG_DP_DWORD_SCATTERED_BLOCK_SIZE_16		(0x3 << 8)
+#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__MASK		0x00000600
+#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE__SHIFT		9
+#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_1			(0x0 << 9)
+#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_2			(0x1 << 9)
+#define GEN6_MSG_DP_BYTE_SCATTERED_DATA_SIZE_4			(0x2 << 9)
+#define GEN6_MSG_DP_BYTE_SCATTERED_MODE__MASK			0x00000100
+#define GEN6_MSG_DP_BYTE_SCATTERED_MODE__SHIFT			8
+#define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD8			(0x0 << 8)
+#define GEN6_MSG_DP_BYTE_SCATTERED_MODE_SIMD16			(0x1 << 8)
 #define GEN6_MSG_DP_RT_LAST					(0x1 << 12)
-#define GEN6_MSG_DP_SLOTGRP_HI					(0x1 << 11)
+#define GEN6_MSG_DP_RT_SLOTGRP_HI				(0x1 << 11)
 #define GEN6_MSG_DP_RT_MODE__MASK				0x00000700
 #define GEN6_MSG_DP_RT_MODE__SHIFT				8
 #define GEN6_MSG_DP_RT_MODE_SIMD16				(0x0 << 8)
@@ -218,6 +270,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI			(0x3 << 8)
 #define GEN6_MSG_DP_RT_MODE_SIMD8_LO				(0x4 << 8)
 #define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR			(0x5 << 8)
+#define GEN7_MSG_DP_TYPED_SLOTGRP_HI				(0x1 << 13)
+#define GEN7_MSG_DP_TYPED_MASK__MASK				0x00000f00
+#define GEN7_MSG_DP_TYPED_MASK__SHIFT				8
 #define GEN7_MSG_DP_UNTYPED_MODE__MASK				0x00003000
 #define GEN7_MSG_DP_UNTYPED_MODE__SHIFT				12
 #define GEN7_MSG_DP_UNTYPED_MODE_SIMD4X2			(0x0 << 12)
@@ -225,10 +280,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MSG_DP_UNTYPED_MODE_SIMD8				(0x2 << 12)
 #define GEN7_MSG_DP_UNTYPED_MASK__MASK				0x00000f00
 #define GEN7_MSG_DP_UNTYPED_MASK__SHIFT				8
-#define GEN7_MSG_DP_UNTYPED_MASK_R				(0x0 << 8)
-#define GEN7_MSG_DP_UNTYPED_MASK_G				(0x1 << 8)
-#define GEN7_MSG_DP_UNTYPED_MASK_B				(0x2 << 8)
-#define GEN7_MSG_DP_UNTYPED_MASK_A				(0x4 << 8)
+#define GEN7_MSG_DP_ATOMIC_RETURN_DATA_ENABLE			(0x1 << 13)
+#define GEN7_MSG_DP_ATOMIC_TYPED_SLOTGRP_HI			(0x1 << 12)
+#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__MASK			0x00001000
+#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE__SHIFT			12
+#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD16			(0x0 << 12)
+#define GEN7_MSG_DP_ATOMIC_UNTYPED_MODE_SIMD8			(0x1 << 12)
+#define GEN7_MSG_DP_ATOMIC_OP__MASK				0x00000f00
+#define GEN7_MSG_DP_ATOMIC_OP__SHIFT				8
 #define GEN6_MSG_DP_SURFACE__MASK				0x000000ff
 #define GEN6_MSG_DP_SURFACE__SHIFT				0
 #define GEN6_MSG_TS_RESOURCE_SELECT__MASK			0x00000010
diff --git a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
index 219ddab2653..7995869a185 100644
--- a/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_mi.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -32,34 +32,131 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
 
 
+#define GEN75_MI_ALU_NOOP					0x0
+#define GEN75_MI_ALU_LOAD					0x80
+#define GEN75_MI_ALU_LOADINV					0x480
+#define GEN75_MI_ALU_LOAD0					0x81
+#define GEN75_MI_ALU_LOAD1					0x481
+#define GEN75_MI_ALU_ADD					0x100
+#define GEN75_MI_ALU_SUB					0x101
+#define GEN75_MI_ALU_AND					0x102
+#define GEN75_MI_ALU_OR						0x103
+#define GEN75_MI_ALU_XOR					0x104
+#define GEN75_MI_ALU_STORE					0x180
+#define GEN75_MI_ALU_STOREINV					0x580
+#define GEN75_MI_ALU_R0						0x0
+#define GEN75_MI_ALU_R1						0x1
+#define GEN75_MI_ALU_R2						0x2
+#define GEN75_MI_ALU_R3						0x3
+#define GEN75_MI_ALU_R4						0x4
+#define GEN75_MI_ALU_R5						0x5
+#define GEN75_MI_ALU_R6						0x6
+#define GEN75_MI_ALU_R7						0x7
+#define GEN75_MI_ALU_R8						0x8
+#define GEN75_MI_ALU_R9						0x9
+#define GEN75_MI_ALU_R10					0xa
+#define GEN75_MI_ALU_R11					0xb
+#define GEN75_MI_ALU_R12					0xc
+#define GEN75_MI_ALU_R13					0xd
+#define GEN75_MI_ALU_R14					0xe
+#define GEN75_MI_ALU_R15					0xf
+#define GEN75_MI_ALU_SRCA					0x20
+#define GEN75_MI_ALU_SRCB					0x21
+#define GEN75_MI_ALU_ACCU					0x31
+#define GEN75_MI_ALU_ZF						0x32
+#define GEN75_MI_ALU_CF						0x33
 #define GEN6_MI_TYPE__MASK					0xe0000000
 #define GEN6_MI_TYPE__SHIFT					29
 #define GEN6_MI_TYPE_MI						(0x0 << 29)
 #define GEN6_MI_OPCODE__MASK					0x1f800000
 #define GEN6_MI_OPCODE__SHIFT					23
 #define GEN6_MI_OPCODE_MI_NOOP					(0x0 << 23)
+#define GEN75_MI_OPCODE_MI_SET_PREDICATE			(0x1 << 23)
+#define GEN75_MI_OPCODE_MI_RS_CONTROL				(0x6 << 23)
+#define GEN75_MI_OPCODE_MI_URB_ATOMIC_ALLOC			(0x9 << 23)
 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END			(0xa << 23)
+#define GEN7_MI_OPCODE_MI_PREDICATE				(0xc << 23)
+#define GEN7_MI_OPCODE_MI_URB_CLEAR				(0x19 << 23)
+#define GEN75_MI_OPCODE_MI_MATH					(0x1a << 23)
 #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM			(0x20 << 23)
 #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM			(0x22 << 23)
 #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM			(0x24 << 23)
 #define GEN6_MI_OPCODE_MI_FLUSH_DW				(0x26 << 23)
 #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT			(0x28 << 23)
 #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM			(0x29 << 23)
+#define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG			(0x2a << 23)
+#define GEN75_MI_OPCODE_MI_LOAD_URB_MEM				(0x2c << 23)
+#define GEN75_MI_OPCODE_MI_STORE_URB_MEM			(0x2d << 23)
 #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START			(0x31 << 23)
 #define GEN6_MI_LENGTH__MASK					0x0000003f
 #define GEN6_MI_LENGTH__SHIFT					0
 #define GEN6_MI_NOOP__SIZE					1
 
+#define GEN75_MI_SET_PREDICATE__SIZE				1
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK		0x00000003
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__SHIFT		0
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ALWAYS		0x0
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_CLEAR		0x1
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_SET		0x2
+#define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_DISABLE		0x3
+
+#define GEN75_MI_RS_CONTROL__SIZE				1
+#define GEN75_MI_RS_CONTROL_DW0_ENABLE				(0x1 << 0)
+
+#define GEN75_MI_URB_ATOMIC_ALLOC__SIZE				1
+#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__MASK		0x000ff000
+#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__SHIFT		12
+#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__MASK		0x000001ff
+#define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__SHIFT		0
+
 #define GEN6_MI_BATCH_BUFFER_END__SIZE				1
 
-#define GEN6_MI_STORE_DATA_IMM__SIZE				5
+#define GEN7_MI_PREDICATE__SIZE					1
+#define GEN7_MI_PREDICATE_DW0_LOADOP__MASK			0x000000c0
+#define GEN7_MI_PREDICATE_DW0_LOADOP__SHIFT			6
+#define GEN7_MI_PREDICATE_DW0_LOADOP_KEEP			(0x0 << 6)
+#define GEN7_MI_PREDICATE_DW0_LOADOP_LOAD			(0x2 << 6)
+#define GEN7_MI_PREDICATE_DW0_LOADOP_LOADINV			(0x3 << 6)
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP__MASK			0x00000018
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP__SHIFT			3
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP_SET			(0x0 << 3)
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP_AND			(0x1 << 3)
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP_OR			(0x2 << 3)
+#define GEN7_MI_PREDICATE_DW0_COMBINEOP_XOR			(0x3 << 3)
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP__MASK			0x00000003
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP__SHIFT			0
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP_TRUE			0x0
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP_FALSE			0x1
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP_SRCS_EQUAL		0x2
+#define GEN7_MI_PREDICATE_DW0_COMPAREOP_DELTAS_EQUAL		0x3
+
+#define GEN7_MI_URB_CLEAR__SIZE					2
+
+#define GEN7_MI_URB_CLEAR_DW1_LENGTH__MASK			0x3fff0000
+#define GEN7_MI_URB_CLEAR_DW1_LENGTH__SHIFT			16
+#define GEN7_MI_URB_CLEAR_DW1_OFFSET__MASK			0x00007fff
+#define GEN7_MI_URB_CLEAR_DW1_OFFSET__SHIFT			0
+
+#define GEN75_MI_MATH__SIZE					65
+
+#define GEN75_MI_MATH_DW_OP__MASK				0xfff00000
+#define GEN75_MI_MATH_DW_OP__SHIFT				20
+#define GEN75_MI_MATH_DW_SRC1__MASK				0x000ffc00
+#define GEN75_MI_MATH_DW_SRC1__SHIFT				10
+#define GEN75_MI_MATH_DW_SRC2__MASK				0x000007ff
+#define GEN75_MI_MATH_DW_SRC2__SHIFT				0
+
+#define GEN6_MI_STORE_DATA_IMM__SIZE				6
 #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT			(0x1 << 22)
 
+
 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK			0xfffffffc
 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT			2
 #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR			2
 
 
+
+
 #define GEN6_MI_LOAD_REGISTER_IMM__SIZE				3
 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK	0x00000f00
 #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT	8
@@ -69,7 +166,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR			2
 
 
-#define GEN6_MI_STORE_REGISTER_MEM__SIZE			3
+#define GEN6_MI_STORE_REGISTER_MEM__SIZE			4
 #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT			(0x1 << 22)
 #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE	(0x1 << 21)
 
@@ -81,18 +178,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT		2
 #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR		2
 
+
 #define GEN6_MI_FLUSH_DW__SIZE					4
 
+
+
+
 #define GEN6_MI_REPORT_PERF_COUNT__SIZE				3
 
+#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE		(0x1 << 4)
+#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT			(0x1 << 0)
 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK		0xffffffc0
 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT		6
 #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR			6
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE		(0x1 << 4)
-#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT			(0x1 << 0)
 
 
-#define GEN7_MI_LOAD_REGISTER_MEM__SIZE				3
+#define GEN7_MI_LOAD_REGISTER_MEM__SIZE				4
 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT			(0x1 << 22)
 #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE		(0x1 << 21)
 
@@ -104,7 +205,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT		2
 #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR			2
 
-#define GEN6_MI_BATCH_BUFFER_START__SIZE			2
+
+#define GEN75_MI_LOAD_REGISTER_REG__SIZE			3
+
+#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__MASK		0x007ffffc
+#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHIFT		2
+#define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHR		2
+
+#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__MASK		0x007ffffc
+#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT		2
+#define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR		2
+
+#define GEN75_MI_LOAD_URB_MEM__SIZE				4
+
+#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK			0x00007ffc
+#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHIFT			2
+#define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHR			2
+
+#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__MASK			0xffffffc0
+#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHIFT			6
+#define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHR			6
+
+
+#define GEN75_MI_STORE_URB_MEM__SIZE				4
+
+#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__MASK			0x00007ffc
+#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHIFT			2
+#define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHR			2
+
+#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__MASK			0xffffffc0
+#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHIFT			6
+#define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR			6
+
+
+#define GEN6_MI_BATCH_BUFFER_START__SIZE			3
 #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL		(0x1 << 22)
 #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE	(0x1 << 16)
 #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE	(0x1 << 15)
@@ -117,4 +251,5 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR		2
 
 
+
 #endif /* GEN_MI_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
index 60867600304..2bdd72b29bc 100644
--- a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -59,6 +59,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN6_REG_TIMESTAMP					0x2358
 
+#define GEN6_REG_OACONTROL					0x2360
+#define GEN6_REG_OACONTROL_COUNTER_SELECT__MASK			0x0000001c
+#define GEN6_REG_OACONTROL_COUNTER_SELECT__SHIFT		2
+#define GEN6_REG_OACONTROL_PERFORMANCE_COUNTER_ENABLE		(0x1 << 0)
+
+
+#define GEN7_REG_MI_PREDICATE_SRC0				0x2400
+
+#define GEN7_REG_MI_PREDICATE_SRC1				0x2408
+
+#define GEN7_REG_MI_PREDICATE_DATA				0x2410
+
+#define GEN7_REG_MI_PREDICATE_RESULT				0x2418
+
+#define GEN75_REG_MI_PREDICATE_RESULT_1				0x241c
+
+#define GEN75_REG_MI_PREDICATE_RESULT_2				0x2214
 
 #define GEN7_REG_3DPRIM_END_OFFSET				0x2420
 
@@ -72,10 +89,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN7_REG_3DPRIM_BASE_VERTEX				0x2440
 
-#define GEN6_REG_OACONTROL					0x2360
-#define GEN6_REG_OACONTROL_COUNTER_SELECT__MASK			0x0000001c
-#define GEN6_REG_OACONTROL_COUNTER_SELECT__SHIFT		2
-#define GEN6_REG_OACONTROL_PERFORMANCE_COUNTER_ENABLE		(0x1 << 0)
+#define GEN75_REG_CS_GPR(i0)					(0x2600 + 0x8*(i0))
+#define GEN75_REG_CS_GPR__ESIZE					0x8
+#define GEN75_REG_CS_GPR__LEN					0x10
 
 
 #define GEN6_REG_SO_PRIM_STORAGE_NEEDED				0x2280
@@ -96,6 +112,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_REG_SO_WRITE_OFFSET__LEN				0x4
 
 
+#define GEN7_REG_CACHE_MODE_0					0x7000
+#define GEN7_REG_CACHE_MODE_0_HIZ_RAW_STALL_OPT_DISABLE		(0x1 << 2)
+
+#define GEN7_REG_CACHE_MODE_1					0x7004
+#define GEN8_REG_CACHE_MODE_1_HIZ_NP_EARLY_Z_FAILS_DISABLE	(0x1 << 13)
+#define GEN8_REG_CACHE_MODE_1_HIZ_NP_PMA_FIX_ENABLE		(0x1 << 11)
+
+
+#define GEN8_REG_L3CNTLREG					0x7034
+
+
 #define GEN7_REG_L3SQCREG1					0xb010
 #define GEN7_REG_L3SQCREG1_CON4DCUNC				(0x1 << 24)
 #define GEN7_REG_L3SQCREG1_SQGHPCI__MASK			0x00ff0000
diff --git a/src/gallium/drivers/ilo/genhw/gen_render.xml.h b/src/gallium/drivers/ilo/genhw/gen_render.xml.h
index 9009437e40f..8a535d8e9f2 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -64,6 +64,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER			(0xa << 16)
 #define GEN75_RENDER_OPCODE_3DSTATE_VF				(0xc << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS	(0xd << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_MULTISAMPLE			(0xd << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS		(0xe << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS	(0xf << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_VS				(0x10 << 16)
@@ -101,6 +102,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_RENDER_OPCODE_3DSTATE_URB_HS			(0x31 << 16)
 #define GEN7_RENDER_OPCODE_3DSTATE_URB_DS			(0x32 << 16)
 #define GEN7_RENDER_OPCODE_3DSTATE_URB_GS			(0x33 << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_VF_INSTANCING		(0x49 << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_VF_SGVS			(0x4a << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_VF_TOPOLOGY			(0x4b << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_WM_CHROMAKEY			(0x4c << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_PS_BLEND			(0x4d << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_WM_DEPTH_STENCIL		(0x4e << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_PS_EXTRA			(0x4f << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_RASTER			(0x50 << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_SBE_SWIZ			(0x51 << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_WM_HZ_OP			(0x52 << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE		(0x100 << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER			(0x105 << 16)
 #define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET		(0x106 << 16)
@@ -119,6 +130,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS	(0x116 << 16)
 #define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST			(0x117 << 16)
 #define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER			(0x118 << 16)
+#define GEN8_RENDER_OPCODE_3DSTATE_SAMPLE_PATTERN		(0x11c << 16)
 #define GEN6_RENDER_OPCODE_PIPE_CONTROL				(0x200 << 16)
 #define GEN6_RENDER_OPCODE_3DPRIMITIVE				(0x300 << 16)
 #define GEN6_RENDER_LENGTH__MASK				0x000000ff
@@ -142,18 +154,39 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MOCS_L3__SHIFT					0
 #define GEN7_MOCS_L3_UC						0x0
 #define GEN7_MOCS_L3_ON						0x1
-#define GEN6_BASE_ADDR__MASK					0xfffff000
-#define GEN6_BASE_ADDR__SHIFT					12
-#define GEN6_BASE_ADDR__SHR					12
-#define GEN6_BASE_ADDR_MOCS__MASK				0x00000f00
-#define GEN6_BASE_ADDR_MOCS__SHIFT				8
-#define GEN6_BASE_ADDR_MODIFIED					(0x1 << 0)
-#define GEN6_STATE_BASE_ADDRESS__SIZE				10
+#define GEN8_MOCS_LLC__MASK					0x00000060
+#define GEN8_MOCS_LLC__SHIFT					5
+#define GEN8_MOCS_LLC_PTE					(0x0 << 5)
+#define GEN8_MOCS_LLC_UC					(0x1 << 5)
+#define GEN8_MOCS_LLC_WT					(0x2 << 5)
+#define GEN8_MOCS_LLC_WB					(0x3 << 5)
+#define GEN8_MOCS_L3__MASK					0x00000018
+#define GEN8_MOCS_L3__SHIFT					3
+#define GEN8_MOCS_L3_ELLC_ONLY					(0x0 << 3)
+#define GEN8_MOCS_L3_LLC_ONLY					(0x1 << 3)
+#define GEN8_MOCS_L3_LLC					(0x2 << 3)
+#define GEN8_MOCS_L3_ON						(0x3 << 3)
+#define GEN9_MOCS__MASK						0x0000007f
+#define GEN9_MOCS__SHIFT					0
+#define GEN9_MOCS_WT						0x5
+#define GEN9_MOCS_WB						0x9
+#define GEN6_SBA_ADDR__MASK					0xfffff000
+#define GEN6_SBA_ADDR__SHIFT					12
+#define GEN6_SBA_ADDR__SHR					12
+#define GEN6_SBA_MOCS__MASK					0x00000f00
+#define GEN6_SBA_MOCS__SHIFT					8
+#define GEN8_SBA_MOCS__MASK					0x000007f0
+#define GEN8_SBA_MOCS__SHIFT					4
+#define GEN6_SBA_ADDR_MODIFIED					(0x1 << 0)
+#define GEN6_BINDING_TABLE_ADDR__MASK				0x0000ffe0
+#define GEN6_BINDING_TABLE_ADDR__SHIFT				5
+#define GEN6_BINDING_TABLE_ADDR__SHR				5
+#define GEN6_STATE_BASE_ADDRESS__SIZE				19
 
 
-#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__MASK		0x000000f0
-#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__SHIFT	4
-#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU	(0x1 << 3)
+#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__MASK		0x000000f0
+#define GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT		4
+#define GEN6_SBA_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU		(0x1 << 3)
 
 
 
@@ -163,13 +196,36 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
-#define GEN6_STATE_SIP__SIZE					2
+
+
+
+
+#define GEN8_SBA_DW3_STATELESS_MOCS__MASK			0x007f0000
+#define GEN8_SBA_DW3_STATELESS_MOCS__SHIFT			16
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#define GEN6_STATE_SIP__SIZE					3
 
 
 #define GEN6_SIP_DW1_KERNEL_ADDR__MASK				0xfffffff0
 #define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT				4
 #define GEN6_SIP_DW1_KERNEL_ADDR__SHR				4
 
+
 #define GEN6_PIPELINE_SELECT__SIZE				1
 
 #define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK			0x00000003
@@ -177,6 +233,62 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_PIPELINE_SELECT_DW0_SELECT_3D			0x0
 #define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA			0x1
 #define GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU			0x2
+#define GEN9_PIPELINE_SELECT_DW0_SELECT__MASK			0x00000700
+#define GEN9_PIPELINE_SELECT_DW0_SELECT__SHIFT			8
+#define GEN9_PIPELINE_SELECT_DW0_SELECT_3D			(0x3 << 8)
+
+#define GEN6_PIPE_CONTROL__SIZE					6
+
+
+#define GEN7_PIPE_CONTROL_USE_GGTT				(0x1 << 24)
+#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK			0x00800000
+#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT			23
+#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE			(0x0 << 23)
+#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM				(0x1 << 23)
+#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE		(0x1 << 22)
+#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX			(0x1 << 21)
+#define GEN6_PIPE_CONTROL_CS_STALL				(0x1 << 20)
+#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET		(0x1 << 19)
+#define GEN6_PIPE_CONTROL_TLB_INVALIDATE			(0x1 << 18)
+#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE			(0x1 << 17)
+#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR		(0x1 << 16)
+#define GEN6_PIPE_CONTROL_WRITE__MASK				0x0000c000
+#define GEN6_PIPE_CONTROL_WRITE__SHIFT				14
+#define GEN6_PIPE_CONTROL_WRITE_NONE				(0x0 << 14)
+#define GEN6_PIPE_CONTROL_WRITE_IMM				(0x1 << 14)
+#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT			(0x2 << 14)
+#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP			(0x3 << 14)
+#define GEN6_PIPE_CONTROL_DEPTH_STALL				(0x1 << 13)
+#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH			(0x1 << 12)
+#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE		(0x1 << 11)
+#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(0x1 << 10)
+#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE	(0x1 << 9)
+#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE				(0x1 << 8)
+#define GEN7_PIPE_CONTROL_WRITE_IMM_FLUSH			(0x1 << 7)
+#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK		0x00000040
+#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT	6
+#define GEN7_PIPE_CONTROL_DC_FLUSH				(0x1 << 5)
+#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE			(0x1 << 4)
+#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE		(0x1 << 3)
+#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE		(0x1 << 2)
+#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL		(0x1 << 1)
+#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH			(0x1 << 0)
+
+#define GEN6_PIPE_CONTROL_DW2_USE_GGTT				(0x1 << 2)
+#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK			0xfffffff8
+#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT			3
+#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR				3
+
+#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK			0xfffffffc
+#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT			2
+#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR				2
+
+#define GEN8_PIPE_CONTROL_DW2_ADDR__MASK			0xfffffffc
+#define GEN8_PIPE_CONTROL_DW2_ADDR__SHIFT			2
+#define GEN8_PIPE_CONTROL_DW2_ADDR__SHR				2
+
+
+
 
 
 #endif /* GEN_RENDER_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
index 2ddc0e56a29..9de3df641c7 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -94,9 +94,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_ALIGNMENT_CC_VIEWPORT				0x20
 #define GEN6_ALIGNMENT_SCISSOR_RECT				0x20
 #define GEN6_ALIGNMENT_BINDING_TABLE_STATE			0x20
-#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR			0x20
+#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE		0x20
+#define GEN8_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE		0x40
 #define GEN6_ALIGNMENT_SAMPLER_STATE				0x20
 #define GEN6_ALIGNMENT_SURFACE_STATE				0x20
+#define GEN8_ALIGNMENT_SURFACE_STATE				0x40
 #define GEN6_VFCOMP_NOSTORE					0x0
 #define GEN6_VFCOMP_STORE_SRC					0x1
 #define GEN6_VFCOMP_STORE_0					0x2
@@ -115,6 +117,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_INTERP_PERSPECTIVE_SAMPLE				(0x1 << 2)
 #define GEN6_INTERP_PERSPECTIVE_CENTROID			(0x1 << 1)
 #define GEN6_INTERP_PERSPECTIVE_PIXEL				(0x1 << 0)
+#define GEN6_PS_DISPATCH_32					(0x1 << 2)
+#define GEN6_PS_DISPATCH_16					(0x1 << 1)
+#define GEN6_PS_DISPATCH_8					(0x1 << 0)
 #define GEN6_THREADDISP_SPF					(0x1 << 31)
 #define GEN6_THREADDISP_VME					(0x1 << 30)
 #define GEN6_THREADDISP_SAMPLER_COUNT__MASK			0x38000000
@@ -148,39 +153,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE		4
 
-#define GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED			(0x1 << 12)
-#define GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED			(0x1 << 9)
-#define GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED			(0x1 << 8)
+#define GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED			(0x1 << 12)
+#define GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED			(0x1 << 9)
+#define GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED			(0x1 << 8)
 
-#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__MASK		0xffffffe0
-#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHIFT		5
-#define GEN6_PTR_BINDING_TABLE_DW1_VS_ADDR__SHR			5
 
-#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__MASK		0xffffffe0
-#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHIFT		5
-#define GEN6_PTR_BINDING_TABLE_DW2_GS_ADDR__SHR			5
 
-#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__MASK		0xffffffe0
-#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHIFT		5
-#define GEN6_PTR_BINDING_TABLE_DW3_PS_ADDR__SHR			5
 
 #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE		4
 
-#define GEN6_PTR_SAMPLER_DW0_PS_CHANGED				(0x1 << 12)
-#define GEN6_PTR_SAMPLER_DW0_GS_CHANGED				(0x1 << 9)
-#define GEN6_PTR_SAMPLER_DW0_VS_CHANGED				(0x1 << 8)
+#define GEN6_SAMPLER_PTR_DW0_PS_CHANGED				(0x1 << 12)
+#define GEN6_SAMPLER_PTR_DW0_GS_CHANGED				(0x1 << 9)
+#define GEN6_SAMPLER_PTR_DW0_VS_CHANGED				(0x1 << 8)
 
-#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__MASK			0xffffffe0
-#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHIFT			5
-#define GEN6_PTR_SAMPLER_DW1_VS_ADDR__SHR			5
+#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__MASK			0xffffffe0
+#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHIFT			5
+#define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHR			5
 
-#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__MASK			0xffffffe0
-#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHIFT			5
-#define GEN6_PTR_SAMPLER_DW2_GS_ADDR__SHR			5
+#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__MASK			0xffffffe0
+#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHIFT			5
+#define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHR			5
 
-#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__MASK			0xffffffe0
-#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHIFT			5
-#define GEN6_PTR_SAMPLER_DW3_PS_ADDR__SHR			5
+#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__MASK			0xffffffe0
+#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHIFT			5
+#define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHR			5
 
 #define GEN6_3DSTATE_URB__SIZE					3
 
@@ -200,42 +196,48 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_3DSTATE_URB_ANY__SIZE				2
 
 
-#define GEN7_URB_ANY_DW1_OFFSET__MASK				0x3e000000
-#define GEN7_URB_ANY_DW1_OFFSET__SHIFT				25
-#define GEN7_URB_ANY_DW1_ENTRY_SIZE__MASK			0x01ff0000
-#define GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT			16
-#define GEN7_URB_ANY_DW1_ENTRY_COUNT__MASK			0x0000ffff
-#define GEN7_URB_ANY_DW1_ENTRY_COUNT__SHIFT			0
+#define GEN7_URB_DW1_OFFSET__MASK				0x3e000000
+#define GEN7_URB_DW1_OFFSET__SHIFT				25
+#define GEN7_URB_DW1_ENTRY_SIZE__MASK				0x01ff0000
+#define GEN7_URB_DW1_ENTRY_SIZE__SHIFT				16
+#define GEN7_URB_DW1_ENTRY_COUNT__MASK				0x0000ffff
+#define GEN7_URB_DW1_ENTRY_COUNT__SHIFT				0
 
 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE		2
 
 
-#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__MASK			0x000f0000
-#define GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT			16
-#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__MASK			0x0000001f
-#define GEN7_PCB_ALLOC_ANY_DW1_SIZE__SHIFT			0
+#define GEN7_PCB_ALLOC_DW1_OFFSET__MASK				0x000f0000
+#define GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT			16
+#define GEN7_PCB_ALLOC_DW1_SIZE__MASK				0x0000001f
+#define GEN7_PCB_ALLOC_DW1_SIZE__SHIFT				0
 
-#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__MASK			0x001f0000
-#define GEN75_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT			16
-#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__MASK			0x0000003f
-#define GEN75_PCB_ALLOC_ANY_DW1_SIZE__SHIFT			0
+#define GEN75_PCB_ALLOC_DW1_OFFSET__MASK			0x001f0000
+#define GEN75_PCB_ALLOC_DW1_OFFSET__SHIFT			16
+#define GEN75_PCB_ALLOC_DW1_SIZE__MASK				0x0000003f
+#define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT				0
 
 #define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE			133
 
 
-#define GEN6_VB_STATE_DW0_INDEX__MASK				0xfc000000
-#define GEN6_VB_STATE_DW0_INDEX__SHIFT				26
-#define GEN6_VB_STATE_DW0_ACCESS__MASK				0x00100000
-#define GEN6_VB_STATE_DW0_ACCESS__SHIFT				20
-#define GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA			(0x0 << 20)
-#define GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA			(0x1 << 20)
-#define GEN6_VB_STATE_DW0_MOCS__MASK				0x000f0000
-#define GEN6_VB_STATE_DW0_MOCS__SHIFT				16
-#define GEN7_VB_STATE_DW0_ADDR_MODIFIED				(0x1 << 14)
-#define GEN6_VB_STATE_DW0_IS_NULL				(0x1 << 13)
-#define GEN6_VB_STATE_DW0_CACHE_INVALIDATE			(0x1 << 12)
-#define GEN6_VB_STATE_DW0_PITCH__MASK				0x00000fff
-#define GEN6_VB_STATE_DW0_PITCH__SHIFT				0
+
+#define GEN6_VB_DW0_INDEX__MASK					0xfc000000
+#define GEN6_VB_DW0_INDEX__SHIFT				26
+#define GEN8_VB_DW0_MOCS__MASK					0x007f0000
+#define GEN8_VB_DW0_MOCS__SHIFT					16
+#define GEN6_VB_DW0_ACCESS__MASK				0x00100000
+#define GEN6_VB_DW0_ACCESS__SHIFT				20
+#define GEN6_VB_DW0_ACCESS_VERTEXDATA				(0x0 << 20)
+#define GEN6_VB_DW0_ACCESS_INSTANCEDATA				(0x1 << 20)
+#define GEN6_VB_DW0_MOCS__MASK					0x000f0000
+#define GEN6_VB_DW0_MOCS__SHIFT					16
+#define GEN7_VB_DW0_ADDR_MODIFIED				(0x1 << 14)
+#define GEN6_VB_DW0_IS_NULL					(0x1 << 13)
+#define GEN6_VB_DW0_CACHE_INVALIDATE				(0x1 << 12)
+#define GEN6_VB_DW0_PITCH__MASK					0x00000fff
+#define GEN6_VB_DW0_PITCH__SHIFT				0
+
+
+
 
 
 
@@ -243,27 +245,28 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE			69
 
 
-#define GEN6_VE_STATE_DW0_VB_INDEX__MASK			0xfc000000
-#define GEN6_VE_STATE_DW0_VB_INDEX__SHIFT			26
-#define GEN6_VE_STATE_DW0_VALID					(0x1 << 25)
-#define GEN6_VE_STATE_DW0_FORMAT__MASK				0x01ff0000
-#define GEN6_VE_STATE_DW0_FORMAT__SHIFT				16
-#define GEN6_VE_STATE_DW0_EDGE_FLAG_ENABLE			(0x1 << 15)
-#define GEN6_VE_STATE_DW0_VB_OFFSET__MASK			0x000007ff
-#define GEN6_VE_STATE_DW0_VB_OFFSET__SHIFT			0
-#define GEN75_VE_STATE_DW0_VB_OFFSET__MASK			0x00000fff
-#define GEN75_VE_STATE_DW0_VB_OFFSET__SHIFT			0
-
-#define GEN6_VE_STATE_DW1_COMP0__MASK				0x70000000
-#define GEN6_VE_STATE_DW1_COMP0__SHIFT				28
-#define GEN6_VE_STATE_DW1_COMP1__MASK				0x07000000
-#define GEN6_VE_STATE_DW1_COMP1__SHIFT				24
-#define GEN6_VE_STATE_DW1_COMP2__MASK				0x00700000
-#define GEN6_VE_STATE_DW1_COMP2__SHIFT				20
-#define GEN6_VE_STATE_DW1_COMP3__MASK				0x00070000
-#define GEN6_VE_STATE_DW1_COMP3__SHIFT				16
-
-#define GEN6_3DSTATE_INDEX_BUFFER__SIZE				3
+
+#define GEN6_VE_DW0_VB_INDEX__MASK				0xfc000000
+#define GEN6_VE_DW0_VB_INDEX__SHIFT				26
+#define GEN6_VE_DW0_VALID					(0x1 << 25)
+#define GEN6_VE_DW0_FORMAT__MASK				0x01ff0000
+#define GEN6_VE_DW0_FORMAT__SHIFT				16
+#define GEN6_VE_DW0_EDGE_FLAG_ENABLE				(0x1 << 15)
+#define GEN6_VE_DW0_VB_OFFSET__MASK				0x000007ff
+#define GEN6_VE_DW0_VB_OFFSET__SHIFT				0
+#define GEN75_VE_DW0_VB_OFFSET__MASK				0x00000fff
+#define GEN75_VE_DW0_VB_OFFSET__SHIFT				0
+
+#define GEN6_VE_DW1_COMP0__MASK					0x70000000
+#define GEN6_VE_DW1_COMP0__SHIFT				28
+#define GEN6_VE_DW1_COMP1__MASK					0x07000000
+#define GEN6_VE_DW1_COMP1__SHIFT				24
+#define GEN6_VE_DW1_COMP2__MASK					0x00700000
+#define GEN6_VE_DW1_COMP2__SHIFT				20
+#define GEN6_VE_DW1_COMP3__MASK					0x00070000
+#define GEN6_VE_DW1_COMP3__SHIFT				16
+
+#define GEN6_3DSTATE_INDEX_BUFFER__SIZE				5
 
 #define GEN6_IB_DW0_MOCS__MASK					0x0000f000
 #define GEN6_IB_DW0_MOCS__SHIFT					12
@@ -276,62 +279,100 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
+
+
+#define GEN8_IB_DW1_FORMAT__MASK				0x00000300
+#define GEN8_IB_DW1_FORMAT__SHIFT				8
+#define GEN8_IB_DW1_FORMAT_BYTE					(0x0 << 8)
+#define GEN8_IB_DW1_FORMAT_WORD					(0x1 << 8)
+#define GEN8_IB_DW1_FORMAT_DWORD				(0x2 << 8)
+#define GEN8_IB_DW1_MOCS__MASK					0x0000007f
+#define GEN8_IB_DW1_MOCS__SHIFT					0
+
+
+
+
 #define GEN75_3DSTATE_VF__SIZE					2
 
 #define GEN75_VF_DW0_CUT_INDEX_ENABLE				(0x1 << 8)
 
 
+#define GEN8_3DSTATE_VF_INSTANCING__SIZE			3
+
+
+#define GEN8_INSTANCING_DW1_ENABLE				(0x1 << 8)
+#define GEN8_INSTANCING_DW1_VB_INDEX__MASK			0x0000003f
+#define GEN8_INSTANCING_DW1_VB_INDEX__SHIFT			0
+
+
+#define GEN8_3DSTATE_VF_SGVS__SIZE				2
+
+
+#define GEN8_SGVS_DW1_IID_ENABLE				(0x1 << 31)
+#define GEN8_SGVS_DW1_IID_VE_COMP__MASK				0x60000000
+#define GEN8_SGVS_DW1_IID_VE_COMP__SHIFT			29
+#define GEN8_SGVS_DW1_IID_VE_INDEX__MASK			0x003f0000
+#define GEN8_SGVS_DW1_IID_VE_INDEX__SHIFT			16
+#define GEN8_SGVS_DW1_VID_ENABLE				(0x1 << 15)
+#define GEN8_SGVS_DW1_VID_VE_COMP__MASK				0x00006000
+#define GEN8_SGVS_DW1_VID_VE_COMP__SHIFT			13
+#define GEN8_SGVS_DW1_VID_VE_INDEX__MASK			0x0000003f
+#define GEN8_SGVS_DW1_VID_VE_INDEX__SHIFT			0
+
+#define GEN8_3DSTATE_VF_TOPOLOGY__SIZE				2
+
+
+#define GEN8_TOPOLOGY_DW1_TYPE__MASK				0x0000003f
+#define GEN8_TOPOLOGY_DW1_TYPE__SHIFT				0
+
 #define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE		4
 
-#define GEN6_PTR_VP_DW0_CC_CHANGED				(0x1 << 12)
-#define GEN6_PTR_VP_DW0_SF_CHANGED				(0x1 << 11)
-#define GEN6_PTR_VP_DW0_CLIP_CHANGED				(0x1 << 10)
+#define GEN6_VP_PTR_DW0_CC_CHANGED				(0x1 << 12)
+#define GEN6_VP_PTR_DW0_SF_CHANGED				(0x1 << 11)
+#define GEN6_VP_PTR_DW0_CLIP_CHANGED				(0x1 << 10)
 
-#define GEN6_PTR_VP_DW1_CLIP_ADDR__MASK				0xffffffe0
-#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHIFT			5
-#define GEN6_PTR_VP_DW1_CLIP_ADDR__SHR				5
+#define GEN6_VP_PTR_DW1_CLIP_ADDR__MASK				0xffffffe0
+#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHIFT			5
+#define GEN6_VP_PTR_DW1_CLIP_ADDR__SHR				5
 
-#define GEN6_PTR_VP_DW2_SF_ADDR__MASK				0xffffffe0
-#define GEN6_PTR_VP_DW2_SF_ADDR__SHIFT				5
-#define GEN6_PTR_VP_DW2_SF_ADDR__SHR				5
+#define GEN6_VP_PTR_DW2_SF_ADDR__MASK				0xffffffe0
+#define GEN6_VP_PTR_DW2_SF_ADDR__SHIFT				5
+#define GEN6_VP_PTR_DW2_SF_ADDR__SHR				5
 
-#define GEN6_PTR_VP_DW3_CC_ADDR__MASK				0xffffffe0
-#define GEN6_PTR_VP_DW3_CC_ADDR__SHIFT				5
-#define GEN6_PTR_VP_DW3_CC_ADDR__SHR				5
+#define GEN6_VP_PTR_DW3_CC_ADDR__MASK				0xffffffe0
+#define GEN6_VP_PTR_DW3_CC_ADDR__SHIFT				5
+#define GEN6_VP_PTR_DW3_CC_ADDR__SHR				5
 
 #define GEN6_3DSTATE_CC_STATE_POINTERS__SIZE			4
 
 
-#define GEN6_PTR_CC_DW1_BLEND_CHANGED				(0x1 << 0)
-#define GEN6_PTR_CC_DW1_BLEND_ADDR__MASK			0xffffffc0
-#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHIFT			6
-#define GEN6_PTR_CC_DW1_BLEND_ADDR__SHR				6
+#define GEN6_CC_PTR_DW1_BLEND_CHANGED				(0x1 << 0)
+#define GEN6_CC_PTR_DW1_BLEND_ADDR__MASK			0xffffffc0
+#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHIFT			6
+#define GEN6_CC_PTR_DW1_BLEND_ADDR__SHR				6
 
-#define GEN6_PTR_CC_DW2_ZS_CHANGED				(0x1 << 0)
-#define GEN6_PTR_CC_DW2_ZS_ADDR__MASK				0xffffffc0
-#define GEN6_PTR_CC_DW2_ZS_ADDR__SHIFT				6
-#define GEN6_PTR_CC_DW2_ZS_ADDR__SHR				6
+#define GEN6_CC_PTR_DW2_ZS_CHANGED				(0x1 << 0)
+#define GEN6_CC_PTR_DW2_ZS_ADDR__MASK				0xffffffc0
+#define GEN6_CC_PTR_DW2_ZS_ADDR__SHIFT				6
+#define GEN6_CC_PTR_DW2_ZS_ADDR__SHR				6
 
-#define GEN6_PTR_CC_DW3_CC_CHANGED				(0x1 << 0)
-#define GEN6_PTR_CC_DW3_CC_ADDR__MASK				0xffffffc0
-#define GEN6_PTR_CC_DW3_CC_ADDR__SHIFT				6
-#define GEN6_PTR_CC_DW3_CC_ADDR__SHR				6
+#define GEN6_CC_PTR_DW3_CC_CHANGED				(0x1 << 0)
+#define GEN6_CC_PTR_DW3_CC_ADDR__MASK				0xffffffc0
+#define GEN6_CC_PTR_DW3_CC_ADDR__SHIFT				6
+#define GEN6_CC_PTR_DW3_CC_ADDR__SHR				6
 
 #define GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE		2
 
 
-#define GEN6_PTR_SCISSOR_DW1_ADDR__MASK				0xffffffe0
-#define GEN6_PTR_SCISSOR_DW1_ADDR__SHIFT			5
-#define GEN6_PTR_SCISSOR_DW1_ADDR__SHR				5
+#define GEN6_SCISSOR_PTR_DW1_ADDR__MASK				0xffffffe0
+#define GEN6_SCISSOR_PTR_DW1_ADDR__SHIFT			5
+#define GEN6_SCISSOR_PTR_DW1_ADDR__SHR				5
 
 #define GEN7_3DSTATE_POINTERS_ANY__SIZE				2
 
 
-#define GEN7_PTR_ANY_DW1_ADDR__MASK				0xffffffe0
-#define GEN7_PTR_ANY_DW1_ADDR__SHIFT				5
-#define GEN7_PTR_ANY_DW1_ADDR__SHR				5
 
-#define GEN6_3DSTATE_VS__SIZE					6
+#define GEN6_3DSTATE_VS__SIZE					9
 
 
 #define GEN6_VS_DW1_KERNEL_ADDR__MASK				0xffffffc0
@@ -355,7 +396,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_VS_DW5_CACHE_DISABLE				(0x1 << 1)
 #define GEN6_VS_DW5_VS_ENABLE					(0x1 << 0)
 
-#define GEN7_3DSTATE_HS__SIZE					7
+
+
+#define GEN8_VS_DW1_KERNEL_ADDR__MASK				0xffffffc0
+#define GEN8_VS_DW1_KERNEL_ADDR__SHIFT				6
+#define GEN8_VS_DW1_KERNEL_ADDR__SHR				6
+
+
+
+
+
+#define GEN8_VS_DW6_URB_GRF_START__MASK				0x01f00000
+#define GEN8_VS_DW6_URB_GRF_START__SHIFT			20
+#define GEN8_VS_DW6_URB_READ_LEN__MASK				0x0001f800
+#define GEN8_VS_DW6_URB_READ_LEN__SHIFT				11
+#define GEN8_VS_DW6_URB_READ_OFFSET__MASK			0x000003f0
+#define GEN8_VS_DW6_URB_READ_OFFSET__SHIFT			4
+
+#define GEN8_VS_DW7_MAX_THREADS__MASK				0xff800000
+#define GEN8_VS_DW7_MAX_THREADS__SHIFT				23
+#define GEN8_VS_DW7_STATISTICS					(0x1 << 10)
+#define GEN8_VS_DW7_SIMD8_ENABLE				(0x1 << 2)
+#define GEN8_VS_DW7_CACHE_DISABLE				(0x1 << 1)
+#define GEN8_VS_DW7_VS_ENABLE					(0x1 << 0)
+
+#define GEN8_VS_DW8_URB_WRITE_OFFSET__MASK			0x03e00000
+#define GEN8_VS_DW8_URB_WRITE_OFFSET__SHIFT			21
+#define GEN8_VS_DW8_URB_WRITE_LEN__MASK				0x001f0000
+#define GEN8_VS_DW8_URB_WRITE_LEN__SHIFT			16
+#define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK			0x0000ff00
+#define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT			8
+
+#define GEN7_3DSTATE_HS__SIZE					9
 
 
 #define GEN7_HS_DW1_DISPATCH_MAX_THREADS__MASK			0x0000007f
@@ -391,6 +463,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHR			6
 
+
+
+#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__MASK			0x000000ff
+#define GEN8_HS_DW1_DISPATCH_MAX_THREADS__SHIFT			0
+
+#define GEN8_HS_DW2_HS_ENABLE					(0x1 << 31)
+#define GEN8_HS_DW2_STATISTICS					(0x1 << 29)
+#define GEN8_HS_DW2_INSTANCE_COUNT__MASK			0x0000000f
+#define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT			0
+
+#define GEN8_HS_DW3_KERNEL_ADDR__MASK				0xffffffc0
+#define GEN8_HS_DW3_KERNEL_ADDR__SHIFT				6
+#define GEN8_HS_DW3_KERNEL_ADDR__SHR				6
+
+
+
+
+#define GEN8_HS_DW7_SPF						(0x1 << 27)
+#define GEN8_HS_DW7_VME						(0x1 << 26)
+#define GEN8_HS_DW7_ACCESS_UAV					(0x1 << 25)
+#define GEN8_HS_DW7_INCLUDE_VERTEX_HANDLES			(0x1 << 24)
+#define GEN8_HS_DW7_URB_GRF_START__MASK				0x00f80000
+#define GEN8_HS_DW7_URB_GRF_START__SHIFT			19
+#define GEN8_HS_DW7_URB_READ_LEN__MASK				0x0001f800
+#define GEN8_HS_DW7_URB_READ_LEN__SHIFT				11
+#define GEN8_HS_DW7_URB_READ_OFFSET__MASK			0x000003f0
+#define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT			4
+
+#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__MASK			0x00001fff
+#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHIFT			0
+#define GEN8_HS_DW8_URB_SEMAPHORE_ADDR__SHR			6
+
 #define GEN7_3DSTATE_TE__SIZE					4
 
 
@@ -418,7 +522,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
-#define GEN7_3DSTATE_DS__SIZE					6
+#define GEN7_3DSTATE_DS__SIZE					11
 
 
 #define GEN7_DS_DW1_KERNEL_ADDR__MASK				0xffffffc0
@@ -443,7 +547,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_DS_DW5_CACHE_DISABLE				(0x1 << 1)
 #define GEN7_DS_DW5_DS_ENABLE					(0x1 << 0)
 
-#define GEN6_3DSTATE_GS__SIZE					7
+
+
+#define GEN8_DS_DW1_KERNEL_ADDR__MASK				0xffffffc0
+#define GEN8_DS_DW1_KERNEL_ADDR__SHIFT				6
+#define GEN8_DS_DW1_KERNEL_ADDR__SHR				6
+
+
+
+
+
+#define GEN8_DS_DW6_URB_GRF_START__MASK				0x01f00000
+#define GEN8_DS_DW6_URB_GRF_START__SHIFT			20
+#define GEN8_DS_DW6_URB_READ_LEN__MASK				0x0003f800
+#define GEN8_DS_DW6_URB_READ_LEN__SHIFT				11
+#define GEN8_DS_DW6_URB_READ_OFFSET__MASK			0x000003f0
+#define GEN8_DS_DW6_URB_READ_OFFSET__SHIFT			4
+
+#define GEN8_DS_DW7_MAX_THREADS__MASK				0x3fe00000
+#define GEN8_DS_DW7_MAX_THREADS__SHIFT				21
+#define GEN8_DS_DW7_STATISTICS					(0x1 << 10)
+#define GEN8_DS_DW7_COMPUTE_W					(0x1 << 2)
+#define GEN8_DS_DW7_CACHE_DISABLE				(0x1 << 1)
+#define GEN8_DS_DW7_DS_ENABLE					(0x1 << 0)
+
+#define GEN8_DS_DW8_URB_WRITE_OFFSET__MASK			0x03e00000
+#define GEN8_DS_DW8_URB_WRITE_OFFSET__SHIFT			21
+#define GEN8_DS_DW8_URB_WRITE_LEN__MASK				0x001f0000
+#define GEN8_DS_DW8_URB_WRITE_LEN__SHIFT			16
+#define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK			0x0000ff00
+#define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT			8
+
+
+
+#define GEN6_3DSTATE_GS__SIZE					10
 
 
 #define GEN6_GS_DW1_KERNEL_ADDR__MASK				0xffffffc0
@@ -536,7 +673,73 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHR			6
 
-#define GEN7_3DSTATE_STREAMOUT__SIZE				3
+
+
+#define GEN8_GS_DW1_KERNEL_ADDR__MASK				0xffffffc0
+#define GEN8_GS_DW1_KERNEL_ADDR__SHIFT				6
+#define GEN8_GS_DW1_KERNEL_ADDR__SHR				6
+
+
+#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK			0x0000007f
+#define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT		0
+
+
+
+#define GEN8_GS_DW6_OUTPUT_SIZE__MASK				0x1f800000
+#define GEN8_GS_DW6_OUTPUT_SIZE__SHIFT				23
+#define GEN8_GS_DW6_OUTPUT_TOPO__MASK				0x007e0000
+#define GEN8_GS_DW6_OUTPUT_TOPO__SHIFT				17
+#define GEN8_GS_DW6_URB_READ_LEN__MASK				0x0001f800
+#define GEN8_GS_DW6_URB_READ_LEN__SHIFT				11
+#define GEN8_GS_DW6_INCLUDE_VERTEX_HANDLES			(0x1 << 10)
+#define GEN8_GS_DW6_URB_READ_OFFSET__MASK			0x000003f0
+#define GEN8_GS_DW6_URB_READ_OFFSET__SHIFT			4
+#define GEN8_GS_DW6_URB_GRF_START__MASK				0x0000000f
+#define GEN8_GS_DW6_URB_GRF_START__SHIFT			0
+
+#define GEN8_GS_DW7_MAX_THREADS__MASK				0xff000000
+#define GEN8_GS_DW7_MAX_THREADS__SHIFT				24
+#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__MASK		0x00f00000
+#define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__SHIFT		20
+#define GEN8_GS_DW7_INSTANCE_CONTROL__MASK			0x000f8000
+#define GEN8_GS_DW7_INSTANCE_CONTROL__SHIFT			15
+#define GEN8_GS_DW7_DEFAULT_STREAM_ID__MASK			0x00006000
+#define GEN8_GS_DW7_DEFAULT_STREAM_ID__SHIFT			13
+#define GEN8_GS_DW7_DISPATCH_MODE__MASK				0x00001800
+#define GEN8_GS_DW7_DISPATCH_MODE__SHIFT			11
+#define GEN8_GS_DW7_DISPATCH_MODE_SINGLE			(0x0 << 11)
+#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_INSTANCE			(0x1 << 11)
+#define GEN8_GS_DW7_DISPATCH_MODE_DUAL_OBJECT			(0x2 << 11)
+#define GEN8_GS_DW7_STATISTICS					(0x1 << 10)
+#define GEN8_GS_DW7_INVOCATION_INCR__MASK			0x000003e0
+#define GEN8_GS_DW7_INVOCATION_INCR__SHIFT			5
+#define GEN8_GS_DW7_INCLUDE_PRIMITIVE_ID			(0x1 << 4)
+#define GEN8_GS_DW7_HINT					(0x1 << 3)
+#define GEN8_GS_DW7_REORDER__MASK				0x00000004
+#define GEN8_GS_DW7_REORDER__SHIFT				2
+#define GEN8_GS_DW7_REORDER_LEADING				(0x0 << 2)
+#define GEN8_GS_DW7_REORDER_TRAILING				(0x1 << 2)
+#define GEN8_GS_DW7_DISCARD_ADJACENCY				(0x1 << 1)
+#define GEN8_GS_DW7_GS_ENABLE					(0x1 << 0)
+
+#define GEN8_GS_DW8_GSCTRL__MASK				0x80000000
+#define GEN8_GS_DW8_GSCTRL__SHIFT				31
+#define GEN8_GS_DW8_GSCTRL_CUT					(0x0 << 31)
+#define GEN8_GS_DW8_GSCTRL_SID					(0x1 << 31)
+#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__MASK			0x00001fff
+#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHIFT			0
+#define GEN8_GS_DW8_URB_SEMAPHORE_ADDR__SHR			6
+#define GEN9_GS_DW8_MAX_THREADS__MASK				0x00001fff
+#define GEN9_GS_DW8_MAX_THREADS__SHIFT				0
+
+#define GEN8_GS_DW9_URB_WRITE_OFFSET__MASK			0x03e00000
+#define GEN8_GS_DW9_URB_WRITE_OFFSET__SHIFT			21
+#define GEN8_GS_DW9_URB_WRITE_LEN__MASK				0x001f0000
+#define GEN8_GS_DW9_URB_WRITE_LEN__SHIFT			16
+#define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK			0x0000ff00
+#define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT			8
+
+#define GEN7_3DSTATE_STREAMOUT__SIZE				5
 
 
 #define GEN7_SO_DW1_SO_ENABLE					(0x1 << 31)
@@ -568,6 +771,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SO_DW2_STREAM0_READ_LEN__MASK			0x0000001f
 #define GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT			0
 
+#define GEN8_SO_DW3_BUFFER1_PITCH__MASK				0x0fff0000
+#define GEN8_SO_DW3_BUFFER1_PITCH__SHIFT			16
+#define GEN8_SO_DW3_BUFFER0_PITCH__MASK				0x00000fff
+#define GEN8_SO_DW3_BUFFER0_PITCH__SHIFT			0
+
+#define GEN8_SO_DW4_BUFFER3_PITCH__MASK				0x0fff0000
+#define GEN8_SO_DW4_BUFFER3_PITCH__SHIFT			16
+#define GEN8_SO_DW4_BUFFER2_PITCH__MASK				0x00000fff
+#define GEN8_SO_DW4_BUFFER2_PITCH__SHIFT			0
+
 #define GEN7_3DSTATE_SO_DECL_LIST__SIZE				259
 
 
@@ -599,13 +812,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SO_DECL_COMPONENT_MASK__MASK			0x0000000f
 #define GEN7_SO_DECL_COMPONENT_MASK__SHIFT			0
 
-#define GEN7_3DSTATE_SO_BUFFER__SIZE				4
+#define GEN7_3DSTATE_SO_BUFFER__SIZE				8
 
 
+#define GEN8_SO_BUF_DW1_ENABLE					(0x1 << 31)
 #define GEN7_SO_BUF_DW1_INDEX__MASK				0x60000000
 #define GEN7_SO_BUF_DW1_INDEX__SHIFT				29
 #define GEN7_SO_BUF_DW1_MOCS__MASK				0x1e000000
 #define GEN7_SO_BUF_DW1_MOCS__SHIFT				25
+#define GEN8_SO_BUF_DW1_MOCS__MASK				0x1fc00000
+#define GEN8_SO_BUF_DW1_MOCS__SHIFT				22
+#define GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE			(0x1 << 21)
+#define GEN8_SO_BUF_DW1_OFFSET_ENABLE				(0x1 << 20)
 #define GEN7_SO_BUF_DW1_PITCH__MASK				0x00000fff
 #define GEN7_SO_BUF_DW1_PITCH__SHIFT				0
 
@@ -617,6 +835,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SO_BUF_DW3_END_ADDR__SHIFT				2
 #define GEN7_SO_BUF_DW3_END_ADDR__SHR				2
 
+#define GEN8_SO_BUF_DW2_ADDR__MASK				0xfffffffc
+#define GEN8_SO_BUF_DW2_ADDR__SHIFT				2
+#define GEN8_SO_BUF_DW2_ADDR__SHR				2
+
+
+
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR__MASK			0xfffffffc
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHIFT			2
+#define GEN8_SO_BUF_DW5_OFFSET_ADDR__SHR			2
+
+
+
 #define GEN6_3DSTATE_CLIP__SIZE					4
 
 
@@ -673,10 +903,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_CLIP_DW3_MAX_VPINDEX__MASK				0x0000000f
 #define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT			0
 
-#define GEN6_3DSTATE_SFBODY__SIZE				6
+#define GEN6_3DSTATE_SF_DW1_DW3__SIZE				3
 
 #define GEN7_SF_DW1_DEPTH_FORMAT__MASK				0x00007000
 #define GEN7_SF_DW1_DEPTH_FORMAT__SHIFT				12
+#define GEN9_SF_DW1_LINE_WIDTH__MASK				0x3ffff000
+#define GEN9_SF_DW1_LINE_WIDTH__SHIFT				12
+#define GEN9_SF_DW1_LINE_WIDTH__RADIX				7
 #define GEN7_SF_DW1_LEGACY_DEPTH_OFFSET				(0x1 << 11)
 #define GEN7_SF_DW1_STATISTICS					(0x1 << 10)
 #define GEN7_SF_DW1_DEPTH_OFFSET_SOLID				(0x1 << 9)
@@ -740,11 +973,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SF_DW3_POINT_WIDTH__SHIFT				0
 #define GEN7_SF_DW3_POINT_WIDTH__RADIX				3
 
+#define GEN7_3DSTATE_SBE_DW1__SIZE				13
 
-
-
-#define GEN6_3DSTATE_SBEBODY__SIZE				13
-
+#define GEN8_SBE_DW1_USE_URB_READ_LEN				(0x1 << 29)
+#define GEN8_SBE_DW1_USE_URB_READ_OFFSET			(0x1 << 28)
 #define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK				0x10000000
 #define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT			28
 #define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15				(0x0 << 28)
@@ -760,32 +992,49 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SBE_DW1_URB_READ_LEN__SHIFT			11
 #define GEN7_SBE_DW1_URB_READ_OFFSET__MASK			0x000003f0
 #define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT			4
+#define GEN8_SBE_DW1_URB_READ_OFFSET__MASK			0x000007e0
+#define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT			5
+
+#define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE			8
+
+#define GEN8_SBE_SWIZ_HIGH__MASK				0xffff0000
+#define GEN8_SBE_SWIZ_HIGH__SHIFT				16
+#define GEN8_SBE_SWIZ_OVERRIDE_W				(0x1 << 15)
+#define GEN8_SBE_SWIZ_OVERRIDE_Z				(0x1 << 14)
+#define GEN8_SBE_SWIZ_OVERRIDE_Y				(0x1 << 13)
+#define GEN8_SBE_SWIZ_OVERRIDE_X				(0x1 << 12)
+#define GEN8_SBE_SWIZ_CONST__MASK				0x00000600
+#define GEN8_SBE_SWIZ_CONST__SHIFT				9
+#define GEN8_SBE_SWIZ_CONST_0000				(0x0 << 9)
+#define GEN8_SBE_SWIZ_CONST_0001_FLOAT				(0x1 << 9)
+#define GEN8_SBE_SWIZ_CONST_1111_FLOAT				(0x2 << 9)
+#define GEN8_SBE_SWIZ_CONST_PRIM_ID				(0x3 << 9)
+#define GEN8_SBE_SWIZ_INPUTATTR__MASK				0x000000c0
+#define GEN8_SBE_SWIZ_INPUTATTR__SHIFT				6
+#define GEN8_SBE_SWIZ_INPUTATTR_NORMAL				(0x0 << 6)
+#define GEN8_SBE_SWIZ_INPUTATTR_FACING				(0x1 << 6)
+#define GEN8_SBE_SWIZ_INPUTATTR_W				(0x2 << 6)
+#define GEN8_SBE_SWIZ_INPUTATTR_FACING_W			(0x3 << 6)
+#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__MASK			0x0000001f
+#define GEN8_SBE_SWIZ_URB_ENTRY_OFFSET__SHIFT			0
+
+#define GEN6_3DSTATE_SF__SIZE					20
+
+
+
+
+
+
+
+
+
+
+
 
-#define GEN7_SBE_ATTR_HIGH__MASK				0xffff0000
-#define GEN7_SBE_ATTR_HIGH__SHIFT				16
-#define GEN7_SBE_ATTR_OVERRIDE_W				(0x1 << 15)
-#define GEN7_SBE_ATTR_OVERRIDE_Z				(0x1 << 14)
-#define GEN7_SBE_ATTR_OVERRIDE_Y				(0x1 << 13)
-#define GEN7_SBE_ATTR_OVERRIDE_X				(0x1 << 12)
-#define GEN7_SBE_ATTR_CONST__MASK				0x00000600
-#define GEN7_SBE_ATTR_CONST__SHIFT				9
-#define GEN7_SBE_ATTR_CONST_0000				(0x0 << 9)
-#define GEN7_SBE_ATTR_CONST_0001_FLOAT				(0x1 << 9)
-#define GEN7_SBE_ATTR_CONST_1111_FLOAT				(0x2 << 9)
-#define GEN7_SBE_ATTR_CONST_PRIM_ID				(0x3 << 9)
-#define GEN7_SBE_ATTR_INPUTATTR__MASK				0x000000c0
-#define GEN7_SBE_ATTR_INPUTATTR__SHIFT				6
-#define GEN7_SBE_ATTR_INPUTATTR_NORMAL				(0x0 << 6)
-#define GEN7_SBE_ATTR_INPUTATTR_FACING				(0x1 << 6)
-#define GEN7_SBE_ATTR_INPUTATTR_W				(0x2 << 6)
-#define GEN7_SBE_ATTR_INPUTATTR_FACING_W			(0x3 << 6)
-#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__MASK			0x0000001f
-#define GEN7_SBE_ATTR_URB_ENTRY_OFFSET__SHIFT			0
 
 
 
 
-#define GEN6_3DSTATE_SF__SIZE					20
 
 
 
@@ -794,6 +1043,64 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
+
+
+
+
+
+
+
+
+
+#define GEN9_SBE_DW_ACTIVE_COMPONENT__MASK			0x00000003
+#define GEN9_SBE_DW_ACTIVE_COMPONENT__SHIFT			0
+#define GEN9_SBE_DW_ACTIVE_COMPONENT_NONE			0x0
+#define GEN9_SBE_DW_ACTIVE_COMPONENT_XY				0x1
+#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZ			0x2
+#define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZW			0x3
+
+#define GEN8_3DSTATE_SBE_SWIZ__SIZE				11
+
+
+
+
+#define GEN8_3DSTATE_RASTER__SIZE				5
+
+
+#define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE			(0x1 << 26)
+#define GEN8_RASTER_DW1_FRONTWINDING__MASK			0x00200000
+#define GEN8_RASTER_DW1_FRONTWINDING__SHIFT			21
+#define GEN8_RASTER_DW1_FRONTWINDING_CW				(0x0 << 21)
+#define GEN8_RASTER_DW1_FRONTWINDING_CCW			(0x1 << 21)
+#define GEN8_RASTER_DW1_CULLMODE__MASK				0x00030000
+#define GEN8_RASTER_DW1_CULLMODE__SHIFT				16
+#define GEN8_RASTER_DW1_CULLMODE_BOTH				(0x0 << 16)
+#define GEN8_RASTER_DW1_CULLMODE_NONE				(0x1 << 16)
+#define GEN8_RASTER_DW1_CULLMODE_FRONT				(0x2 << 16)
+#define GEN8_RASTER_DW1_CULLMODE_BACK				(0x3 << 16)
+#define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE			(0x1 << 13)
+#define GEN8_RASTER_DW1_API_MULTISAMPLE_ENABLE			(0x1 << 12)
+#define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID			(0x1 << 9)
+#define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME			(0x1 << 8)
+#define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT			(0x1 << 7)
+#define GEN8_RASTER_DW1_FRONTFACE__MASK				0x00000060
+#define GEN8_RASTER_DW1_FRONTFACE__SHIFT			5
+#define GEN8_RASTER_DW1_FRONTFACE_SOLID				(0x0 << 5)
+#define GEN8_RASTER_DW1_FRONTFACE_WIREFRAME			(0x1 << 5)
+#define GEN8_RASTER_DW1_FRONTFACE_POINT				(0x2 << 5)
+#define GEN8_RASTER_DW1_BACKFACE__MASK				0x00000018
+#define GEN8_RASTER_DW1_BACKFACE__SHIFT				3
+#define GEN8_RASTER_DW1_BACKFACE_SOLID				(0x0 << 3)
+#define GEN8_RASTER_DW1_BACKFACE_WIREFRAME			(0x1 << 3)
+#define GEN8_RASTER_DW1_BACKFACE_POINT				(0x2 << 3)
+#define GEN8_RASTER_DW1_AA_LINE_ENABLE				(0x1 << 2)
+#define GEN8_RASTER_DW1_SCISSOR_ENABLE				(0x1 << 1)
+#define GEN8_RASTER_DW1_Z_TEST_ENABLE				(0x1 << 0)
+#define GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE			(0x1 << 0)
+
+
+
+
 #define GEN6_3DSTATE_WM__SIZE					9
 
 
@@ -817,10 +1124,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_WM_DW5_MAX_THREADS__MASK				0xfe000000
 #define GEN6_WM_DW5_MAX_THREADS__SHIFT				25
 #define GEN6_WM_DW5_LEGACY_LINE_RAST				(0x1 << 23)
-#define GEN6_WM_DW5_PS_KILL					(0x1 << 22)
+#define GEN6_WM_DW5_PS_KILL_PIXEL				(0x1 << 22)
 #define GEN6_WM_DW5_PS_COMPUTE_DEPTH				(0x1 << 21)
 #define GEN6_WM_DW5_PS_USE_DEPTH				(0x1 << 20)
-#define GEN6_WM_DW5_PS_ENABLE					(0x1 << 19)
+#define GEN6_WM_DW5_PS_DISPATCH_ENABLE				(0x1 << 19)
 #define GEN6_WM_DW5_AA_LINE_CAP__MASK				0x00030000
 #define GEN6_WM_DW5_AA_LINE_CAP__SHIFT				16
 #define GEN6_WM_DW5_AA_LINE_CAP_0_5				(0x0 << 16)
@@ -837,18 +1144,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_WM_DW5_LINE_STIPPLE_ENABLE				(0x1 << 11)
 #define GEN6_WM_DW5_PS_COMPUTE_OMASK				(0x1 << 9)
 #define GEN6_WM_DW5_PS_USE_W					(0x1 << 8)
-#define GEN6_WM_DW5_DUAL_SOURCE_BLEND				(0x1 << 7)
-#define GEN6_WM_DW5_32_PIXEL_DISPATCH				(0x1 << 2)
-#define GEN6_WM_DW5_16_PIXEL_DISPATCH				(0x1 << 1)
-#define GEN6_WM_DW5_8_PIXEL_DISPATCH				(0x1 << 0)
+#define GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND			(0x1 << 7)
+#define GEN6_WM_DW5_PS_DISPATCH_MODE__MASK			0x00000007
+#define GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT			0
 
 #define GEN6_WM_DW6_SF_ATTR_COUNT__MASK				0x03f00000
 #define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT			20
-#define GEN6_WM_DW6_POSOFFSET__MASK				0x000c0000
-#define GEN6_WM_DW6_POSOFFSET__SHIFT				18
-#define GEN6_WM_DW6_POSOFFSET_NONE				(0x0 << 18)
-#define GEN6_WM_DW6_POSOFFSET_CENTROID				(0x2 << 18)
-#define GEN6_WM_DW6_POSOFFSET_SAMPLE				(0x3 << 18)
+#define GEN6_WM_DW6_PS_POSOFFSET__MASK				0x000c0000
+#define GEN6_WM_DW6_PS_POSOFFSET__SHIFT				18
+#define GEN6_WM_DW6_PS_POSOFFSET_NONE				(0x0 << 18)
+#define GEN6_WM_DW6_PS_POSOFFSET_CENTROID			(0x2 << 18)
+#define GEN6_WM_DW6_PS_POSOFFSET_SAMPLE				(0x3 << 18)
 #define GEN6_WM_DW6_ZW_INTERP__MASK				0x00030000
 #define GEN6_WM_DW6_ZW_INTERP__SHIFT				16
 #define GEN6_WM_DW6_ZW_INTERP_PIXEL				(0x0 << 16)
@@ -882,11 +1188,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN7_WM_DW1_STATISTICS					(0x1 << 31)
 #define GEN7_WM_DW1_DEPTH_CLEAR					(0x1 << 30)
-#define GEN7_WM_DW1_PS_ENABLE					(0x1 << 29)
+#define GEN7_WM_DW1_PS_DISPATCH_ENABLE				(0x1 << 29)
 #define GEN7_WM_DW1_DEPTH_RESOLVE				(0x1 << 28)
 #define GEN7_WM_DW1_HIZ_RESOLVE					(0x1 << 27)
 #define GEN7_WM_DW1_LEGACY_LINE_RAST				(0x1 << 26)
-#define GEN7_WM_DW1_PS_KILL					(0x1 << 25)
+#define GEN7_WM_DW1_PS_KILL_PIXEL				(0x1 << 25)
 #define GEN7_WM_DW1_PSCDEPTH__MASK				0x01800000
 #define GEN7_WM_DW1_PSCDEPTH__SHIFT				23
 #define GEN7_WM_DW1_PSCDEPTH_OFF				(0x0 << 23)
@@ -907,7 +1213,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_WM_DW1_ZW_INTERP_SAMPLE				(0x3 << 17)
 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK			0x0001f800
 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT			11
-#define GEN7_WM_DW1_PS_USE_COVERAGE				(0x1 << 10)
+#define GEN7_WM_DW1_PS_USE_COVERAGE_MASK			(0x1 << 10)
 #define GEN7_WM_DW1_AA_LINE_CAP__MASK				0x00000300
 #define GEN7_WM_DW1_AA_LINE_CAP__SHIFT				8
 #define GEN7_WM_DW1_AA_LINE_CAP_0_5				(0x0 << 8)
@@ -920,6 +1226,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_WM_DW1_AA_LINE_WIDTH_1_0				(0x1 << 6)
 #define GEN7_WM_DW1_AA_LINE_WIDTH_2_0				(0x2 << 6)
 #define GEN7_WM_DW1_AA_LINE_WIDTH_4_0				(0x3 << 6)
+#define GEN75_WM_DW1_RT_INDEPENDENT_RAST			(0x1 << 5)
 #define GEN7_WM_DW1_POLY_STIPPLE_ENABLE				(0x1 << 4)
 #define GEN7_WM_DW1_LINE_STIPPLE_ENABLE				(0x1 << 3)
 #define GEN7_WM_DW1_POINT_RASTRULE__MASK			0x00000004
@@ -937,8 +1244,86 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_WM_DW2_MSDISPMODE__SHIFT				31
 #define GEN7_WM_DW2_MSDISPMODE_PERSAMPLE			(0x0 << 31)
 #define GEN7_WM_DW2_MSDISPMODE_PERPIXEL				(0x1 << 31)
-
-#define GEN7_3DSTATE_PS__SIZE					8
+#define GEN75_WM_DW2_PS_UAV_ONLY				(0x1 << 30)
+
+#define GEN8_3DSTATE_WM_CHROMAKEY__SIZE				2
+
+
+
+#define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE			4
+
+
+#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__MASK			0xe0000000
+#define GEN8_ZS_DW1_STENCIL0_FAIL_OP__SHIFT			29
+#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__MASK			0x1c000000
+#define GEN8_ZS_DW1_STENCIL0_ZFAIL_OP__SHIFT			26
+#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__MASK			0x03800000
+#define GEN8_ZS_DW1_STENCIL0_ZPASS_OP__SHIFT			23
+#define GEN8_ZS_DW1_STENCIL1_FUNC__MASK				0x00700000
+#define GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT			20
+#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__MASK			0x000e0000
+#define GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT			17
+#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__MASK			0x0001c000
+#define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT			14
+#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__MASK			0x00003800
+#define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT			11
+#define GEN8_ZS_DW1_STENCIL0_FUNC__MASK				0x00000700
+#define GEN8_ZS_DW1_STENCIL0_FUNC__SHIFT			8
+#define GEN8_ZS_DW1_DEPTH_FUNC__MASK				0x000000e0
+#define GEN8_ZS_DW1_DEPTH_FUNC__SHIFT				5
+#define GEN8_ZS_DW1_STENCIL1_ENABLE				(0x1 << 4)
+#define GEN8_ZS_DW1_STENCIL_TEST_ENABLE				(0x1 << 3)
+#define GEN8_ZS_DW1_STENCIL_WRITE_ENABLE			(0x1 << 2)
+#define GEN8_ZS_DW1_DEPTH_TEST_ENABLE				(0x1 << 1)
+#define GEN8_ZS_DW1_DEPTH_WRITE_ENABLE				(0x1 << 0)
+
+#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__MASK			0xff000000
+#define GEN8_ZS_DW2_STENCIL0_VALUEMASK__SHIFT			24
+#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__MASK			0x00ff0000
+#define GEN8_ZS_DW2_STENCIL0_WRITEMASK__SHIFT			16
+#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__MASK			0x0000ff00
+#define GEN8_ZS_DW2_STENCIL1_VALUEMASK__SHIFT			8
+#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__MASK			0x000000ff
+#define GEN8_ZS_DW2_STENCIL1_WRITEMASK__SHIFT			0
+
+#define GEN9_ZS_DW3_STENCIL0_REF__MASK				0x0000ff00
+#define GEN9_ZS_DW3_STENCIL0_REF__SHIFT				8
+#define GEN9_ZS_DW3_STENCIL1_REF__MASK				0x000000ff
+#define GEN9_ZS_DW3_STENCIL1_REF__SHIFT				0
+
+#define GEN8_3DSTATE_WM_HZ_OP__SIZE				5
+
+
+#define GEN8_WM_HZ_DW1_STENCIL_CLEAR				(0x1 << 31)
+#define GEN8_WM_HZ_DW1_DEPTH_CLEAR				(0x1 << 30)
+#define GEN8_WM_HZ_DW1_DEPTH_RESOLVE				(0x1 << 28)
+#define GEN8_WM_HZ_DW1_HIZ_RESOLVE				(0x1 << 27)
+#define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE			(0x1 << 26)
+#define GEN8_WM_HZ_DW1_FULL_SURFACE_DEPTH_CLEAR			(0x1 << 25)
+#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__MASK		0x00ff0000
+#define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__SHIFT		16
+#define GEN8_WM_HZ_DW1_NUMSAMPLES__MASK				0x0000e000
+#define GEN8_WM_HZ_DW1_NUMSAMPLES__SHIFT			13
+#define GEN8_WM_HZ_DW1_NUMSAMPLES_1				(0x0 << 13)
+#define GEN8_WM_HZ_DW1_NUMSAMPLES_2				(0x1 << 13)
+#define GEN8_WM_HZ_DW1_NUMSAMPLES_4				(0x2 << 13)
+#define GEN8_WM_HZ_DW1_NUMSAMPLES_8				(0x3 << 13)
+#define GEN8_WM_HZ_DW1_NUMSAMPLES_16				(0x4 << 13)
+
+#define GEN8_WM_HZ_DW2_RECT_MIN_Y__MASK				0xffff0000
+#define GEN8_WM_HZ_DW2_RECT_MIN_Y__SHIFT			16
+#define GEN8_WM_HZ_DW2_RECT_MIN_X__MASK				0x0000ffff
+#define GEN8_WM_HZ_DW2_RECT_MIN_X__SHIFT			0
+
+#define GEN8_WM_HZ_DW3_RECT_MAX_Y__MASK				0xffff0000
+#define GEN8_WM_HZ_DW3_RECT_MAX_Y__SHIFT			16
+#define GEN8_WM_HZ_DW3_RECT_MAX_X__MASK				0x0000ffff
+#define GEN8_WM_HZ_DW3_RECT_MAX_X__SHIFT			0
+
+#define GEN8_WM_HZ_DW4_SAMPLE_MASK__MASK			0x0000ffff
+#define GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT			0
+
+#define GEN7_3DSTATE_PS__SIZE					12
 
 
 #define GEN7_PS_DW1_KERNEL0_ADDR__MASK				0xffffffc0
@@ -955,19 +1340,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_PS_DW4_SAMPLE_MASK__SHIFT				12
 #define GEN7_PS_DW4_PUSH_CONSTANT_ENABLE			(0x1 << 11)
 #define GEN7_PS_DW4_ATTR_ENABLE					(0x1 << 10)
-#define GEN7_PS_DW4_PS_COMPUTE_OMASK				(0x1 << 9)
+#define GEN7_PS_DW4_COMPUTE_OMASK				(0x1 << 9)
 #define GEN7_PS_DW4_RT_FAST_CLEAR				(0x1 << 8)
 #define GEN7_PS_DW4_DUAL_SOURCE_BLEND				(0x1 << 7)
 #define GEN7_PS_DW4_RT_RESOLVE					(0x1 << 6)
-#define GEN75_PS_DW4_PS_ACCESS_UAV				(0x1 << 5)
+#define GEN75_PS_DW4_ACCESS_UAV					(0x1 << 5)
 #define GEN7_PS_DW4_POSOFFSET__MASK				0x00000018
 #define GEN7_PS_DW4_POSOFFSET__SHIFT				3
 #define GEN7_PS_DW4_POSOFFSET_NONE				(0x0 << 3)
 #define GEN7_PS_DW4_POSOFFSET_CENTROID				(0x2 << 3)
 #define GEN7_PS_DW4_POSOFFSET_SAMPLE				(0x3 << 3)
-#define GEN7_PS_DW4_32_PIXEL_DISPATCH				(0x1 << 2)
-#define GEN7_PS_DW4_16_PIXEL_DISPATCH				(0x1 << 1)
-#define GEN7_PS_DW4_8_PIXEL_DISPATCH				(0x1 << 0)
+#define GEN7_PS_DW4_DISPATCH_MODE__MASK				0x00000007
+#define GEN7_PS_DW4_DISPATCH_MODE__SHIFT			0
 
 #define GEN7_PS_DW5_URB_GRF_START0__MASK			0x007f0000
 #define GEN7_PS_DW5_URB_GRF_START0__SHIFT			16
@@ -984,38 +1368,120 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_PS_DW7_KERNEL2_ADDR__SHIFT				6
 #define GEN7_PS_DW7_KERNEL2_ADDR__SHR				6
 
-#define GEN6_3DSTATE_CONSTANT_ANY__SIZE				7
 
-#define GEN6_PCB_ANY_DW0_PCB3_VALID				(0x1 << 15)
-#define GEN6_PCB_ANY_DW0_PCB2_VALID				(0x1 << 14)
-#define GEN6_PCB_ANY_DW0_PCB1_VALID				(0x1 << 13)
-#define GEN6_PCB_ANY_DW0_PCB0_VALID				(0x1 << 12)
-#define GEN6_PCB_ANY_DW0_MOCS__MASK				0x00000f00
-#define GEN6_PCB_ANY_DW0_MOCS__SHIFT				8
 
-#define GEN6_PCB_ANY_SIZE__MASK					0x0000001f
-#define GEN6_PCB_ANY_SIZE__SHIFT				0
-#define GEN6_PCB_ANY_ADDR__MASK					0xffffffe0
-#define GEN6_PCB_ANY_ADDR__SHIFT				5
-#define GEN6_PCB_ANY_ADDR__SHR					5
+#define GEN8_PS_DW1_KERNEL0_ADDR__MASK				0xffffffc0
+#define GEN8_PS_DW1_KERNEL0_ADDR__SHIFT				6
+#define GEN8_PS_DW1_KERNEL0_ADDR__SHR				6
+
+
+
+
 
+#define GEN8_PS_DW6_MAX_THREADS__MASK				0xff800000
+#define GEN8_PS_DW6_MAX_THREADS__SHIFT				23
+#define GEN8_PS_DW6_PUSH_CONSTANT_ENABLE			(0x1 << 11)
+#define GEN8_PS_DW6_RT_FAST_CLEAR				(0x1 << 8)
+#define GEN8_PS_DW6_RT_RESOLVE					(0x1 << 6)
+#define GEN8_PS_DW6_POSOFFSET__MASK				0x00000018
+#define GEN8_PS_DW6_POSOFFSET__SHIFT				3
+#define GEN8_PS_DW6_POSOFFSET_NONE				(0x0 << 3)
+#define GEN8_PS_DW6_POSOFFSET_CENTROID				(0x2 << 3)
+#define GEN8_PS_DW6_POSOFFSET_SAMPLE				(0x3 << 3)
+#define GEN8_PS_DW6_DISPATCH_MODE__MASK				0x00000007
+#define GEN8_PS_DW6_DISPATCH_MODE__SHIFT			0
 
+#define GEN8_PS_DW7_URB_GRF_START0__MASK			0x007f0000
+#define GEN8_PS_DW7_URB_GRF_START0__SHIFT			16
+#define GEN8_PS_DW7_URB_GRF_START1__MASK			0x00007f00
+#define GEN8_PS_DW7_URB_GRF_START1__SHIFT			8
+#define GEN8_PS_DW7_URB_GRF_START2__MASK			0x0000007f
+#define GEN8_PS_DW7_URB_GRF_START2__SHIFT			0
 
-#define GEN7_PCB_ANY_DW1_PCB1_SIZE__MASK			0xffff0000
-#define GEN7_PCB_ANY_DW1_PCB1_SIZE__SHIFT			16
-#define GEN7_PCB_ANY_DW1_PCB0_SIZE__MASK			0x0000ffff
-#define GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT			0
+#define GEN8_PS_DW8_KERNEL1_ADDR__MASK				0xffffffc0
+#define GEN8_PS_DW8_KERNEL1_ADDR__SHIFT				6
+#define GEN8_PS_DW8_KERNEL1_ADDR__SHR				6
 
-#define GEN7_PCB_ANY_DW2_PCB3_SIZE__MASK			0xffff0000
-#define GEN7_PCB_ANY_DW2_PCB3_SIZE__SHIFT			16
-#define GEN7_PCB_ANY_DW2_PCB2_SIZE__MASK			0x0000ffff
-#define GEN7_PCB_ANY_DW2_PCB2_SIZE__SHIFT			0
 
-#define GEN7_PCB_ANY_MOCS__MASK					0x0000001f
-#define GEN7_PCB_ANY_MOCS__SHIFT				0
-#define GEN7_PCB_ANY_ADDR__MASK					0xffffffe0
-#define GEN7_PCB_ANY_ADDR__SHIFT				5
-#define GEN7_PCB_ANY_ADDR__SHR					5
+#define GEN8_PS_DW10_KERNEL2_ADDR__MASK				0xffffffc0
+#define GEN8_PS_DW10_KERNEL2_ADDR__SHIFT			6
+#define GEN8_PS_DW10_KERNEL2_ADDR__SHR				6
+
+
+#define GEN8_3DSTATE_PS_EXTRA__SIZE				2
+
+
+#define GEN8_PSX_DW1_DISPATCH_ENABLE				(0x1 << 31)
+#define GEN8_PSX_DW1_UAV_ONLY					(0x1 << 30)
+#define GEN8_PSX_DW1_COMPUTE_OMASK				(0x1 << 29)
+#define GEN8_PSX_DW1_KILL_PIXEL					(0x1 << 28)
+#define GEN8_PSX_DW1_PSCDEPTH__MASK				0x0c000000
+#define GEN8_PSX_DW1_PSCDEPTH__SHIFT				26
+#define GEN8_PSX_DW1_PSCDEPTH_OFF				(0x0 << 26)
+#define GEN8_PSX_DW1_PSCDEPTH_ON				(0x1 << 26)
+#define GEN8_PSX_DW1_PSCDEPTH_ON_GE				(0x2 << 26)
+#define GEN8_PSX_DW1_PSCDEPTH_ON_LE				(0x3 << 26)
+#define GEN8_PSX_DW1_FORCE_COMPUTE_DEPTH			(0x1 << 25)
+#define GEN8_PSX_DW1_USE_DEPTH					(0x1 << 24)
+#define GEN8_PSX_DW1_USE_W					(0x1 << 23)
+#define GEN8_PSX_DW1_ATTR_ENABLE				(0x1 << 8)
+#define GEN8_PSX_DW1_DISABLE_ALPHA_TO_COVERAGE			(0x1 << 7)
+#define GEN8_PSX_DW1_PER_SAMPLE					(0x1 << 6)
+#define GEN8_PSX_DW1_COMPUTE_STENCIL				(0x1 << 5)
+#define GEN8_PSX_DW1_ACCESS_UAV					(0x1 << 2)
+#define GEN8_PSX_DW1_USE_COVERAGE_MASK				(0x1 << 1)
+
+#define GEN8_3DSTATE_PS_BLEND__SIZE				2
+
+
+#define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE			(0x1 << 31)
+#define GEN8_PS_BLEND_DW1_WRITABLE_RT				(0x1 << 30)
+#define GEN8_PS_BLEND_DW1_BLEND_ENABLE				(0x1 << 29)
+#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__MASK		0x1f000000
+#define GEN8_PS_BLEND_DW1_SRC_ALPHA_FACTOR__SHIFT		24
+#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__MASK		0x00f80000
+#define GEN8_PS_BLEND_DW1_DST_ALPHA_FACTOR__SHIFT		19
+#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__MASK		0x0007c000
+#define GEN8_PS_BLEND_DW1_SRC_COLOR_FACTOR__SHIFT		14
+#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__MASK		0x00003e00
+#define GEN8_PS_BLEND_DW1_DST_COLOR_FACTOR__SHIFT		9
+#define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE			(0x1 << 8)
+#define GEN8_PS_BLEND_DW1_INDEPENDENT_ALPHA_ENABLE		(0x1 << 7)
+
+#define GEN6_3DSTATE_CONSTANT_ANY__SIZE				11
+
+#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__MASK			0x0000f000
+#define GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT			12
+#define GEN6_CONSTANT_DW0_MOCS__MASK				0x00000f00
+#define GEN6_CONSTANT_DW0_MOCS__SHIFT				8
+
+#define GEN6_CONSTANT_DW_ADDR_READ_LEN__MASK			0x0000001f
+#define GEN6_CONSTANT_DW_ADDR_READ_LEN__SHIFT			0
+#define GEN6_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
+#define GEN6_CONSTANT_DW_ADDR_ADDR__SHIFT			5
+#define GEN6_CONSTANT_DW_ADDR_ADDR__SHR				5
+
+
+
+#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK		0xffff0000
+#define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT		16
+#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__MASK		0x0000ffff
+#define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__SHIFT		0
+
+#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__MASK		0xffff0000
+#define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__SHIFT		16
+#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__MASK		0x0000ffff
+#define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__SHIFT		0
+
+#define GEN7_CONSTANT_DW_ADDR_MOCS__MASK			0x0000001f
+#define GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT			0
+#define GEN7_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
+#define GEN7_CONSTANT_DW_ADDR_ADDR__SHIFT			5
+#define GEN7_CONSTANT_DW_ADDR_ADDR__SHR				5
+
+#define GEN8_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
+#define GEN8_CONSTANT_DW_ADDR_ADDR__SHIFT			5
+#define GEN8_CONSTANT_DW_ADDR_ADDR__SHR				5
 
 #define GEN6_3DSTATE_SAMPLE_MASK__SIZE				2
 
@@ -1024,6 +1490,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_SAMPLE_MASK_DW1_VAL__SHIFT				0
 #define GEN7_SAMPLE_MASK_DW1_VAL__MASK				0x000000ff
 #define GEN7_SAMPLE_MASK_DW1_VAL__SHIFT				0
+#define GEN8_SAMPLE_MASK_DW1_VAL__MASK				0x0000ffff
+#define GEN8_SAMPLE_MASK_DW1_VAL__SHIFT				0
 
 #define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE			4
 
@@ -1043,7 +1511,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__MASK		0x0000ffff
 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__SHIFT		0
 
-#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE				7
+#define GEN6_3DSTATE_DEPTH_BUFFER__SIZE				8
 
 
 #define GEN6_DEPTH_DW1_TYPE__MASK				0xe0000000
@@ -1121,6 +1589,44 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__MASK			0xffe00000
 #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT			21
 
+
+
+#define GEN8_DEPTH_DW1_TYPE__MASK				0xe0000000
+#define GEN8_DEPTH_DW1_TYPE__SHIFT				29
+#define GEN8_DEPTH_DW1_DEPTH_WRITE_ENABLE			(0x1 << 28)
+#define GEN8_DEPTH_DW1_STENCIL_WRITE_ENABLE			(0x1 << 27)
+#define GEN8_DEPTH_DW1_HIZ_ENABLE				(0x1 << 22)
+#define GEN8_DEPTH_DW1_FORMAT__MASK				0x001c0000
+#define GEN8_DEPTH_DW1_FORMAT__SHIFT				18
+#define GEN8_DEPTH_DW1_PITCH__MASK				0x0003ffff
+#define GEN8_DEPTH_DW1_PITCH__SHIFT				0
+
+
+
+#define GEN8_DEPTH_DW4_HEIGHT__MASK				0xfffc0000
+#define GEN8_DEPTH_DW4_HEIGHT__SHIFT				18
+#define GEN8_DEPTH_DW4_WIDTH__MASK				0x0003fff0
+#define GEN8_DEPTH_DW4_WIDTH__SHIFT				4
+#define GEN8_DEPTH_DW4_LOD__MASK				0x0000000f
+#define GEN8_DEPTH_DW4_LOD__SHIFT				0
+
+#define GEN8_DEPTH_DW5_DEPTH__MASK				0xffe00000
+#define GEN8_DEPTH_DW5_DEPTH__SHIFT				21
+#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__MASK			0x001ffc00
+#define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__SHIFT			10
+#define GEN8_DEPTH_DW5_MOCS__MASK				0x0000007f
+#define GEN8_DEPTH_DW5_MOCS__SHIFT				0
+
+#define GEN8_DEPTH_DW6_OFFSET_Y__MASK				0xffff0000
+#define GEN8_DEPTH_DW6_OFFSET_Y__SHIFT				16
+#define GEN8_DEPTH_DW6_OFFSET_X__MASK				0x0000ffff
+#define GEN8_DEPTH_DW6_OFFSET_X__SHIFT				0
+
+#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK			0xffe00000
+#define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT			21
+#define GEN8_DEPTH_DW7_QPITCH__MASK				0x00007fff
+#define GEN8_DEPTH_DW7_QPITCH__SHIFT				0
+
 #define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE			2
 
 
@@ -1185,22 +1691,41 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__MASK			0x0000000e
 #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES__SHIFT			1
 #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1			(0x0 << 1)
+#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_2			(0x1 << 1)
 #define GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4			(0x2 << 1)
 #define GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8			(0x3 << 1)
+#define GEN8_MULTISAMPLE_DW1_NUMSAMPLES_16			(0x4 << 1)
+
+
+
+#define GEN8_3DSTATE_SAMPLE_PATTERN__SIZE			9
+
 
 
 
-#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE			3
+
+#define GEN8_SAMPLE_PATTERN_DW8_1X__MASK			0x00ff0000
+#define GEN8_SAMPLE_PATTERN_DW8_1X__SHIFT			16
+#define GEN8_SAMPLE_PATTERN_DW8_2X__MASK			0x0000ffff
+#define GEN8_SAMPLE_PATTERN_DW8_2X__SHIFT			0
+
+#define GEN6_3DSTATE_STENCIL_BUFFER__SIZE			5
 
 
 #define GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE			(0x1 << 31)
 #define GEN6_STENCIL_DW1_MOCS__MASK				0x1e000000
 #define GEN6_STENCIL_DW1_MOCS__SHIFT				25
+#define GEN8_STENCIL_DW1_MOCS__MASK				0x1fc00000
+#define GEN8_STENCIL_DW1_MOCS__SHIFT				22
 #define GEN6_STENCIL_DW1_PITCH__MASK				0x0001ffff
 #define GEN6_STENCIL_DW1_PITCH__SHIFT				0
 
 
-#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE			3
+
+#define GEN8_STENCIL_DW4_QPITCH__MASK				0x00007fff
+#define GEN8_STENCIL_DW4_QPITCH__SHIFT				0
+
+#define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE			5
 
 
 #define GEN6_HIZ_DW1_MOCS__MASK					0x1e000000
@@ -1215,56 +1740,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
-
-
 #define GEN7_CLEAR_PARAMS_DW2_VALID				(0x1 << 0)
 
-#define GEN6_PIPE_CONTROL__SIZE					5
-
-
-#define GEN7_PIPE_CONTROL_USE_GGTT				(0x1 << 24)
-#define GEN7_PIPE_CONTROL_LRI_WRITE__MASK			0x00800000
-#define GEN7_PIPE_CONTROL_LRI_WRITE__SHIFT			23
-#define GEN7_PIPE_CONTROL_LRI_WRITE_NONE			(0x0 << 23)
-#define GEN7_PIPE_CONTROL_LRI_WRITE_IMM				(0x1 << 23)
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_ENABLE		(0x1 << 22)
-#define GEN6_PIPE_CONTROL_STORE_DATA_INDEX			(0x1 << 21)
-#define GEN6_PIPE_CONTROL_CS_STALL				(0x1 << 20)
-#define GEN6_PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET		(0x1 << 19)
-#define GEN6_PIPE_CONTROL_TLB_INVALIDATE			(0x1 << 18)
-#define GEN6_PIPE_CONTROL_SYNC_GFDT_SURFACE			(0x1 << 17)
-#define GEN6_PIPE_CONTROL_GENERIC_MEDIA_STATE_CLEAR		(0x1 << 16)
-#define GEN6_PIPE_CONTROL_WRITE__MASK				0x0000c000
-#define GEN6_PIPE_CONTROL_WRITE__SHIFT				14
-#define GEN6_PIPE_CONTROL_WRITE_NONE				(0x0 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_IMM				(0x1 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT			(0x2 << 14)
-#define GEN6_PIPE_CONTROL_WRITE_TIMESTAMP			(0x3 << 14)
-#define GEN6_PIPE_CONTROL_DEPTH_STALL				(0x1 << 13)
-#define GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH			(0x1 << 12)
-#define GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE		(0x1 << 11)
-#define GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(0x1 << 10)
-#define GEN6_PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE	(0x1 << 9)
-#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE				(0x1 << 8)
-#define GEN7_PIPE_CONTROL_FLUSH_ENABLE				(0x1 << 7)
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__MASK		0x00000040
-#define GEN6_PIPE_CONTROL_PROTECTED_MEMORY_APP_ID__SHIFT	6
-#define GEN7_PIPE_CONTROL_DC_FLUSH_ENABLE			(0x1 << 5)
-#define GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE			(0x1 << 4)
-#define GEN6_PIPE_CONTROL_CONSTANT_CACHE_INVALIDATE		(0x1 << 3)
-#define GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE		(0x1 << 2)
-#define GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL		(0x1 << 1)
-#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH			(0x1 << 0)
-
-#define GEN6_PIPE_CONTROL_DW2_ADDR__MASK			0xfffffff8
-#define GEN6_PIPE_CONTROL_DW2_ADDR__SHIFT			3
-#define GEN6_PIPE_CONTROL_DW2_ADDR__SHR				3
-#define GEN6_PIPE_CONTROL_DW2_USE_GGTT				(0x1 << 2)
-#define GEN7_PIPE_CONTROL_DW2_ADDR__MASK			0xfffffffc
-#define GEN7_PIPE_CONTROL_DW2_ADDR__SHIFT			2
-#define GEN7_PIPE_CONTROL_DW2_ADDR__SHR				2
-
-
 #define GEN6_3DPRIMITIVE__SIZE					7
 
 #define GEN6_3DPRIM_DW0_ACCESS__MASK				0x00008000
@@ -1282,6 +1759,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 #define GEN7_3DPRIM_DW0_INDIRECT_PARAM_ENABLE			(0x1 << 10)
+#define GEN75_3DPRIM_DW0_UAV_COHERENCY_REQUIRED			(0x1 << 9)
 #define GEN7_3DPRIM_DW0_PREDICATE_ENABLE			(0x1 << 8)
 
 #define GEN7_3DPRIM_DW1_END_OFFSET_ENABLE			(0x1 << 9)
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
index f1bae49e26b..570ea6bdfae 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -109,6 +109,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_TEXCOORDMODE_CUBE					0x3
 #define GEN6_TEXCOORDMODE_CLAMP_BORDER				0x4
 #define GEN6_TEXCOORDMODE_MIRROR_ONCE				0x5
+#define GEN8_TEXCOORDMODE_HALF_BORDER				0x6
 #define GEN6_KEYFILTER_KILL_ON_ANY_MATCH			0x0
 #define GEN6_KEYFILTER_REPLACE_BLACK				0x1
 #define GEN6_COLOR_CALC_STATE__SIZE				6
@@ -164,72 +165,145 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_ZS_DW2_DEPTH_FUNC__SHIFT				27
 #define GEN6_ZS_DW2_DEPTH_WRITE_ENABLE				(0x1 << 26)
 
-#define GEN6_BLEND_STATE__SIZE					2
+#define GEN6_BLEND_STATE__SIZE					17
+
+
+#define GEN6_RT_DW0_BLEND_ENABLE				(0x1 << 31)
+#define GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE			(0x1 << 30)
+#define GEN6_RT_DW0_ALPHA_FUNC__MASK				0x1c000000
+#define GEN6_RT_DW0_ALPHA_FUNC__SHIFT				26
+#define GEN6_RT_DW0_SRC_ALPHA_FACTOR__MASK			0x01f00000
+#define GEN6_RT_DW0_SRC_ALPHA_FACTOR__SHIFT			20
+#define GEN6_RT_DW0_DST_ALPHA_FACTOR__MASK			0x000f8000
+#define GEN6_RT_DW0_DST_ALPHA_FACTOR__SHIFT			15
+#define GEN6_RT_DW0_COLOR_FUNC__MASK				0x00003800
+#define GEN6_RT_DW0_COLOR_FUNC__SHIFT				11
+#define GEN6_RT_DW0_SRC_COLOR_FACTOR__MASK			0x000003e0
+#define GEN6_RT_DW0_SRC_COLOR_FACTOR__SHIFT			5
+#define GEN6_RT_DW0_DST_COLOR_FACTOR__MASK			0x0000001f
+#define GEN6_RT_DW0_DST_COLOR_FACTOR__SHIFT			0
 
-#define GEN6_BLEND_DW0_BLEND_ENABLE				(0x1 << 31)
-#define GEN6_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE			(0x1 << 30)
-#define GEN6_BLEND_DW0_ALPHA_FUNC__MASK				0x1c000000
-#define GEN6_BLEND_DW0_ALPHA_FUNC__SHIFT			26
-#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__MASK			0x01f00000
-#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__SHIFT			20
-#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__MASK			0x000f8000
-#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__SHIFT			15
-#define GEN6_BLEND_DW0_COLOR_FUNC__MASK				0x00003800
-#define GEN6_BLEND_DW0_COLOR_FUNC__SHIFT			11
-#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__MASK			0x000003e0
-#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__SHIFT			5
-#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__MASK			0x0000001f
-#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__SHIFT			0
+#define GEN6_RT_DW1_ALPHA_TO_COVERAGE				(0x1 << 31)
+#define GEN6_RT_DW1_ALPHA_TO_ONE				(0x1 << 30)
+#define GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER			(0x1 << 29)
+#define GEN6_RT_DW1_WRITE_DISABLE_A				(0x1 << 27)
+#define GEN6_RT_DW1_WRITE_DISABLE_R				(0x1 << 26)
+#define GEN6_RT_DW1_WRITE_DISABLE_G				(0x1 << 25)
+#define GEN6_RT_DW1_WRITE_DISABLE_B				(0x1 << 24)
+#define GEN6_RT_DW1_LOGICOP_ENABLE				(0x1 << 22)
+#define GEN6_RT_DW1_LOGICOP_FUNC__MASK				0x003c0000
+#define GEN6_RT_DW1_LOGICOP_FUNC__SHIFT				18
+#define GEN6_RT_DW1_ALPHA_TEST_ENABLE				(0x1 << 16)
+#define GEN6_RT_DW1_ALPHA_TEST_FUNC__MASK			0x0000e000
+#define GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT			13
+#define GEN6_RT_DW1_DITHER_ENABLE				(0x1 << 12)
+#define GEN6_RT_DW1_X_DITHER_OFFSET__MASK			0x00000c00
+#define GEN6_RT_DW1_X_DITHER_OFFSET__SHIFT			10
+#define GEN6_RT_DW1_Y_DITHER_OFFSET__MASK			0x00000300
+#define GEN6_RT_DW1_Y_DITHER_OFFSET__SHIFT			8
+#define GEN6_RT_DW1_COLORCLAMP__MASK				0x0000000c
+#define GEN6_RT_DW1_COLORCLAMP__SHIFT				2
+#define GEN6_RT_DW1_COLORCLAMP_UNORM				(0x0 << 2)
+#define GEN6_RT_DW1_COLORCLAMP_SNORM				(0x1 << 2)
+#define GEN6_RT_DW1_COLORCLAMP_RTFORMAT				(0x2 << 2)
+#define GEN6_RT_DW1_PRE_BLEND_CLAMP				(0x1 << 1)
+#define GEN6_RT_DW1_POST_BLEND_CLAMP				(0x1 << 0)
 
-#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE			(0x1 << 31)
-#define GEN6_BLEND_DW1_ALPHA_TO_ONE				(0x1 << 30)
-#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE_DITHER			(0x1 << 29)
-#define GEN6_BLEND_DW1_WRITE_DISABLE_A				(0x1 << 27)
-#define GEN6_BLEND_DW1_WRITE_DISABLE_R				(0x1 << 26)
-#define GEN6_BLEND_DW1_WRITE_DISABLE_G				(0x1 << 25)
-#define GEN6_BLEND_DW1_WRITE_DISABLE_B				(0x1 << 24)
-#define GEN6_BLEND_DW1_LOGICOP_ENABLE				(0x1 << 22)
-#define GEN6_BLEND_DW1_LOGICOP_FUNC__MASK			0x003c0000
-#define GEN6_BLEND_DW1_LOGICOP_FUNC__SHIFT			18
-#define GEN6_BLEND_DW1_ALPHA_TEST_ENABLE			(0x1 << 16)
-#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__MASK			0x0000e000
-#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__SHIFT			13
-#define GEN6_BLEND_DW1_DITHER_ENABLE				(0x1 << 12)
-#define GEN6_BLEND_DW1_X_DITHER_OFFSET__MASK			0x00000c00
-#define GEN6_BLEND_DW1_X_DITHER_OFFSET__SHIFT			10
-#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__MASK			0x00000300
-#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__SHIFT			8
-#define GEN6_BLEND_DW1_COLORCLAMP__MASK				0x0000000c
-#define GEN6_BLEND_DW1_COLORCLAMP__SHIFT			2
-#define GEN6_BLEND_DW1_COLORCLAMP_UNORM				(0x0 << 2)
-#define GEN6_BLEND_DW1_COLORCLAMP_SNORM				(0x1 << 2)
-#define GEN6_BLEND_DW1_COLORCLAMP_RTFORMAT			(0x2 << 2)
-#define GEN6_BLEND_DW1_PRE_BLEND_CLAMP				(0x1 << 1)
-#define GEN6_BLEND_DW1_POST_BLEND_CLAMP				(0x1 << 0)
 
-#define GEN6_CLIP_VIEWPORT__SIZE				4
+#define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE			(0x1 << 31)
+#define GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE			(0x1 << 30)
+#define GEN8_BLEND_DW0_ALPHA_TO_ONE				(0x1 << 29)
+#define GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER			(0x1 << 28)
+#define GEN8_BLEND_DW0_ALPHA_TEST_ENABLE			(0x1 << 27)
+#define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__MASK			0x07000000
+#define GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT			24
+#define GEN8_BLEND_DW0_DITHER_ENABLE				(0x1 << 23)
+#define GEN8_BLEND_DW0_X_DITHER_OFFSET__MASK			0x00600000
+#define GEN8_BLEND_DW0_X_DITHER_OFFSET__SHIFT			21
+#define GEN8_BLEND_DW0_Y_DITHER_OFFSET__MASK			0x00180000
+#define GEN8_BLEND_DW0_Y_DITHER_OFFSET__SHIFT			19
 
 
+#define GEN8_RT_DW0_BLEND_ENABLE				(0x1 << 31)
+#define GEN8_RT_DW0_SRC_COLOR_FACTOR__MASK			0x7c000000
+#define GEN8_RT_DW0_SRC_COLOR_FACTOR__SHIFT			26
+#define GEN8_RT_DW0_DST_COLOR_FACTOR__MASK			0x03e00000
+#define GEN8_RT_DW0_DST_COLOR_FACTOR__SHIFT			21
+#define GEN8_RT_DW0_COLOR_FUNC__MASK				0x001c0000
+#define GEN8_RT_DW0_COLOR_FUNC__SHIFT				18
+#define GEN8_RT_DW0_SRC_ALPHA_FACTOR__MASK			0x0003e000
+#define GEN8_RT_DW0_SRC_ALPHA_FACTOR__SHIFT			13
+#define GEN8_RT_DW0_DST_ALPHA_FACTOR__MASK			0x00001f00
+#define GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT			8
+#define GEN8_RT_DW0_ALPHA_FUNC__MASK				0x000000e0
+#define GEN8_RT_DW0_ALPHA_FUNC__SHIFT				5
+#define GEN8_RT_DW0_WRITE_DISABLE_A				(0x1 << 3)
+#define GEN8_RT_DW0_WRITE_DISABLE_R				(0x1 << 2)
+#define GEN8_RT_DW0_WRITE_DISABLE_G				(0x1 << 1)
+#define GEN8_RT_DW0_WRITE_DISABLE_B				(0x1 << 0)
 
+#define GEN8_RT_DW1_LOGICOP_ENABLE				(0x1 << 31)
+#define GEN8_RT_DW1_LOGICOP_FUNC__MASK				0x78000000
+#define GEN8_RT_DW1_LOGICOP_FUNC__SHIFT				27
+#define GEN8_RT_DW1_PRE_BLEND_CLAMP_SRC_ONLY			(0x1 << 4)
+#define GEN8_RT_DW1_COLORCLAMP__MASK				0x0000000c
+#define GEN8_RT_DW1_COLORCLAMP__SHIFT				2
+#define GEN8_RT_DW1_COLORCLAMP_UNORM				(0x0 << 2)
+#define GEN8_RT_DW1_COLORCLAMP_SNORM				(0x1 << 2)
+#define GEN8_RT_DW1_COLORCLAMP_RTFORMAT				(0x2 << 2)
+#define GEN8_RT_DW1_PRE_BLEND_CLAMP				(0x1 << 1)
+#define GEN8_RT_DW1_POST_BLEND_CLAMP				(0x1 << 0)
 
+#define GEN6_CLIP_VIEWPORT__SIZE				64
 
-#define GEN6_SF_VIEWPORT__SIZE					8
 
 
 
 
 
+#define GEN6_SF_VIEWPORT__SIZE					128
 
 
-#define GEN7_SF_CLIP_VIEWPORT__SIZE				16
 
 
 
-#define GEN6_CC_VIEWPORT__SIZE					2
 
 
 
-#define GEN6_SCISSOR_RECT__SIZE					2
+
+
+#define GEN7_SF_CLIP_VIEWPORT__SIZE				256
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#define GEN6_CC_VIEWPORT__SIZE					32
+
+
+
+
+#define GEN6_SCISSOR_RECT__SIZE					32
+
 
 #define GEN6_SCISSOR_DW0_MIN_Y__MASK				0xffff0000
 #define GEN6_SCISSOR_DW0_MIN_Y__SHIFT				16
@@ -241,15 +315,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_SCISSOR_DW1_MAX_X__MASK				0x0000ffff
 #define GEN6_SCISSOR_DW1_MAX_X__SHIFT				0
 
-#define GEN6_SAMPLER_BORDER_COLOR__SIZE				12
+#define GEN6_SAMPLER_BORDER_COLOR_STATE__SIZE			12
 
 
 
 #define GEN6_SAMPLER_STATE__SIZE				4
 
 #define GEN6_SAMPLER_DW0_DISABLE				(0x1 << 31)
+#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK		0x20000000
+#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT		29
+#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL		(0x0 << 29)
+#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9			(0x1 << 29)
 #define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE			(0x1 << 28)
 #define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL			(0x1 << 27)
+#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_ENABLE__MASK		0x18000000
+#define GEN8_SAMPLER_DW0_LOD_PRECLAMP_ENABLE__SHIFT		27
 #define GEN6_SAMPLER_DW0_BASE_LOD__MASK				0x07c00000
 #define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT			22
 #define GEN6_SAMPLER_DW0_MIP_FILTER__MASK			0x00300000
@@ -263,6 +343,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_SAMPLER_DW0_LOD_BIAS__RADIX			6
 #define GEN6_SAMPLER_DW0_SHADOW_FUNC__MASK			0x00000007
 #define GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT			0
+#define GEN7_SAMPLER_DW0_LOD_BIAS__MASK				0x00003ffe
+#define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT			1
+#define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX			8
+#define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK			0x00000001
+#define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT			0
+#define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY			0x0
+#define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA				0x1
 
 #define GEN6_SAMPLER_DW1_MIN_LOD__MASK				0xffc00000
 #define GEN6_SAMPLER_DW1_MIN_LOD__SHIFT				22
@@ -281,10 +368,45 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_SAMPLER_DW1_R_WRAP__MASK				0x00000007
 #define GEN6_SAMPLER_DW1_R_WRAP__SHIFT				0
 
+#define GEN7_SAMPLER_DW1_MIN_LOD__MASK				0xfff00000
+#define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT				20
+#define GEN7_SAMPLER_DW1_MIN_LOD__RADIX				8
+#define GEN7_SAMPLER_DW1_MAX_LOD__MASK				0x000fff00
+#define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT				8
+#define GEN7_SAMPLER_DW1_MAX_LOD__RADIX				8
+#define GEN8_SAMPLER_DW1_CHROMAKEY_ENABLE			(0x1 << 7)
+#define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__MASK			0x00000060
+#define GEN8_SAMPLER_DW1_CHROMAKEY_INDEX__SHIFT			5
+#define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__MASK			0x00000010
+#define GEN8_SAMPLER_DW1_CHROMAKEY_MODE__SHIFT			4
+#define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK			0x0000000e
+#define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT			1
+#define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK			0x00000001
+#define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT			0
+#define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED		0x0
+#define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE			0x1
+
 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK		0xffffffe0
 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT		5
 #define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR			5
 
+#define GEN8_SAMPLER_DW2_SEP_FILTER_COEFF_TABLE_SIZE__MASK	0xc0000000
+#define GEN8_SAMPLER_DW2_SEP_FILTER_COEFF_TABLE_SIZE__SHIFT	30
+#define GEN8_SAMPLER_DW2_SEP_FILTER_WIDTH__MASK			0x30000000
+#define GEN8_SAMPLER_DW2_SEP_FILTER_WIDTH__SHIFT		28
+#define GEN8_SAMPLER_DW2_SEP_FILTER_HEIGHT__MASK		0x0c000000
+#define GEN8_SAMPLER_DW2_SEP_FILTER_HEIGHT__SHIFT		26
+#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__MASK		0x00ffffc0
+#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHIFT		6
+#define GEN8_SAMPLER_DW2_INDIRECT_STATE_ADDR__SHR		6
+#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_MODE			(0x1 << 4)
+#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_COEFF_SIZE		(0x1 << 3)
+#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_HALIGN			(0x1 << 2)
+#define GEN8_SAMPLER_DW2_FLEXIBLE_FILTER_VALIGN			(0x1 << 1)
+#define GEN8_SAMPLER_DW2_LOD_CLAMP_MAG_MODE			(0x1 << 0)
+
+#define GEN8_SAMPLER_DW3_NON_SEP_FILTER_FOOTPRINT_MASK__MASK	0xff000000
+#define GEN8_SAMPLER_DW3_NON_SEP_FILTER_FOOTPRINT_MASK__SHIFT	24
 #define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE			(0x1 << 25)
 #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK			0x01800000
 #define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT			23
@@ -298,61 +420,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_SAMPLER_DW3_V_MIN_ROUND				(0x1 << 15)
 #define GEN6_SAMPLER_DW3_R_MAG_ROUND				(0x1 << 14)
 #define GEN6_SAMPLER_DW3_R_MIN_ROUND				(0x1 << 13)
-#define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD			(0x1 << 0)
-
-
-#define GEN7_SAMPLER_DW0_DISABLE				(0x1 << 31)
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK		0x20000000
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT		29
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL		(0x0 << 29)
-#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9			(0x1 << 29)
-#define GEN7_SAMPLER_DW0_LOD_PRECLAMP_ENABLE			(0x1 << 28)
-#define GEN7_SAMPLER_DW0_BASE_LOD__MASK				0x07c00000
-#define GEN7_SAMPLER_DW0_BASE_LOD__SHIFT			22
-#define GEN7_SAMPLER_DW0_MIP_FILTER__MASK			0x00300000
-#define GEN7_SAMPLER_DW0_MIP_FILTER__SHIFT			20
-#define GEN7_SAMPLER_DW0_MAG_FILTER__MASK			0x000e0000
-#define GEN7_SAMPLER_DW0_MAG_FILTER__SHIFT			17
-#define GEN7_SAMPLER_DW0_MIN_FILTER__MASK			0x0001c000
-#define GEN7_SAMPLER_DW0_MIN_FILTER__SHIFT			14
-#define GEN7_SAMPLER_DW0_LOD_BIAS__MASK				0x00003ffe
-#define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT			1
-#define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX			8
-#define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK			0x00000001
-#define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT			0
-#define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY			0x0
-#define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA				0x1
-
-#define GEN7_SAMPLER_DW1_MIN_LOD__MASK				0xfff00000
-#define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT				20
-#define GEN7_SAMPLER_DW1_MIN_LOD__RADIX				8
-#define GEN7_SAMPLER_DW1_MAX_LOD__MASK				0x000fff00
-#define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT				8
-#define GEN7_SAMPLER_DW1_MAX_LOD__RADIX				8
-#define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK			0x0000000e
-#define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT			1
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK			0x00000001
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT			0
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED		0x0
-#define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE			0x1
-
-#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK		0xffffffe0
-#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT		5
-#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR			5
-
-#define GEN7_SAMPLER_DW3_CHROMAKEY_ENABLE			(0x1 << 25)
-#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__MASK			0x01800000
-#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT			23
-#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__MASK			0x00400000
-#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT			22
-#define GEN7_SAMPLER_DW3_MAX_ANISO__MASK			0x00380000
-#define GEN7_SAMPLER_DW3_MAX_ANISO__SHIFT			19
-#define GEN7_SAMPLER_DW3_U_MAG_ROUND				(0x1 << 18)
-#define GEN7_SAMPLER_DW3_U_MIN_ROUND				(0x1 << 17)
-#define GEN7_SAMPLER_DW3_V_MAG_ROUND				(0x1 << 16)
-#define GEN7_SAMPLER_DW3_V_MIN_ROUND				(0x1 << 15)
-#define GEN7_SAMPLER_DW3_R_MAG_ROUND				(0x1 << 14)
-#define GEN7_SAMPLER_DW3_R_MIN_ROUND				(0x1 << 13)
 #define GEN7_SAMPLER_DW3_TRIQUAL__MASK				0x00001800
 #define GEN7_SAMPLER_DW3_TRIQUAL__SHIFT				11
 #define GEN7_SAMPLER_DW3_TRIQUAL_FULL				(0x0 << 11)
@@ -366,6 +433,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SAMPLER_DW3_V_WRAP__SHIFT				3
 #define GEN7_SAMPLER_DW3_R_WRAP__MASK				0x00000007
 #define GEN7_SAMPLER_DW3_R_WRAP__SHIFT				0
+#define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD			(0x1 << 0)
 
 
 #endif /* GEN_RENDER_DYNAMIC_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h
index 3590c795a38..55d830bad32 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_media.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -45,15 +45,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION			(0x1 << 11)
 #define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION			(0x1 << 7)
 
+#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK			0x0000001c
+#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT			2
 #define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK			0xffffffe0
 #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT			5
 #define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR				5
-#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK			0x0000001c
-#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT			2
 
-#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__MASK			0x0000ffe0
-#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHIFT			5
-#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHR			5
 #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK			0x0000001f
 #define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT			0
 
@@ -85,16 +82,61 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT	0
 
 
-#define GEN6_MEDIA_VFE_STATE__SIZE				8
+
+#define GEN8_IDRT_DW0_KERNEL_ADDR__MASK				0xffffffc0
+#define GEN8_IDRT_DW0_KERNEL_ADDR__SHIFT			6
+#define GEN8_IDRT_DW0_KERNEL_ADDR__SHR				6
+
+
+#define GEN8_IDRT_DW2_THREAD_PREEMPTION_DISABLE			(0x1 << 20)
+#define GEN8_IDRT_DW2_DENORM__MASK				0x00080000
+#define GEN8_IDRT_DW2_DENORM__SHIFT				19
+#define GEN8_IDRT_DW2_DENORM_FTZ				(0x0 << 19)
+#define GEN8_IDRT_DW2_DENORM_RET				(0x1 << 19)
+#define GEN8_IDRT_DW2_SPF					(0x1 << 18)
+#define GEN8_IDRT_DW2_PRIORITY_HIGH				(0x1 << 17)
+#define GEN8_IDRT_DW2_FP_MODE_ALT				(0x1 << 16)
+#define GEN8_IDRT_DW2_ILLEGAL_CODE_EXCEPTION			(0x1 << 13)
+#define GEN8_IDRT_DW2_MASK_STACK_EXCEPTION			(0x1 << 11)
+#define GEN8_IDRT_DW2_SOFTWARE_EXCEPTION			(0x1 << 7)
+
+#define GEN8_IDRT_DW3_SAMPLER_COUNT__MASK			0x0000001c
+#define GEN8_IDRT_DW3_SAMPLER_COUNT__SHIFT			2
+#define GEN8_IDRT_DW3_SAMPLER_ADDR__MASK			0xffffffe0
+#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHIFT			5
+#define GEN8_IDRT_DW3_SAMPLER_ADDR__SHR				5
+
+#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__MASK			0x0000001f
+#define GEN8_IDRT_DW4_BINDING_TABLE_SIZE__SHIFT			0
+
+#define GEN8_IDRT_DW5_CURBE_READ_LEN__MASK			0xffff0000
+#define GEN8_IDRT_DW5_CURBE_READ_LEN__SHIFT			16
+
+#define GEN8_IDRT_DW6_ROUNDING_MODE__MASK			0x00c00000
+#define GEN8_IDRT_DW6_ROUNDING_MODE__SHIFT			22
+#define GEN8_IDRT_DW6_ROUNDING_MODE_RTNE			(0x0 << 22)
+#define GEN8_IDRT_DW6_ROUNDING_MODE_RU				(0x1 << 22)
+#define GEN8_IDRT_DW6_ROUNDING_MODE_RD				(0x2 << 22)
+#define GEN8_IDRT_DW6_ROUNDING_MODE_RTZ				(0x3 << 22)
+#define GEN8_IDRT_DW6_BARRIER_ENABLE				(0x1 << 21)
+#define GEN8_IDRT_DW6_SLM_SIZE__MASK				0x001f0000
+#define GEN8_IDRT_DW6_SLM_SIZE__SHIFT				16
+#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__MASK			0x000000ff
+#define GEN8_IDRT_DW6_THREAD_GROUP_SIZE__SHIFT			0
+
+#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__MASK		0x000000ff
+#define GEN8_IDRT_DW7_CROSS_THREAD_CURBE_READ_LEN__SHIFT	0
+
+#define GEN6_MEDIA_VFE_STATE__SIZE				9
 
 
-#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK				0xfffffc00
-#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT			10
-#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR				10
 #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK			0x000000f0
 #define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT			4
 #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK		0x0000000f
 #define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT		0
+#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK				0xfffffc00
+#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT			10
+#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR				10
 
 #define GEN6_VFE_DW2_MAX_THREADS__MASK				0xffff0000
 #define GEN6_VFE_DW2_MAX_THREADS__SHIFT				16
@@ -128,39 +170,44 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK			0x000000ff
 #define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT			0
 
-#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__MASK			0xf0000000
-#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__SHIFT		28
-#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__MASK			0x0f000000
-#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__SHIFT		24
-#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__MASK			0x00f00000
-#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__SHIFT		20
-#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__MASK			0x000f0000
-#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__SHIFT		16
-#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__MASK			0x0000f000
-#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__SHIFT		12
-#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__MASK			0x00000f00
-#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__SHIFT		8
-#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__MASK			0x000000f0
-#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__SHIFT		4
-#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__MASK			0x0000000f
-#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__SHIFT		0
-
-#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__MASK			0xf0000000
-#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__SHIFT		28
-#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__MASK			0x0f000000
-#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__SHIFT		24
-#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__MASK			0x00f00000
-#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__SHIFT		20
-#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__MASK			0x000f0000
-#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__SHIFT		16
-#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__MASK			0x0000f000
-#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__SHIFT		12
-#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__MASK			0x00000f00
-#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__SHIFT		8
-#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__MASK			0x000000f0
-#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__SHIFT		4
-#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__MASK			0x0000000f
-#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__SHIFT		0
+
+
+
+#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__MASK			0x000000f0
+#define GEN8_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT			4
+#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK		0x0000000f
+#define GEN8_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT		0
+#define GEN8_VFE_DW1_SCRATCH_ADDR__MASK				0xfffffc00
+#define GEN8_VFE_DW1_SCRATCH_ADDR__SHIFT			10
+#define GEN8_VFE_DW1_SCRATCH_ADDR__SHR				10
+
+
+#define GEN8_VFE_DW3_MAX_THREADS__MASK				0xffff0000
+#define GEN8_VFE_DW3_MAX_THREADS__SHIFT				16
+#define GEN8_VFE_DW3_URB_ENTRY_COUNT__MASK			0x0000ff00
+#define GEN8_VFE_DW3_URB_ENTRY_COUNT__SHIFT			8
+#define GEN8_VFE_DW3_RESET_GATEWAY_TIMER			(0x1 << 7)
+#define GEN8_VFE_DW3_BYPASS_GATEWAY_CONTROL			(0x1 << 6)
+
+#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__MASK			0x00000003
+#define GEN8_VFE_DW4_HALF_SLICE_DISABLE__SHIFT			0
+#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_NONE			0x0
+#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_23			0x1
+#define GEN8_VFE_DW4_HALF_SLICE_DISABLE_123			0x3
+
+#define GEN8_VFE_DW5_URB_ENTRY_SIZE__MASK			0xffff0000
+#define GEN8_VFE_DW5_URB_ENTRY_SIZE__SHIFT			16
+#define GEN8_VFE_DW5_CURBE_SIZE__MASK				0x0000ffff
+#define GEN8_VFE_DW5_CURBE_SIZE__SHIFT				0
+
+#define GEN8_VFE_DW6_SCOREBOARD_ENABLE				(0x1 << 31)
+#define GEN8_VFE_DW6_SCOREBOARD_TYPE__MASK			0x40000000
+#define GEN8_VFE_DW6_SCOREBOARD_TYPE__SHIFT			30
+#define GEN8_VFE_DW6_SCOREBOARD_TYPE_STALLING			(0x0 << 30)
+#define GEN8_VFE_DW6_SCOREBOARD_TYPE_NON_STALLING		(0x1 << 30)
+#define GEN8_VFE_DW6_SCOREBOARD_MASK__MASK			0x000000ff
+#define GEN8_VFE_DW6_SCOREBOARD_MASK__SHIFT			0
+
 
 #define GEN6_MEDIA_CURBE_LOAD__SIZE				4
 
@@ -169,6 +216,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_CURBE_LOAD_DW2_LEN__MASK				0x0001ffff
 #define GEN6_CURBE_LOAD_DW2_LEN__SHIFT				0
 
+#define GEN6_CURBE_LOAD_DW3_ADDR__MASK				0xffffffe0
+#define GEN6_CURBE_LOAD_DW3_ADDR__SHIFT				5
+#define GEN6_CURBE_LOAD_DW3_ADDR__SHR				5
 
 #define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE		4
 
@@ -177,6 +227,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN6_IDRT_LOAD_DW2_LEN__MASK				0x0001ffff
 #define GEN6_IDRT_LOAD_DW2_LEN__SHIFT				0
 
+#define GEN6_IDRT_LOAD_DW3_ADDR__MASK				0xffffffe0
+#define GEN6_IDRT_LOAD_DW3_ADDR__SHIFT				5
+#define GEN6_IDRT_LOAD_DW3_ADDR__SHR				5
 
 #define GEN6_MEDIA_STATE_FLUSH__SIZE				2
 
@@ -192,7 +245,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK			0x0000003f
 #define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT			0
 
-#define GEN7_GPGPU_WALKER__SIZE					11
+#define GEN7_GPGPU_WALKER__SIZE					15
 
 #define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE			(0x1 << 10)
 #define GEN7_GPGPU_DW0_PREDICATE_ENABLE				(0x1 << 8)
@@ -221,4 +274,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 
 
+#define GEN8_GPGPU_DW0_INDIRECT_PARAM_ENABLE			(0x1 << 10)
+#define GEN8_GPGPU_DW0_PREDICATE_ENABLE				(0x1 << 8)
+
+#define GEN8_GPGPU_DW1_IDRT_OFFSET__MASK			0x0000003f
+#define GEN8_GPGPU_DW1_IDRT_OFFSET__SHIFT			0
+
+
+#define GEN8_GPGPU_DW3_INDIRECT_ADDR__MASK			0xffffffe0
+#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHIFT			5
+#define GEN8_GPGPU_DW3_INDIRECT_ADDR__SHR			5
+
+#define GEN8_GPGPU_DW4_SIMD_SIZE__MASK				0xc0000000
+#define GEN8_GPGPU_DW4_SIMD_SIZE__SHIFT				30
+#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD8				(0x0 << 30)
+#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD16				(0x1 << 30)
+#define GEN8_GPGPU_DW4_SIMD_SIZE_SIMD32				(0x2 << 30)
+#define GEN8_GPGPU_DW4_THREAD_MAX_Z__MASK			0x003f0000
+#define GEN8_GPGPU_DW4_THREAD_MAX_Z__SHIFT			16
+#define GEN8_GPGPU_DW4_THREAD_MAX_Y__MASK			0x00003f00
+#define GEN8_GPGPU_DW4_THREAD_MAX_Y__SHIFT			8
+#define GEN8_GPGPU_DW4_THREAD_MAX_X__MASK			0x0000003f
+#define GEN8_GPGPU_DW4_THREAD_MAX_X__SHIFT			0
+
+
+
+
+
+
+
+
+
+
+
+
 #endif /* GEN_RENDER_MEDIA_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
index 7d9dfdbd1fb..f5ee27aa3e7 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
@@ -7,7 +7,7 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
 https://github.com/olvaffe/envytools/
 git clone https://github.com/olvaffe/envytools.git
 
-Copyright (C) 2014 by the following authors:
+Copyright (C) 2014-2015 by the following authors:
 - Chia-I Wu <[email protected]> (olv)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -261,6 +261,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFTYPE_STRBUF					0x5
 #define GEN6_SURFTYPE_NULL					0x7
 #define GEN6_TILING_NONE					0x0
+#define GEN8_TILING_W						0x1
 #define GEN6_TILING_X						0x2
 #define GEN6_TILING_Y						0x3
 #define GEN7_CLEAR_COLOR_ZERO					0x0
@@ -271,7 +272,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN75_SCS_GREEN						0x5
 #define GEN75_SCS_BLUE						0x6
 #define GEN75_SCS_ALPHA						0x7
-#define GEN6_SURFACE_STATE__SIZE				8
+#define GEN6_SURFACE_STATE__SIZE				16
 
 #define GEN6_SURFACE_DW0_TYPE__MASK				0xe0000000
 #define GEN6_SURFACE_DW0_TYPE__SHIFT				29
@@ -325,12 +326,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN6_SURFACE_DW5_X_OFFSET__MASK				0xfe000000
 #define GEN6_SURFACE_DW5_X_OFFSET__SHIFT			25
+#define GEN6_SURFACE_DW5_X_OFFSET__SHR				2
 #define GEN6_SURFACE_DW5_VALIGN__MASK				0x01000000
 #define GEN6_SURFACE_DW5_VALIGN__SHIFT				24
 #define GEN6_SURFACE_DW5_VALIGN_2				(0x0 << 24)
 #define GEN6_SURFACE_DW5_VALIGN_4				(0x1 << 24)
 #define GEN6_SURFACE_DW5_Y_OFFSET__MASK				0x00f00000
 #define GEN6_SURFACE_DW5_Y_OFFSET__SHIFT			20
+#define GEN6_SURFACE_DW5_Y_OFFSET__SHR				1
 #define GEN6_SURFACE_DW5_MOCS__MASK				0x000f0000
 #define GEN6_SURFACE_DW5_MOCS__SHIFT				16
 
@@ -344,6 +347,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW0_VALIGN__SHIFT				16
 #define GEN7_SURFACE_DW0_VALIGN_2				(0x0 << 16)
 #define GEN7_SURFACE_DW0_VALIGN_4				(0x1 << 16)
+#define GEN8_SURFACE_DW0_VALIGN_8				(0x2 << 16)
+#define GEN8_SURFACE_DW0_VALIGN_16				(0x3 << 16)
 #define GEN7_SURFACE_DW0_HALIGN__MASK				0x00008000
 #define GEN7_SURFACE_DW0_HALIGN__SHIFT				15
 #define GEN7_SURFACE_DW0_HALIGN_4				(0x0 << 15)
@@ -356,6 +361,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW0_ARYSPC__SHIFT				10
 #define GEN7_SURFACE_DW0_ARYSPC_FULL				(0x0 << 10)
 #define GEN7_SURFACE_DW0_ARYSPC_LOD0				(0x1 << 10)
+#define GEN8_SURFACE_DW0_HALIGN__MASK				0x0000c000
+#define GEN8_SURFACE_DW0_HALIGN__SHIFT				14
+#define GEN8_SURFACE_DW0_HALIGN_4				(0x1 << 14)
+#define GEN8_SURFACE_DW0_HALIGN_8				(0x2 << 14)
+#define GEN8_SURFACE_DW0_HALIGN_16				(0x3 << 14)
+#define GEN8_SURFACE_DW0_TILING__MASK				0x00003000
+#define GEN8_SURFACE_DW0_TILING__SHIFT				12
+#define GEN8_SURFACE_DW0_VSTRIDE				(0x1 << 11)
+#define GEN8_SURFACE_DW0_VSTRIDE_OFFSET				(0x1 << 10)
+#define GEN8_SURFACE_DW0_SAMPLER_L2_BYPASS_MODE			(0x1 << 9)
 #define GEN7_SURFACE_DW0_RENDER_CACHE_RW			(0x1 << 8)
 #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK	0x000000c0
 #define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT	6
@@ -363,6 +378,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT		0
 
 
+#define GEN8_SURFACE_DW1_MOCS__MASK				0x7f000000
+#define GEN8_SURFACE_DW1_MOCS__SHIFT				24
+#define GEN8_SURFACE_DW1_BASE_LOD__MASK				0x00f80000
+#define GEN8_SURFACE_DW1_BASE_LOD__SHIFT			19
+#define GEN8_SURFACE_DW1_QPITCH__MASK				0x00007fff
+#define GEN8_SURFACE_DW1_QPITCH__SHIFT				0
+
 #define GEN7_SURFACE_DW2_HEIGHT__MASK				0x3fff0000
 #define GEN7_SURFACE_DW2_HEIGHT__SHIFT				16
 #define GEN7_SURFACE_DW2_WIDTH__MASK				0x00003fff
@@ -391,8 +413,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__MASK			0x00000038
 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT		3
 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1			(0x0 << 3)
+#define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_2			(0x1 << 3)
 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4			(0x2 << 3)
 #define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8			(0x3 << 3)
+#define GEN8_SURFACE_DW4_MULTISAMPLECOUNT_16			(0x4 << 3)
 #define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK			0x00000007
 #define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT			0
 #define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__MASK		0x07ffffff
@@ -400,15 +424,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define GEN7_SURFACE_DW5_X_OFFSET__MASK				0xfe000000
 #define GEN7_SURFACE_DW5_X_OFFSET__SHIFT			25
+#define GEN7_SURFACE_DW5_X_OFFSET__SHR				2
 #define GEN7_SURFACE_DW5_Y_OFFSET__MASK				0x00f00000
 #define GEN7_SURFACE_DW5_Y_OFFSET__SHIFT			20
+#define GEN7_SURFACE_DW5_Y_OFFSET__SHR				1
 #define GEN7_SURFACE_DW5_MOCS__MASK				0x000f0000
 #define GEN7_SURFACE_DW5_MOCS__SHIFT				16
+#define GEN8_SURFACE_DW5_Y_OFFSET__MASK				0x00e00000
+#define GEN8_SURFACE_DW5_Y_OFFSET__SHIFT			21
+#define GEN8_SURFACE_DW5_Y_OFFSET__SHR				1
+#define GEN8_SURFACE_DW5_CUBE_EWA				(0x1 << 20)
+#define GEN8_SURFACE_DW5_COHERENCY_TYPE				(0x1 << 14)
 #define GEN7_SURFACE_DW5_MIN_LOD__MASK				0x000000f0
 #define GEN7_SURFACE_DW5_MIN_LOD__SHIFT				4
 #define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK			0x0000000f
 #define GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT			0
 
+#define GEN8_SURFACE_DW6_SEPARATE_UV_ENABLE			(0x1 << 31)
 #define GEN7_SURFACE_DW6_UV_X_OFFSET__MASK			0x3fff0000
 #define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT			16
 #define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK			0x00003fff
@@ -416,13 +448,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW6_MCS_ADDR__MASK				0xfffff000
 #define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT			12
 #define GEN7_SURFACE_DW6_MCS_ADDR__SHR				12
-#define GEN7_SURFACE_DW6_MCS_PITCH__MASK			0x00000ff8
-#define GEN7_SURFACE_DW6_MCS_PITCH__SHIFT			3
+#define GEN8_SURFACE_DW6_AUX_QPITCH__MASK			0x7fff0000
+#define GEN8_SURFACE_DW6_AUX_QPITCH__SHIFT			16
+#define GEN7_SURFACE_DW6_AUX_PITCH__MASK			0x00000ff8
+#define GEN7_SURFACE_DW6_AUX_PITCH__SHIFT			3
 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK		0xffffffc0
 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT		6
 #define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR		6
-#define GEN7_SURFACE_DW6_APPEND_COUNTER_ENABLE			(0x1 << 1)
-#define GEN7_SURFACE_DW6_MCS_ENABLE				(0x1 << 0)
+#define GEN7_SURFACE_DW6_AUX_MODE__MASK				0x00000007
+#define GEN7_SURFACE_DW6_AUX_MODE__SHIFT			0
+#define GEN7_SURFACE_DW6_AUX_MODE_NONE				0x0
+#define GEN7_SURFACE_DW6_AUX_MODE_MCS				0x1
+#define GEN7_SURFACE_DW6_AUX_MODE_APPEND			0x2
+#define GEN8_SURFACE_DW6_AUX_MODE_HIZ				0x3
 
 #define GEN7_SURFACE_DW7_CC_R__MASK				0x80000000
 #define GEN7_SURFACE_DW7_CC_R__SHIFT				31
@@ -443,11 +481,23 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GEN7_SURFACE_DW7_RES_MIN_LOD__MASK			0x00000fff
 #define GEN7_SURFACE_DW7_RES_MIN_LOD__SHIFT			0
 
+
+
+
+
+
+
+
+
 #define GEN6_BINDING_TABLE_STATE__SIZE				256
 
-#define GEN6_BINDING_TABLE_SURFACE_ADDR__MASK			0xffffffe0
-#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHIFT			5
-#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHR			5
+#define GEN6_BINDING_TABLE_DW_ADDR__MASK			0xffffffe0
+#define GEN6_BINDING_TABLE_DW_ADDR__SHIFT			5
+#define GEN6_BINDING_TABLE_DW_ADDR__SHR				5
+
+#define GEN8_BINDING_TABLE_DW_ADDR__MASK			0xffffffc0
+#define GEN8_BINDING_TABLE_DW_ADDR__SHIFT			6
+#define GEN8_BINDING_TABLE_DW_ADDR__SHR				6
 
 
 #endif /* GEN_RENDER_SURFACE_XML */
diff --git a/src/gallium/drivers/ilo/genhw/genhw.h b/src/gallium/drivers/ilo/genhw/genhw.h
index 4c2cb57c359..9e05bf5beca 100644
--- a/src/gallium/drivers/ilo/genhw/genhw.h
+++ b/src/gallium/drivers/ilo/genhw/genhw.h
@@ -54,6 +54,7 @@
 #define GEN6_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN6, op)
 #define GEN7_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN7, op)
 #define GEN75_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN75, op)
+#define GEN8_RENDER_CMD(subtype, op) GEN_RENDER_CMD(subtype, GEN8, op)
 
 #define GEN_EXTRACT(bits, field) (((bits) & field ## __MASK) >> field ## __SHIFT)
 #define GEN_SHIFT32(bits, field) gen_shift32(bits, field ## __MASK, field ## __SHIFT)
@@ -177,6 +178,36 @@ gen_get_hsw_gt(int devid)
 }
 
 static inline bool
+gen_is_bdw(int devid)
+{
+   return (devid == 0x1602 || /* GT1 ULT */
+           devid == 0x1606 || /* GT1 ULT */
+           devid == 0x160a || /* GT1 server */
+           devid == 0x160b || /* GT1 Iris */
+           devid == 0x160d || /* GT1 workstation */
+           devid == 0x160e || /* GT1 ULX */
+           devid == 0x1612 || /* GT2 */
+           devid == 0x1616 ||
+           devid == 0x161a ||
+           devid == 0x161b ||
+           devid == 0x161d ||
+           devid == 0x161e ||
+           devid == 0x1622 || /* GT3 */
+           devid == 0x1626 ||
+           devid == 0x162a ||
+           devid == 0x162b ||
+           devid == 0x162d ||
+           devid == 0x162e);
+}
+
+static inline int
+gen_get_bdw_gt(int devid)
+{
+   assert(gen_is_bdw(devid));
+   return ((devid & 0x30) >> 4) + 1;
+}
+
+static inline bool
 gen_is_vlv(int devid)
 {
    return (devid == 0x0f30 ||
@@ -188,9 +219,19 @@ gen_is_vlv(int devid)
 }
 
 static inline bool
+gen_is_chv(int devid)
+{
+   return (devid == 0x22b0 ||
+           devid == 0x22b1 ||
+           devid == 0x22b2 ||
+           devid == 0x22b3);
+}
+
+static inline bool
 gen_is_atom(int devid)
 {
-   return gen_is_vlv(devid);
+   return (gen_is_vlv(devid) ||
+           gen_is_chv(devid));
 }
 
 static inline bool