i965g: update to similiar gen stuff as i965

33 files changed, 173 insertions, 151 deletions

diff --git a/src/gallium/drivers/i965/brw_batchbuffer.c b/src/gallium/drivers/i965/brw_batchbuffer.c
index e80067f3b19..3c935792465 100644
--- a/src/gallium/drivers/i965/brw_batchbuffer.c
+++ b/src/gallium/drivers/i965/brw_batchbuffer.c
@@ -64,13 +64,11 @@ brw_batchbuffer_reset(struct brw_batchbuffer *batch)
 }
 
 struct brw_batchbuffer *
-brw_batchbuffer_alloc(struct brw_winsys_screen *sws,
-                      struct brw_chipset chipset)
+brw_batchbuffer_alloc(struct brw_winsys_screen *sws)
 {
    struct brw_batchbuffer *batch = CALLOC_STRUCT(brw_batchbuffer);
 
    batch->sws = sws;
-   batch->chipset = chipset;
    brw_batchbuffer_reset(batch);
 
    return batch;
diff --git a/src/gallium/drivers/i965/brw_batchbuffer.h b/src/gallium/drivers/i965/brw_batchbuffer.h
index 6ca9f617f5e..6ecb91857dd 100644
--- a/src/gallium/drivers/i965/brw_batchbuffer.h
+++ b/src/gallium/drivers/i965/brw_batchbuffer.h
@@ -26,7 +26,6 @@ struct brw_batchbuffer {
 
    struct brw_winsys_screen *sws;
    struct brw_winsys_buffer *buf;
-   struct brw_chipset chipset;
 
    /**
     * Values exported to speed up the writing the batchbuffer,
@@ -47,8 +46,8 @@ struct brw_batchbuffer {
    /*@}*/
 };
 
-struct brw_batchbuffer *brw_batchbuffer_alloc( struct brw_winsys_screen *sws,
-                                               struct brw_chipset chipset );
+struct brw_batchbuffer *brw_batchbuffer_alloc( struct brw_winsys_screen *sws );
+
 
 void brw_batchbuffer_free(struct brw_batchbuffer *batch);
 
diff --git a/src/gallium/drivers/i965/brw_clip.c b/src/gallium/drivers/i965/brw_clip.c
index ccba205e8c7..66b13ea58e2 100644
--- a/src/gallium/drivers/i965/brw_clip.c
+++ b/src/gallium/drivers/i965/brw_clip.c
@@ -66,16 +66,14 @@ compile_clip_prog( struct brw_context *brw,
 
    c.func.single_program_flow = 1;
 
-   c.chipset = brw->chipset;
    c.key = *key;
-   c.need_ff_sync = c.chipset.is_igdng;
 
    /* Need to locate the two positions present in vertex + header.
     * These are currently hardcoded:
     */
    c.header_position_offset = ATTR_SIZE;
 
-   if (c.chipset.is_igdng)
+   if (brw->gen == 5)
        delta = 3 * REG_SIZE;
    else
        delta = REG_SIZE;
@@ -97,7 +95,7 @@ compile_clip_prog( struct brw_context *brw,
    if (c.key.output_edgeflag != BRW_OUTPUT_NOT_PRESENT)
       c.offset_edgeflag = delta + c.key.output_edgeflag * ATTR_SIZE;
    
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
    else
        c.nr_regs = (c.key.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
diff --git a/src/gallium/drivers/i965/brw_clip.h b/src/gallium/drivers/i965/brw_clip.h
index 80e3a11a370..f123b73c063 100644
--- a/src/gallium/drivers/i965/brw_clip.h
+++ b/src/gallium/drivers/i965/brw_clip.h
@@ -125,12 +125,10 @@ struct brw_clip_compile {
    GLuint last_tmp;
 
    GLboolean need_direction;
-   struct brw_chipset chipset;
 
    GLuint last_mrf;
 
    GLuint header_position_offset;
-   GLboolean need_ff_sync;
 
    GLuint nr_color_attrs;
    GLuint offset_color0;
diff --git a/src/gallium/drivers/i965/brw_clip_line.c b/src/gallium/drivers/i965/brw_clip_line.c
index 66caadc4d53..4ed7362171b 100644
--- a/src/gallium/drivers/i965/brw_clip_line.c
+++ b/src/gallium/drivers/i965/brw_clip_line.c
@@ -32,6 +32,7 @@
 #include "util/u_debug.h"
 
 #include "brw_defines.h"
+#include "brw_context.h"
 #include "brw_eu.h"
 #include "brw_clip.h"
 
@@ -41,7 +42,7 @@
 static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
 {
    GLuint i = 0,j;
-
+   struct brw_context *brw = c->func.brw;
    /* Register usage is static, precompute here:
     */
    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
@@ -79,7 +80,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
       i++;
    }
 
-   if (c->need_ff_sync) {
+   if (brw->needs_ff_sync) {
       c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
       i++;
    }
@@ -120,6 +121,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
 static void clip_and_emit_line( struct brw_clip_compile *c )
 {
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    struct brw_indirect vtx0     = brw_indirect(0, 0);
    struct brw_indirect vtx1      = brw_indirect(1, 0);
    struct brw_indirect newvtx0   = brw_indirect(2, 0);
@@ -146,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    brw_clip_init_clipmask(c);
 
    /* -ve rhw workaround */
-   if (c->chipset.is_965) {
+   if (brw->has_negative_rhw_bug) {
       brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
       brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
               brw_imm_ud(1<<20));
@@ -183,7 +185,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
               * Both can be negative on GM965/G965 due to RHW workaround
               * if so, this object should be rejected.
               */
-             if (c->chipset.is_965) {
+	     if (brw->has_negative_rhw_bug) {
                  brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
                  is_neg2 = brw_IF(p, BRW_EXECUTE_1);
                  {
@@ -208,7 +210,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
 
              /* If both are positive, do nothing */
              /* Only on GM965/G965 */
-             if (c->chipset.is_965) {
+	     if (brw->has_negative_rhw_bug) {
                  brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
                  is_neg2 = brw_IF(p, BRW_EXECUTE_1);
              }
@@ -223,7 +225,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
                  brw_set_predicate_control(p, BRW_PREDICATE_NONE);
              }
 
-             if (c->chipset.is_965) {
+	     if (brw->has_negative_rhw_bug) {
                  brw_ENDIF(p, is_neg2);
              }
          }
diff --git a/src/gallium/drivers/i965/brw_clip_state.c b/src/gallium/drivers/i965/brw_clip_state.c
index 5c3ccfd8d0d..f56edf3177c 100644
--- a/src/gallium/drivers/i965/brw_clip_state.c
+++ b/src/gallium/drivers/i965/brw_clip_state.c
@@ -109,7 +109,7 @@ clip_unit_create_from_key(struct brw_context *brw,
       /* Although up to 16 concurrent Clip threads are allowed on IGDNG, 
        * only 2 threads can output VUEs at a time.
        */
-      if (BRW_IS_IGDNG(brw))
+      if (brw->gen == 5)
          clip.thread4.max_threads = 16 - 1;        
       else
          clip.thread4.max_threads = 2 - 1;
@@ -134,7 +134,7 @@ clip_unit_create_from_key(struct brw_context *brw,
    clip.clip5.api_mode = BRW_CLIP_API_OGL;
    clip.clip5.clip_mode = key->clip_mode;
 
-   if (BRW_IS_G4X(brw))
+   if (brw->is_g4x)
       clip.clip5.negative_w_clip_test = 1;
 
    clip.clip6.clipper_viewport_state_ptr = 0;
diff --git a/src/gallium/drivers/i965/brw_clip_tri.c b/src/gallium/drivers/i965/brw_clip_tri.c
index 069524bc14f..7d400e6028b 100644
--- a/src/gallium/drivers/i965/brw_clip_tri.c
+++ b/src/gallium/drivers/i965/brw_clip_tri.c
@@ -30,6 +30,7 @@
   */
 
 #include "brw_defines.h"
+#include "brw_context.h"
 #include "brw_eu.h"
 #include "brw_clip.h"
 
@@ -43,6 +44,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
 			      GLuint nr_verts )
 {
    GLuint i = 0,j;
+   struct brw_context *brw = c->func.brw;
 
    /* Register usage is static, precompute here:
     */
@@ -69,7 +71,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
       for (j = 0; j < 3; j++) {
 	 GLuint delta = c->key.nr_attrs*16 + 32;
 
-         if (c->chipset.is_igdng)
+         if (brw->gen == 5)
              delta = c->key.nr_attrs * 16 + 32 * 3;
 
 	 brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
@@ -110,7 +112,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
       i++;
    }
 
-   if (c->need_ff_sync) {
+   if (brw->needs_ff_sync) {
       c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
       i++;
    }
@@ -563,7 +565,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
 
    /* if -ve rhw workaround bit is set, 
       do cliptest */
-   if (c->chipset.is_965) {
+   if (p->brw->has_negative_rhw_bug) {
       brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
       brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
               brw_imm_ud(1<<20));
diff --git a/src/gallium/drivers/i965/brw_clip_util.c b/src/gallium/drivers/i965/brw_clip_util.c
index 23e51ee9bcd..5713f25da7c 100644
--- a/src/gallium/drivers/i965/brw_clip_util.c
+++ b/src/gallium/drivers/i965/brw_clip_util.c
@@ -31,6 +31,7 @@
 
 
 #include "brw_defines.h"
+#include "brw_context.h"
 #include "brw_eu.h"
 #include "brw_clip.h"
 
@@ -126,6 +127,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
 			     GLboolean force_edgeflag)
 {
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    struct brw_reg tmp = get_tmp(c);
    GLuint i;
 
@@ -142,7 +144,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
    for (i = 0; i < c->key.nr_attrs; i++) {
       GLuint delta = i*16 + 32;
 
-      if (c->chipset.is_igdng)
+      if (brw->gen == 5)
           delta = i * 16 + 32 * 3;
 
       if (delta == c->offset_edgeflag) {
@@ -176,7 +178,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
    if (i & 1) {
       GLuint delta = i*16 + 32;
 
-      if (c->chipset.is_igdng)
+      if (brw->gen == 5)
           delta = i * 16 + 32 * 3;
 
       brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
@@ -350,7 +352,8 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
 
 void brw_clip_ff_sync(struct brw_clip_compile *c)
 {
-    if (c->need_ff_sync) {
+    struct brw_context *brw = c->func.brw;
+    if (brw->needs_ff_sync) {
         struct brw_compile *p = &c->func;
         struct brw_instruction *need_ff_sync;
 
@@ -379,7 +382,8 @@ void brw_clip_ff_sync(struct brw_clip_compile *c)
 
 void brw_clip_init_ff_sync(struct brw_clip_compile *c)
 {
-    if (c->need_ff_sync) {
+    struct brw_context *brw = c->func.brw;
+    if (brw->needs_ff_sync) {
 	struct brw_compile *p = &c->func;
         
         brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));
diff --git a/src/gallium/drivers/i965/brw_context.c b/src/gallium/drivers/i965/brw_context.c
index a2736f783d5..41a468a32f0 100644
--- a/src/gallium/drivers/i965/brw_context.c
+++ b/src/gallium/drivers/i965/brw_context.c
@@ -107,7 +107,7 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
 					void *priv)
 {
    struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context);
-
+   struct brw_screen *brs = brw_screen(screen);
    if (!brw) {
       debug_printf("%s: failed to alloc context\n", __FUNCTION__);
       return NULL;
@@ -117,7 +117,10 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
    brw->base.priv = priv;
    brw->base.destroy = brw_destroy_context;
    brw->sws = brw_screen(screen)->sws;
-   brw->chipset = brw_screen(screen)->chipset;
+   brw->is_g4x = brs->is_g4x;
+   brw->needs_ff_sync = brs->needs_ff_sync;
+   brw->has_negative_rhw_bug = brs->has_negative_rhw_bug;
+   brw->gen = brs->gen;
 
    brw_init_resource_functions( brw );
    brw_pipe_blend_init( brw );
@@ -145,7 +148,7 @@ struct pipe_context *brw_create_context(struct pipe_screen *screen,
 
    make_empty_list(&brw->query.active_head);
 
-   brw->batch = brw_batchbuffer_alloc( brw->sws, brw->chipset );
+   brw->batch = brw_batchbuffer_alloc( brw->sws );
    if (brw->batch == NULL)
       goto fail;
 
diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h
index d927f382d5f..45fc26dd7d8 100644
--- a/src/gallium/drivers/i965/brw_context.h
+++ b/src/gallium/drivers/i965/brw_context.h
@@ -529,7 +529,14 @@ struct brw_query_object {
 struct brw_context 
 {
    struct pipe_context base;
-   struct brw_chipset chipset;
+   int gen;
+   boolean has_negative_rhw_bug;
+   boolean needs_ff_sync;
+   boolean is_g4x;
+
+   int urb_size;
+   int vs_max_threads;
+   int wm_max_threads;
 
    struct brw_winsys_screen *sws;
 
@@ -854,11 +861,5 @@ brw_context( struct pipe_context *ctx )
    return (struct brw_context *)ctx;
 }
 
-
-#define BRW_IS_965(brw)    ((brw)->chipset.is_965)
-#define BRW_IS_IGDNG(brw)  ((brw)->chipset.is_igdng)
-#define BRW_IS_G4X(brw)    ((brw)->chipset.is_g4x)
-
-
 #endif
 
diff --git a/src/gallium/drivers/i965/brw_defines.h b/src/gallium/drivers/i965/brw_defines.h
index e201ce4d7ce..feb1b48fafe 100644
--- a/src/gallium/drivers/i965/brw_defines.h
+++ b/src/gallium/drivers/i965/brw_defines.h
@@ -839,8 +839,8 @@
 #define R02_PRIM_END    0x1
 #define R02_PRIM_START  0x2
 
-#define URB_SIZES(brw)                  (BRW_IS_IGDNG(brw) ? 1024 : \
-                                         (BRW_IS_G4X(brw) ? 384 : 256))  /* 512 bit units */
+#define URB_SIZES(brw)                  (brw->gen == 5 ? 1024 : \
+                                         (brw->is_g4x ? 384 : 256))  /* 512 bit units */
 
 
 
diff --git a/src/gallium/drivers/i965/brw_draw_upload.c b/src/gallium/drivers/i965/brw_draw_upload.c
index cf9405470c8..04ec5c81a6b 100644
--- a/src/gallium/drivers/i965/brw_draw_upload.c
+++ b/src/gallium/drivers/i965/brw_draw_upload.c
@@ -170,7 +170,7 @@ static int brw_emit_vertex_buffers( struct brw_context *brw )
       OUT_RELOC(brw->vb.vb[i].bo,
 		BRW_USAGE_VERTEX,
 		brw->vb.vb[i].offset);
-      if (BRW_IS_IGDNG(brw)) {
+      if (brw->gen == 5) {
 	 OUT_RELOC(brw->vb.vb[i].bo,
 		   BRW_USAGE_VERTEX,
 		   brw->vb.vb[i].bo->size - 1);
diff --git a/src/gallium/drivers/i965/brw_eu_emit.c b/src/gallium/drivers/i965/brw_eu_emit.c
index 00d8eaccbc4..6c9b35fbf31 100644
--- a/src/gallium/drivers/i965/brw_eu_emit.c
+++ b/src/gallium/drivers/i965/brw_eu_emit.c
@@ -255,7 +255,7 @@ static void brw_set_math_message( struct brw_context *brw,
 {
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (BRW_IS_IGDNG(brw)) {
+   if (brw->gen == 5) {
        insn->bits3.math_igdng.function = function;
        insn->bits3.math_igdng.int_type = integer_type;
        insn->bits3.math_igdng.precision = low_precision;
@@ -322,7 +322,7 @@ static void brw_set_urb_message( struct brw_context *brw,
 {
     brw_set_src1(insn, brw_imm_d(0));
 
-    if (BRW_IS_IGDNG(brw)) {
+    if (brw->gen == 5) {
         insn->bits3.urb_igdng.opcode = 0;	/* ? */
         insn->bits3.urb_igdng.offset = offset;
         insn->bits3.urb_igdng.swizzle_control = swizzle_control;
@@ -361,7 +361,7 @@ static void brw_set_dp_write_message( struct brw_context *brw,
 {
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (BRW_IS_IGDNG(brw)) {
+   if (brw->gen == 5) {
        insn->bits3.dp_write_igdng.binding_table_index = binding_table_index;
        insn->bits3.dp_write_igdng.msg_control = msg_control;
        insn->bits3.dp_write_igdng.pixel_scoreboard_clear = pixel_scoreboard_clear;
@@ -398,7 +398,7 @@ static void brw_set_dp_read_message( struct brw_context *brw,
 {
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (BRW_IS_IGDNG(brw)) {
+   if (brw->gen == 5) {
        insn->bits3.dp_read_igdng.binding_table_index = binding_table_index;
        insn->bits3.dp_read_igdng.msg_control = msg_control;
        insn->bits3.dp_read_igdng.msg_type = msg_type;
@@ -437,7 +437,7 @@ static void brw_set_sampler_message(struct brw_context *brw,
    assert(eot == 0);
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (BRW_IS_IGDNG(brw)) {
+   if (brw->gen == 5) {
       insn->bits3.sampler_igdng.binding_table_index = binding_table_index;
       insn->bits3.sampler_igdng.sampler = sampler;
       insn->bits3.sampler_igdng.msg_type = msg_type;
@@ -448,7 +448,7 @@ static void brw_set_sampler_message(struct brw_context *brw,
       insn->bits3.sampler_igdng.end_of_thread = eot;
       insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER;
       insn->bits2.send_igdng.end_of_thread = eot;
-   } else if (BRW_IS_G4X(brw)) {
+   } else if (brw->is_g4x) {
       insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
       insn->bits3.sampler_g4x.sampler = sampler;
       insn->bits3.sampler_g4x.msg_type = msg_type;
@@ -658,7 +658,7 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
    struct brw_instruction *insn;
    GLuint br = 1;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
       br = 2;
 
    if (p->single_program_flow) {
@@ -699,7 +699,7 @@ void brw_ENDIF(struct brw_compile *p,
 {
    GLuint br = 1;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
       br = 2; 
  
    if (p->single_program_flow) {
@@ -813,7 +813,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
    struct brw_instruction *insn;
    GLuint br = 1;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
       br = 2;
 
    if (p->single_program_flow)
@@ -856,7 +856,7 @@ void brw_land_fwd_jump(struct brw_compile *p,
    struct brw_instruction *landing = &p->store[p->nr_insn];
    GLuint jmpi = 1;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
        jmpi = 2;
 
    assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);
diff --git a/src/gallium/drivers/i965/brw_gs.c b/src/gallium/drivers/i965/brw_gs.c
index 06826635a8a..2a8165b83ee 100644
--- a/src/gallium/drivers/i965/brw_gs.c
+++ b/src/gallium/drivers/i965/brw_gs.c
@@ -51,13 +51,13 @@ static enum pipe_error compile_gs_prog( struct brw_context *brw,
    memset(&c, 0, sizeof(c));
    
    c.key = *key;
-   c.need_ff_sync = BRW_IS_IGDNG(brw);
+   c.need_ff_sync = brw->gen == 5;
    /* Need to locate the two positions present in vertex + header.
     * These are currently hardcoded:
     */
    c.nr_attrs = c.key.nr_attrs;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       c.nr_regs = (c.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
    else
       c.nr_regs = (c.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
diff --git a/src/gallium/drivers/i965/brw_gs_state.c b/src/gallium/drivers/i965/brw_gs_state.c
index b64ec286cea..6e070f6d756 100644
--- a/src/gallium/drivers/i965/brw_gs_state.c
+++ b/src/gallium/drivers/i965/brw_gs_state.c
@@ -103,7 +103,7 @@ gs_unit_create_from_key(struct brw_context *brw,
    else
       gs.thread4.max_threads = 0;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       gs.thread4.rendering_enable = 1;
 
    if (BRW_DEBUG & DEBUG_STATS)
diff --git a/src/gallium/drivers/i965/brw_misc_state.c b/src/gallium/drivers/i965/brw_misc_state.c
index c635d696617..d53ce6ccfd4 100644
--- a/src/gallium/drivers/i965/brw_misc_state.c
+++ b/src/gallium/drivers/i965/brw_misc_state.c
@@ -239,7 +239,7 @@ static int prepare_depthbuffer(struct brw_context *brw)
 static int emit_depthbuffer(struct brw_context *brw)
 {
    struct pipe_surface *surface = brw->curr.fb.zsbuf;
-   unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5;
+   unsigned int len = (brw->is_g4x || brw->gen == 5) ? 6 : 5;
 
    if (surface == NULL) {
       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
@@ -250,7 +250,7 @@ static int emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       OUT_BATCH(0);
 
-      if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
+      if (brw->is_g4x || brw->gen == 5)
          OUT_BATCH(0);
 
       ADVANCE_BATCH();
@@ -298,7 +298,7 @@ static int emit_depthbuffer(struct brw_context *brw)
 		((surface->height - 1) << 19));
       OUT_BATCH(0);
 
-      if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
+      if (brw->is_g4x || brw->gen == 5)
          OUT_BATCH(0);
 
       ADVANCE_BATCH();
@@ -374,7 +374,7 @@ static int upload_invariant_state( struct brw_context *brw )
       struct brw_pipeline_select ps;
 
       memset(&ps, 0, sizeof(ps));
-      if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))
+      if (brw->is_g4x || brw->gen == 5)
 	 ps.header.opcode = CMD_PIPELINE_SELECT_GM45;
       else
 	 ps.header.opcode = CMD_PIPELINE_SELECT_965;
@@ -413,7 +413,7 @@ static int upload_invariant_state( struct brw_context *brw )
       struct brw_vf_statistics vfs;
       memset(&vfs, 0, sizeof(vfs));
 
-      if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) 
+      if (brw->is_g4x || brw->gen == 5)
 	 vfs.opcode = CMD_VF_STATISTICS_GM45;
       else 
 	 vfs.opcode = CMD_VF_STATISTICS_965;
@@ -424,7 +424,7 @@ static int upload_invariant_state( struct brw_context *brw )
       BRW_BATCH_STRUCT(brw, &vfs);
    }
    
-   if (!BRW_IS_965(brw))
+   if (!(brw->gen == 4))
    {
       struct brw_aa_line_parameters balp;
 
@@ -480,7 +480,7 @@ static int upload_state_base_address( struct brw_context *brw )
    /* Output the structure (brw_state_base_address) directly to the
     * batchbuffer, so we can emit relocations inline.
     */
-   if (BRW_IS_IGDNG(brw)) {
+   if (brw->gen == 5) {
        BEGIN_BATCH(8, IGNORE_CLIPRECTS);
        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
        OUT_BATCH(1); /* General state base address */
diff --git a/src/gallium/drivers/i965/brw_pipe_rast.c b/src/gallium/drivers/i965/brw_pipe_rast.c
index 4c1a6d7dcdf..c86681d1495 100644
--- a/src/gallium/drivers/i965/brw_pipe_rast.c
+++ b/src/gallium/drivers/i965/brw_pipe_rast.c
@@ -35,7 +35,7 @@ calculate_clip_key_rast( const struct brw_context *brw,
 {
    memset(key, 0, sizeof *key);
 
-   if (brw->chipset.is_igdng)
+   if (brw->gen == 5)
        key->clip_mode = BRW_CLIPMODE_KERNEL_CLIP;
    else
        key->clip_mode = BRW_CLIPMODE_NORMAL;
diff --git a/src/gallium/drivers/i965/brw_pipe_surface.c b/src/gallium/drivers/i965/brw_pipe_surface.c
index 4deead98b19..58a610089e2 100644
--- a/src/gallium/drivers/i965/brw_pipe_surface.c
+++ b/src/gallium/drivers/i965/brw_pipe_surface.c
@@ -169,20 +169,15 @@ static struct brw_surface *create_in_place_view( struct brw_screen *brw_screen,
 
       surface->ss.ss1.base_addr = surface->offset - tile_offset;
 
-      if (brw_screen->chipset.is_g4x) {
-	 if (tex->tiling == BRW_TILING_X) {
-	    /* Note that the low bits of these fields are missing, so
-	     * there's the possibility of getting in trouble.
-	     */
-	    surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4;
-	    surface->ss.ss5.y_offset = tile_offset / 512 / 2;
-	 } else {
-	    surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4;
+      if (tex->tiling == BRW_TILING_X) {
+	/* Note that the low bits of these fields are missing, so
+	 * there's the possibility of getting in trouble.
+	 */
+	surface->ss.ss5.x_offset = (tile_offset % 512) / tex->cpp / 4;
+	surface->ss.ss5.y_offset = tile_offset / 512 / 2;
+      } else {
+	surface->ss.ss5.x_offset = (tile_offset % 128) / tex->cpp / 4;
 	    surface->ss.ss5.y_offset = tile_offset / 128 / 2;
-	 }
-      }
-      else {
-	 assert(tile_offset == 0);
       }
    }
 
diff --git a/src/gallium/drivers/i965/brw_pipe_vertex.c b/src/gallium/drivers/i965/brw_pipe_vertex.c
index e1697687ccc..b23454b5808 100644
--- a/src/gallium/drivers/i965/brw_pipe_vertex.c
+++ b/src/gallium/drivers/i965/brw_pipe_vertex.c
@@ -203,7 +203,7 @@ static void brw_translate_vertex_elements(struct brw_context *brw,
       brw_velems->ve[i].ve1.vfcomponent2 = comp2;
       brw_velems->ve[i].ve1.vfcomponent3 = comp3;
 
-      if (BRW_IS_IGDNG(brw))
+      if (brw->gen == 5)
          brw_velems->ve[i].ve1.dst_offset = 0;
       else
          brw_velems->ve[i].ve1.dst_offset = i * 4;
diff --git a/src/gallium/drivers/i965/brw_reg.h b/src/gallium/drivers/i965/brw_reg.h
index ba10f9d5df1..2e3eeb6ecf8 100644
--- a/src/gallium/drivers/i965/brw_reg.h
+++ b/src/gallium/drivers/i965/brw_reg.h
@@ -93,18 +93,52 @@
 #define PCI_CHIP_G45_G                  0x2E22
 #define PCI_CHIP_G41_G                  0x2E32
 #define PCI_CHIP_B43_G                  0x2E42
+#define PCI_CHIP_B43_G1                 0x2E92
 
 #define PCI_CHIP_ILD_G                  0x0042
 #define PCI_CHIP_ILM_G                  0x0046
 
-struct brw_chipset {
-   unsigned pci_id:16;
-   unsigned is_965:1;
-   unsigned is_igdng:1;
-   unsigned is_g4x:1;
-   unsigned pad:13;
-};
-
+#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102	/* Desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
+#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106	/* Mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
+#define PCI_CHIP_SANDYBRIDGE_S		0x010A	/* Server */
+
+#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
+                                 devid == PCI_CHIP_Q45_G || \
+                                 devid == PCI_CHIP_G45_G || \
+                                 devid == PCI_CHIP_G41_G || \
+                                 devid == PCI_CHIP_B43_G || \
+                                 devid == PCI_CHIP_B43_G1)
+#define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
+#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
+
+#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
+				 devid == PCI_CHIP_I965_Q || \
+				 devid == PCI_CHIP_I965_G_1 || \
+				 devid == PCI_CHIP_I965_GM || \
+				 devid == PCI_CHIP_I965_GME || \
+				 devid == PCI_CHIP_I946_GZ || \
+				 IS_G4X(devid))
+
+#define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
+#define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
+#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
+
+#define IS_GEN6(devid)		(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS	|| \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
+				 devid == PCI_CHIP_SANDYBRIDGE_S)
+
+#define IS_965(devid)		(IS_GEN4(devid) || \
+				 IS_G4X(devid) || \
+				 IS_GEN5(devid) || \
+				 IS_GEN6(devid))
 
 /* XXX: hacks
  */
diff --git a/src/gallium/drivers/i965/brw_resource_texture.c b/src/gallium/drivers/i965/brw_resource_texture.c
index fded2da3820..0cb895f35de 100644
--- a/src/gallium/drivers/i965/brw_resource_texture.c
+++ b/src/gallium/drivers/i965/brw_resource_texture.c
@@ -392,7 +392,7 @@ brw_texture_create( struct pipe_screen *screen,
    if (tex->compressed == 0 &&
        !bscreen->no_tiling) 
    {
-      if (bscreen->chipset.is_965 &&
+      if (bscreen->gen < 5 &&
 	  util_format_is_depth_or_stencil(template->format))
 	 tex->tiling = BRW_TILING_Y;
       else
diff --git a/src/gallium/drivers/i965/brw_resource_texture_layout.c b/src/gallium/drivers/i965/brw_resource_texture_layout.c
index 2187bdd82ce..afecc77e312 100644
--- a/src/gallium/drivers/i965/brw_resource_texture_layout.c
+++ b/src/gallium/drivers/i965/brw_resource_texture_layout.c
@@ -388,7 +388,7 @@ GLboolean brw_texture_layout(struct brw_screen *brw_screen,
 {
    switch (tex->b.b.target) {
    case PIPE_TEXTURE_CUBE:
-      if (brw_screen->chipset.is_igdng)
+      if (brw_screen->gen == 5)
 	 brw_layout_cubemap_idgng( tex );
       else
 	 brw_layout_3d_cube( tex );
diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c
index f5b75b17e36..6ab9075e13a 100644
--- a/src/gallium/drivers/i965/brw_screen.c
+++ b/src/gallium/drivers/i965/brw_screen.c
@@ -97,7 +97,7 @@ brw_get_name(struct pipe_screen *screen)
    static char buffer[128];
    const char *chipset;
 
-   switch (brw_screen(screen)->chipset.pci_id) {
+   switch (brw_screen(screen)->pci_id) {
    case PCI_CHIP_I965_G:
       chipset = "I965_G";
       break;
@@ -405,8 +405,7 @@ struct pipe_screen *
 brw_screen_create(struct brw_winsys_screen *sws)
 {
    struct brw_screen *bscreen;
-   struct brw_chipset chipset;
-
+   int gen;
 #ifdef DEBUG
    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
@@ -415,46 +414,29 @@ brw_screen_create(struct brw_winsys_screen *sws)
    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 #endif
 
-   memset(&chipset, 0, sizeof chipset);
-
-   chipset.pci_id = sws->pci_id;
-
-   switch (chipset.pci_id) {
-   case PCI_CHIP_I965_G:
-   case PCI_CHIP_I965_Q:
-   case PCI_CHIP_I965_G_1:
-   case PCI_CHIP_I946_GZ:
-   case PCI_CHIP_I965_GM:
-   case PCI_CHIP_I965_GME:
-      chipset.is_965 = TRUE;
-      break;
-
-   case PCI_CHIP_GM45_GM:
-   case PCI_CHIP_IGD_E_G:
-   case PCI_CHIP_Q45_G:
-   case PCI_CHIP_G45_G:
-   case PCI_CHIP_G41_G:
-   case PCI_CHIP_B43_G:
-      chipset.is_g4x = TRUE;
-      break;
-
-   case PCI_CHIP_ILD_G:
-   case PCI_CHIP_ILM_G:
-      chipset.is_igdng = TRUE;
-      break;
+   bscreen = CALLOC_STRUCT(brw_screen);
+   if (!bscreen)
+      return NULL;
 
-   default:
+   bscreen->pci_id = sws->pci_id;
+   if (IS_GEN6(sws->pci_id)) {
+       bscreen->gen = 6;
+       bscreen->needs_ff_sync = TRUE;
+   } else if (IS_GEN5(sws->pci_id)) {
+       bscreen->gen = 5;
+       bscreen->needs_ff_sync = TRUE;
+   } else if (IS_965(sws->pci_id)) {
+       bscreen->gen = 4;
+       if (IS_G4X(sws->pci_id)) {
+	   bscreen->is_g4x = true;
+       }
+   } else {
       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", 
-                   __FUNCTION__, chipset.pci_id);
+                   __FUNCTION__, sws->pci_id);
+      free(bscreen);
       return NULL;
    }
 
-
-   bscreen = CALLOC_STRUCT(brw_screen);
-   if (!bscreen)
-      return NULL;
-
-   bscreen->chipset = chipset;
    bscreen->sws = sws;
    bscreen->base.winsys = NULL;
    bscreen->base.destroy = brw_destroy_screen;
diff --git a/src/gallium/drivers/i965/brw_screen.h b/src/gallium/drivers/i965/brw_screen.h
index 58e293bc76f..a62e1afc405 100644
--- a/src/gallium/drivers/i965/brw_screen.h
+++ b/src/gallium/drivers/i965/brw_screen.h
@@ -43,7 +43,11 @@ struct brw_winsys_screen;
 struct brw_screen
 {
    struct pipe_screen base;
-   struct brw_chipset chipset;
+   int gen;
+   boolean has_negative_rhw_bug;
+   boolean needs_ff_sync;
+   boolean is_g4x;
+   int pci_id;
    struct brw_winsys_screen *sws;
    boolean no_tiling;
 };
diff --git a/src/gallium/drivers/i965/brw_sf_emit.c b/src/gallium/drivers/i965/brw_sf_emit.c
index 497634ec9ed..901c3341642 100644
--- a/src/gallium/drivers/i965/brw_sf_emit.c
+++ b/src/gallium/drivers/i965/brw_sf_emit.c
@@ -161,7 +161,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
    if (c->key.primitive == SF_UNFILLED_TRIS)
       return;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
        jmpi = 2;
 
    brw_push_insn_state(p);
@@ -205,7 +205,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
    if (c->key.primitive == SF_UNFILLED_TRIS)
       return;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
        jmpi = 2;
 
    brw_push_insn_state(p);
diff --git a/src/gallium/drivers/i965/brw_sf_state.c b/src/gallium/drivers/i965/brw_sf_state.c
index 6c299a86b49..eec024650ce 100644
--- a/src/gallium/drivers/i965/brw_sf_state.c
+++ b/src/gallium/drivers/i965/brw_sf_state.c
@@ -148,7 +148,7 @@ sf_unit_create_from_key(struct brw_context *brw,
 
    sf.thread3.dispatch_grf_start_reg = 3;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
        sf.thread3.urb_entry_read_offset = 3;
    else
        sf.thread3.urb_entry_read_offset = 1;
@@ -161,7 +161,7 @@ sf_unit_create_from_key(struct brw_context *brw,
    /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or 
     * 48(IGDNG) threads 
     */
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       chipset_max_threads = 48;
    else
       chipset_max_threads = 24;
diff --git a/src/gallium/drivers/i965/brw_urb.c b/src/gallium/drivers/i965/brw_urb.c
index 907ec56c6ca..b630752809e 100644
--- a/src/gallium/drivers/i965/brw_urb.c
+++ b/src/gallium/drivers/i965/brw_urb.c
@@ -147,7 +147,7 @@ static int recalculate_urb_fence( struct brw_context *brw )
 
       brw->urb.constrained = 0;
 
-      if (BRW_IS_IGDNG(brw)) {
+      if (brw->gen == 5) {
          brw->urb.nr_vs_entries = 128;
          brw->urb.nr_sf_entries = 48;
          if (check_urb_layout(brw)) {
@@ -157,7 +157,7 @@ static int recalculate_urb_fence( struct brw_context *brw )
             brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
             brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
          }
-      } else if (BRW_IS_G4X(brw)) {
+      } else if (brw->is_g4x) {
 	 brw->urb.nr_vs_entries = 64;
 	 if (check_urb_layout(brw)) {
 	    goto done;
diff --git a/src/gallium/drivers/i965/brw_vs.h b/src/gallium/drivers/i965/brw_vs.h
index 944d88c84cc..b6d1091618e 100644
--- a/src/gallium/drivers/i965/brw_vs.h
+++ b/src/gallium/drivers/i965/brw_vs.h
@@ -56,7 +56,6 @@ struct brw_vs_compile {
    struct brw_compile func;
    struct brw_vs_prog_key key;
    struct brw_vs_prog_data prog_data;
-   struct brw_chipset chipset;
 
    struct brw_vertex_shader *vp;
 
diff --git a/src/gallium/drivers/i965/brw_vs_emit.c b/src/gallium/drivers/i965/brw_vs_emit.c
index 5dcbd597ddc..a53553d0986 100644
--- a/src/gallium/drivers/i965/brw_vs_emit.c
+++ b/src/gallium/drivers/i965/brw_vs_emit.c
@@ -116,6 +116,7 @@ static boolean find_output_slot( struct brw_vs_compile *c,
  */
 static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 {
+   struct brw_context *brw = c->func.brw;
    GLuint i, reg = 0, subreg = 0, mrf;
    int attributes_in_vue;
 
@@ -218,7 +219,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    c->nr_outputs = c->prog_data.nr_outputs;
 
-   if (c->chipset.is_igdng)
+   if (brw->gen == 5)
       mrf = 8;
    else
       mrf = 4;
@@ -333,7 +334,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
 
-   if (c->chipset.is_igdng)
+   if (brw->gen == 5)
       c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
    else
       c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@@ -1124,6 +1125,7 @@ static struct brw_reg get_dst( struct brw_vs_compile *c,
 static void emit_vertex_write( struct brw_vs_compile *c)
 {
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    struct brw_reg m0 = brw_message_reg(0);
    struct brw_reg pos = c->regs[TGSI_FILE_OUTPUT][VERT_RESULT_HPOS];
    struct brw_reg ndc;
@@ -1143,7 +1145,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
     */
    if (c->prog_data.writes_psiz ||
        c->key.nr_userclip || 
-       c->chipset.is_965)
+       brw->has_negative_rhw_bug)
    {
       struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
       GLuint i;
@@ -1174,7 +1176,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
        * Later, clipping will detect ucp[6] and ensure the primitive is
        * clipped against all fixed planes.
        */
-      if (c->chipset.is_965) {
+      if (brw->has_negative_rhw_bug) {
 	 brw_CMP(p,
 		 vec8(brw_null_reg()),
 		 BRW_CONDITIONAL_L,
@@ -1202,7 +1204,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
    brw_set_access_mode(p, BRW_ALIGN_1);
    brw_MOV(p, offset(m0, 2), ndc);
 
-   if (c->chipset.is_igdng) {
+   if (brw->gen == 5) {
        /* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */
        brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */
        /* m4, m5 contain the distances from vertex to the user clip planeXXX. 
@@ -1339,6 +1341,7 @@ static void emit_insn(struct brw_vs_compile *c,
    unsigned opcode = inst->Instruction.Opcode;
    unsigned label = inst->Label.Label;
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    struct brw_reg args[3], dst;
    GLuint i;
 
@@ -1514,7 +1517,7 @@ static void emit_insn(struct brw_vs_compile *c,
 
       c->loop_depth--;
 
-      if (c->chipset.is_igdng)
+      if (brw->gen == 5)
 	 br = 2;
 
       inst0 = inst1 = brw_WHILE(p, c->loop_inst[c->loop_depth]);
diff --git a/src/gallium/drivers/i965/brw_vs_state.c b/src/gallium/drivers/i965/brw_vs_state.c
index dadbb622e4d..6d2ccfd6d98 100644
--- a/src/gallium/drivers/i965/brw_vs_state.c
+++ b/src/gallium/drivers/i965/brw_vs_state.c
@@ -100,7 +100,7 @@ vs_unit_create_from_key(struct brw_context *brw,
     */
    vs.thread1.single_program_flow = 0;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
    else
       vs.thread1.binding_table_entry_count = key->nr_surfaces;
@@ -111,16 +111,16 @@ vs_unit_create_from_key(struct brw_context *brw,
    vs.thread3.urb_entry_read_offset = 0;
    vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
        vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
    else
        vs.thread4.nr_urb_entries = key->nr_urb_entries;
 
    vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       chipset_max_threads = 72;
-   else if (BRW_IS_G4X(brw))
+   else if (brw->is_g4x)
       chipset_max_threads = 32;
    else
       chipset_max_threads = 16;
diff --git a/src/gallium/drivers/i965/brw_wm_emit.c b/src/gallium/drivers/i965/brw_wm_emit.c
index 8f983a60ae8..a866fe758b2 100644
--- a/src/gallium/drivers/i965/brw_wm_emit.c
+++ b/src/gallium/drivers/i965/brw_wm_emit.c
@@ -848,7 +848,7 @@ static void emit_tex( struct brw_wm_compile *c,
 
    responseLength = 8;		/* always */
 
-   if (BRW_IS_IGDNG(p->brw)) {
+   if (p->brw->gen == 5) {
        if (shadow)
            msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG;
        else
@@ -917,7 +917,7 @@ static void emit_txb( struct brw_wm_compile *c,
    brw_MOV(p, brw_message_reg(8), coord[3]);
    msgLength = 9;
 
-   if (BRW_IS_IGDNG(p->brw))
+   if (p->brw->gen == 5)
        msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG;
    else
        msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
diff --git a/src/gallium/drivers/i965/brw_wm_glsl.c b/src/gallium/drivers/i965/brw_wm_glsl.c
index 3b3afc39d3c..fb8e40d928e 100644
--- a/src/gallium/drivers/i965/brw_wm_glsl.c
+++ b/src/gallium/drivers/i965/brw_wm_glsl.c
@@ -1607,7 +1607,7 @@ static void emit_txb(struct brw_wm_compile *c,
     brw_MOV(p, brw_message_reg(5), src[3]);          /* bias */
     brw_MOV(p, brw_message_reg(6), brw_imm_f(0));    /* ref (unused?) */
 
-    if (BRW_IS_IGDNG(p->brw)) {
+    if (p->brw->gen == 5) {
         msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG;
     } else {
         /* Does it work well on SIMD8? */
@@ -1688,7 +1688,7 @@ static void emit_tex(struct brw_wm_compile *c,
        brw_MOV(p, brw_message_reg(6), src[2]);        /* ref value / R coord */
     }
 
-    if (BRW_IS_IGDNG(p->brw)) {
+    if (p->brw->gen == 5) {
         if (shadow)
             msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG;
         else
@@ -1970,7 +1970,7 @@ static void brw_wm_emit_branching_shader(struct brw_context *brw, struct brw_wm_
                   struct brw_instruction *inst0, *inst1;
                   GLuint br = 1;
 
-                  if (BRW_IS_IGDNG(brw))
+                  if (brw->gen == 5)
                      br = 2;
  
                   loop_depth--;
diff --git a/src/gallium/drivers/i965/brw_wm_state.c b/src/gallium/drivers/i965/brw_wm_state.c
index efc2d96be13..a690003ecbd 100644
--- a/src/gallium/drivers/i965/brw_wm_state.c
+++ b/src/gallium/drivers/i965/brw_wm_state.c
@@ -70,9 +70,9 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
       key->max_threads = 1;
    else {
       /* WM maximum threads is number of EUs times number of threads per EU. */
-      if (BRW_IS_IGDNG(brw))
+      if (brw->gen == 5)
          key->max_threads = 12 * 6;
-      else if (BRW_IS_G4X(brw))
+      else if (brw->is_g4x)
 	 key->max_threads = 10 * 5;
       else
 	 key->max_threads = 8 * 4;
@@ -155,7 +155,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
    wm.thread1.depth_coef_urb_read_offset = 1;
    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
-   if (BRW_IS_IGDNG(brw))
+   if (brw->gen == 5)
       wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
    else
       wm.thread1.binding_table_entry_count = key->nr_surfaces;
@@ -174,7 +174,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
    wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
    wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 
-   if (BRW_IS_IGDNG(brw)) 
+   if (brw->gen == 5) 
       wm.wm4.sampler_count = 0; /* hardware requirement */
    else
       wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
@@ -277,7 +277,7 @@ static enum pipe_error upload_wm_unit( struct brw_context *brw )
    grf_reg_count = (align(key.total_grf, 16) / 16 - 1);
    per_thread_scratch_space = key.total_scratch / 1024 - 1;
    stats_enable = (BRW_DEBUG & DEBUG_STATS) || key.stats_wm;
-   sampler_count = BRW_IS_IGDNG(brw) ? 0 :(key.sampler_count + 1) / 4;
+   sampler_count = brw->gen == 5 ? 0 :(key.sampler_count + 1) / 4;
 
    /* Emit WM program relocation */
    make_reloc(&reloc[nr_reloc++],