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| author | Marek Olšák <[email protected]> | 2019-08-21 00:18:17 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-08-27 16:16:08 -0400 |
| commit | 4dde40908fdb20ca3efce4a138293ddf829e2c0b (patch) | |
| tree | 54d58eb5374a9b8d7444d554fd97b81c6d9be08e /src/gallium/drivers/i915/i915_surface.h | |
| parent | 1426acf9e7ecba1a252b68979f8721b26fc73f44 (diff) | |
radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.
Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/i915/i915_surface.h')
0 files changed, 0 insertions, 0 deletions