diff options
| author | Stéphane Marchesin <[email protected]> | 2013-09-04 17:55:21 -0700 |
|---|---|---|
| committer | Stéphane Marchesin <[email protected]> | 2013-09-04 19:48:18 -0700 |
| commit | 8709e2b6c564435111545c470da8796c81f020c4 (patch) | |
| tree | 7baa8736e5c2ae7cca8d8cfcc28a34d68b59e6f5 /src/gallium/drivers/i915/i915_state.c | |
| parent | b1461acf15ab450fa0d360ec5e03c90d0797a6d4 (diff) | |
i915g: Implement writemask fixup
The fixup code emulates non-BGRA render targets by adding an
extra instruction at the end of fragment shaders to swizzle the
output. To do this, we also swizzle the blend function. However
an oversight until now was that the writemask wasn't getting
swizzled. This patch fixes that which fixes a bunch of piglit
tests.
Diffstat (limited to 'src/gallium/drivers/i915/i915_state.c')
| -rw-r--r-- | src/gallium/drivers/i915/i915_state.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c index 06d4d3bd1af..8ca69fc790e 100644 --- a/src/gallium/drivers/i915/i915_state.c +++ b/src/gallium/drivers/i915/i915_state.c @@ -94,7 +94,6 @@ static unsigned translate_mip_filter( unsigned filter ) } } - /* None of this state is actually used for anything yet. */ static void * @@ -117,10 +116,10 @@ i915_create_blend_state(struct pipe_context *pipe, */ if (srcA != srcRGB || - dstA != dstRGB || - eqA != eqRGB) { + dstA != dstRGB || + eqA != eqRGB) { - cso_data->iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | + cso_data->iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE | IAB_ENABLE | IAB_MODIFY_FUNC | @@ -131,7 +130,7 @@ i915_create_blend_state(struct pipe_context *pipe, (i915_translate_blend_func(eqA) << IAB_FUNC_SHIFT)); } else { - cso_data->iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | + cso_data->iab = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE | 0); } @@ -147,7 +146,7 @@ i915_create_blend_state(struct pipe_context *pipe, if (blend->dither) cso_data->LIS5 |= S5_COLOR_DITHER_ENABLE; - /* XXX here take the target fixup into account */ + /* We potentially do some fixup at emission for non-BGRA targets */ if ((blend->rt[0].colormask & PIPE_MASK_R) == 0) cso_data->LIS5 |= S5_WRITEDISABLE_RED; @@ -276,7 +275,7 @@ i915_create_sampler_state(struct pipe_context *pipe, maxlod = CLAMP(maxlod, 0, 16 * 11); if (minlod > maxlod) - maxlod = minlod; + maxlod = minlod; cso->minlod = minlod; cso->maxlod = maxlod; @@ -499,7 +498,7 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, (func << S6_DEPTH_TEST_FUNC_SHIFT)); if (depth_stencil->depth.writemask) - cso->depth_LIS6 |= S6_DEPTH_WRITE_ENABLE; + cso->depth_LIS6 |= S6_DEPTH_WRITE_ENABLE; } if (depth_stencil->alpha.enabled) { |