i915g: rip out ->sw_tiled

It looks like this was meant to facilitate unfenced access to textures/
color/renderbuffers. It's totally incomplete and fundamentally broken
on a few levels:
- broken: The kernel needs to about every tiled bo to fix up bit17
  swizzling on swap-in.
- unflexible: fenced/unfenced relocs from execbuffer2 do the same, much
  simpler.
- unneeded: with relaxed fencing tiled gem bos are as memory-efficient
  as this trick.

Hence kill it.

Reviewed-by: Jakob Bornecrantz <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Signed-off-by: Jakob Bornecrantz <[email protected]>

1 files changed, 0 insertions, 1 deletions

diff --git a/src/gallium/drivers/i915/i915_resource.h b/src/gallium/drivers/i915/i915_resource.h
index 1093e8f41f9..1f87f56efaa 100644
--- a/src/gallium/drivers/i915/i915_resource.h
+++ b/src/gallium/drivers/i915/i915_resource.h
@@ -56,7 +56,6 @@ struct i915_texture {
    unsigned depth_stride;          /* per-image on i945? */
    unsigned total_nblocksy;
 
-   unsigned sw_tiled; /**< tiled with software flags */
    unsigned hw_tiled; /**< tiled with hardware fences */
 
    unsigned nr_images[I915_MAX_TEXTURE_2D_LEVELS];