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| author | Kenneth Graunke <[email protected]> | 2017-04-21 01:28:13 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-04-22 00:01:16 -0700 |
| commit | 2faf227ec2e22c7a37e0a54783a3f0a0062ac852 (patch) | |
| tree | be1c51b725775d55d3ab2ffcecbbd7020130ac3d /src/gallium/drivers/i915/i915_flush.c | |
| parent | d682f8aa8e0edd166166f87fcd774dd2d57b4180 (diff) | |
i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().
opt_register_coalesce() was optimizing sequences such as:
mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
mach(8) vgrf5.xy:D, attr18.xyyy:D, attr19.xyyy:D
mov(8) m4.zw:F, vgrf5.xxxy:F
into:
mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
mach(8) m4.zw:D, attr18.xxxy:D, attr19.xxxy:D
This doesn't work - if we're going to reswizzle MACH, we'd need to
reswizzle the MUL as well. Here, the MUL fills the accumulator's .zw
components with attr18.yy * attr19.yy. But the MACH instruction expects
.z to contain attr18.x * attr19.x. Bogus results ensue.
No change in shader-db on Haswell. Prevents regressions in Timothy's
patches to use enhanced layouts for varying packing (which rearrange
code just enough to trigger this pre-existing bug, but were fine
themselves).
Acked-by: Timothy Arceri <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/gallium/drivers/i915/i915_flush.c')
0 files changed, 0 insertions, 0 deletions