i915g: fix transfer coherency

The kernel drm takes care of all coherency as long as we don't forget
to submit all outstanding commands in the batchbuffer ...

Also move batchbuffer initialization up because otherwise transfers
for some helper textures fail with a segmentation fault.

And kill the dead code, flushes should now be correct everywhere.

Signed-off-by: Daniel Vetter <[email protected]>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 5dbf0cfcbf1..cb3de82a104 100644
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -151,6 +151,10 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
                     16, UTIL_SLAB_SINGLETHREADED);
 
+   /* Batch stream debugging is a bit hacked up at the moment:
+    */
+   i915->batch = i915->iws->batchbuffer_create(i915->iws);
+
    /*
     * Create drawing context and plug our rendering stage into it.
     */
@@ -183,9 +187,5 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    i915->dynamic_dirty = ~0;
    i915->flush_dirty = 0;
 
-   /* Batch stream debugging is a bit hacked up at the moment:
-    */
-   i915->batch = i915->iws->batchbuffer_create(i915->iws);
-
    return &i915->base;
 }