diff options
| author | Rob Clark <[email protected]> | 2019-06-10 06:43:52 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-06-11 10:55:27 -0700 |
| commit | 4f1319a17dc795cb76cd97853b15bfd1dfb02a14 (patch) | |
| tree | 4fd5ce39dfcc8cdb34e73bed9bb45b12c60fb4d9 /src/gallium/drivers/freedreno | |
| parent | d42ce659edd6c302a9909dadc8864fe51714ab8c (diff) | |
freedreno/a6xx: use correct UBWC reg builders
No functional change, the registers have the same layout as MRT flags
pitch reg.
Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Kristian H. Kristensen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_blitter.c | 8 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 14 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c index ced13ad1a07..0fb552c1233 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c @@ -475,8 +475,8 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) if (subwc_enabled) { OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6); OUT_RELOC(ring, src->bo, subwcoff, 0, 0); - OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(src->ubwc_pitch) | - A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(src->ubwc_size)); + OUT_RING(ring, A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(src->ubwc_pitch) | + A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(src->ubwc_size)); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); @@ -501,8 +501,8 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) if (dubwc_enabled) { OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6); OUT_RELOCW(ring, dst->bo, dubwcoff, 0, 0); - OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(dst->ubwc_pitch) | - A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(dst->ubwc_size)); + OUT_RING(ring, A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(dst->ubwc_pitch) | + A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(dst->ubwc_size)); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index ebdfd5b8923..1afb1d74fa3 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -189,12 +189,12 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf, OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3); if (ubwc_enabled) { OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); /* BASE_LO/HI */ - OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) | - A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size)); + OUT_RING(ring, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) | + A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size)); } else { - OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */ - OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */ + OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */ + OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */ } if (rsc->lrz) { @@ -759,8 +759,8 @@ emit_blit(struct fd_batch *batch, if (ubwc_enabled) { OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3); OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); - OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) | - A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size)); + OUT_RING(ring, A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(rsc->ubwc_pitch) | + A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(rsc->ubwc_size)); } fd6_emit_blit(batch, ring); |