diff options
| author | Ilia Mirkin <[email protected]> | 2015-04-27 23:47:40 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2015-05-20 21:53:59 -0400 |
| commit | 3e7bc6728520b469ed53a2588ead28287f8b88f0 (patch) | |
| tree | 44dd9511e1fef2761b11fca8c50fd58ee7ecd604 /src/gallium/drivers/freedreno | |
| parent | 36438f0db6c7c696df73ced12684f4df9d2b47e5 (diff) | |
freedreno/ir3: fix immediate usage in tgsi tex fe
get_immediate will return a const reference, the requested immediate
isn't necessarily in the x slot. Make sure to use the swizzle.
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: [email protected]
Diffstat (limited to 'src/gallium/drivers/freedreno')
| -rw-r--r-- | src/gallium/drivers/freedreno/ir3/ir3_compiler.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c index ad0340032e4..cc049d3fdfd 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c @@ -1615,7 +1615,7 @@ trans_samp(const struct instr_translater *t, instr->cat1.src_type = type_mov; instr->cat1.dst_type = type_mov; add_dst_reg(ctx, instr, &tmp_dst, i); - add_src_reg(ctx, instr, &zero, 0); + add_src_reg(ctx, instr, &zero, zero.SwizzleX); i++; } if (tgt->array) { @@ -1669,15 +1669,18 @@ trans_samp(const struct instr_translater *t, */ if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) { while (collect->regs_count < 5) - ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); + ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), + &zero, zero.SwizzleX); for (i = 0; i < tgt->dims; i++) ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdx, i); if (tgt->dims < 2) - ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); + ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), + &zero, zero.SwizzleX); for (i = 0; i < tgt->dims; i++) ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdy, i); if (tgt->dims < 2) - ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); + ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), + &zero, zero.SwizzleX); tinf.src_wrmask |= ((1 << (2 * MAX2(tgt->dims, 2))) - 1) << 4; } @@ -1700,7 +1703,8 @@ trans_samp(const struct instr_translater *t, ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), offset, i); if (tgt->dims < 2) - ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); + ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), + &zero, zero.SwizzleX); } if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), |