diff options
| author | Ilia Mirkin <[email protected]> | 2014-11-28 20:54:30 -0500 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2014-11-30 13:00:41 -0500 |
| commit | 8e147e9ec80c5789466e16665925f4a08e3664a3 (patch) | |
| tree | 711e10eb7517dbdf893dd4b0e339f1c7d73afeb5 /src/gallium/drivers/freedreno | |
| parent | d63afe3b588096ca6b91db8d1d8807968b63b390 (diff) | |
freedreno/a3xx: remove blend clamp enables from gmem/clears
Just pass the data through unmolested. This probably has no effect since
blending isn't actually enabled.
Signed-off-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_draw.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c index fe53c8ece7a..ff6db58f783 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c @@ -323,8 +323,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers, A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) | A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) | A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) | - A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) | - A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE); + A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO)); } OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1); diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c index 1dd43cc6b4c..dae0b113635 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c @@ -493,8 +493,7 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile) A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) | A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) | A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) | - A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) | - A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE); + A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO)); } OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1); |