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authorMarek Olšák <[email protected]>2019-09-25 21:38:40 -0400
committerMarek Olšák <[email protected]>2019-10-07 20:05:00 -0400
commit732ea0b213ce534c2ac05ced8ead2df8fa769efb (patch)
treef6d7168f59565a5e8d6e5f2e5409ff68d150a5fc /src/gallium/drivers/freedreno
parent59dd4dafb5fea8a76e43d1280650b087809945a1 (diff)
gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lock
u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
-rw-r--r--src/gallium/drivers/freedreno/freedreno_resource.c4
-rw-r--r--src/gallium/drivers/freedreno/freedreno_state.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
index fcc8fc66189..d52f9441f63 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -419,7 +419,7 @@ static void fd_resource_transfer_flush_region(struct pipe_context *pctx,
struct fd_resource *rsc = fd_resource(ptrans->resource);
if (ptrans->resource->target == PIPE_BUFFER)
- util_range_add(&rsc->valid_buffer_range,
+ util_range_add(&rsc->base, &rsc->valid_buffer_range,
ptrans->box.x + box->x,
ptrans->box.x + box->x + box->width);
}
@@ -489,7 +489,7 @@ fd_resource_transfer_unmap(struct pipe_context *pctx,
fd_bo_cpu_fini(rsc->bo);
}
- util_range_add(&rsc->valid_buffer_range,
+ util_range_add(&rsc->base, &rsc->valid_buffer_range,
ptrans->box.x,
ptrans->box.x + ptrans->box.width);
diff --git a/src/gallium/drivers/freedreno/freedreno_state.c b/src/gallium/drivers/freedreno/freedreno_state.c
index 3133d2746b2..4f315488d1b 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.c
+++ b/src/gallium/drivers/freedreno/freedreno_state.c
@@ -472,7 +472,7 @@ fd_create_stream_output_target(struct pipe_context *pctx,
target->buffer_size = buffer_size;
assert(rsc->base.target == PIPE_BUFFER);
- util_range_add(&rsc->valid_buffer_range,
+ util_range_add(&rsc->base, &rsc->valid_buffer_range,
buffer_offset, buffer_offset + buffer_size);
return target;