diff options
| author | Wladimir J. van der Laan <[email protected]> | 2017-08-08 15:06:21 +0000 |
|---|---|---|
| committer | Wladimir J. van der Laan <[email protected]> | 2018-03-31 06:17:59 +0000 |
| commit | e8e3aa68d666d2cad47ef055a1d7b16df4c958d7 (patch) | |
| tree | f2e9e2a0585e862c4f1edf08af6dc712bfb94262 /src/gallium/drivers/freedreno | |
| parent | 79d6b194f252a2ea029244b831129cfb6cb6d153 (diff) | |
freedreno: a2xx: Implement DP2 instruction
Use DOT2ADDv instruction with 0.0f constant add.
Signed-off-by: Wladimir J. van der Laan <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
| -rw-r--r-- | src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c index 84855a48d2a..3ad47f98508 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c @@ -987,6 +987,24 @@ translate_trig(struct fd2_compile_context *ctx, add_src_reg(ctx, instr, &tmp_src); } +static void +translate_dp2(struct fd2_compile_context *ctx, + struct tgsi_full_instruction *inst, + unsigned opc) +{ + struct tgsi_src_register tmp_const; + struct ir2_instruction *instr; + /* DP2ADD c,a,b -> dot2(a,b) + c */ + /* for c we use the constant 0.0 */ + instr = ir2_instr_create_alu(next_exec_cf(ctx), DOT2ADDv, ~0); + get_immediate(ctx, &tmp_const, fui(0.0f)); + add_dst_reg(ctx, instr, &inst->Dst[0].Register); + add_src_reg(ctx, instr, &tmp_const); + add_src_reg(ctx, instr, &inst->Src[0].Register); + add_src_reg(ctx, instr, &inst->Src[1].Register); + add_vector_clamp(inst, instr); +} + /* * Main part of compiler/translator: */ @@ -1054,6 +1072,9 @@ translate_instruction(struct fd2_compile_context *ctx, instr = ir2_instr_create_alu(cf, ADDv, ~0); add_regs_vector_2(ctx, inst, instr); break; + case TGSI_OPCODE_DP2: + translate_dp2(ctx, inst, opc); + break; case TGSI_OPCODE_DP3: instr = ir2_instr_create_alu(cf, DOT3v, ~0); add_regs_vector_2(ctx, inst, instr); |