diff options
| author | Rob Clark <[email protected]> | 2013-12-14 12:13:28 -0500 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2013-12-14 12:35:07 -0500 |
| commit | f9cfe5ce82cf49fec5603db42324df40372ee671 (patch) | |
| tree | fe8c5fad271c4d932f04569f0b07894463490860 /src/gallium/drivers/freedreno | |
| parent | b56c7f4df118a4a178988cb6c07154b56e6788db (diff) | |
freedreno: dummy-draw workaround for a320
Fixes gpu lockups in supertuxkart.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_emit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/freedreno_draw.h | 15 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index a8b2df758e3..f6a116056a4 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -231,6 +231,7 @@ emit_cache_flush(struct fd_ringbuffer *ring) OUT_PKT3(ring, CP_EVENT_WRITE, 1); OUT_RING(ring, CACHE_FLUSH); + /* probably only really needed on a320: */ OUT_PKT3(ring, CP_DRAW_INDX, 3); OUT_RING(ring, 0x00000000); OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, @@ -523,7 +524,7 @@ fd3_emit_restore(struct fd_context *ctx) OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE | A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) | A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff)); - OUT_RING(ring, 0x00000000); /* UNKNOWN_20C3 */ + OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */ OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1); OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) | diff --git a/src/gallium/drivers/freedreno/freedreno_draw.h b/src/gallium/drivers/freedreno/freedreno_draw.h index cf83a360325..9ccc246395f 100644 --- a/src/gallium/drivers/freedreno/freedreno_draw.h +++ b/src/gallium/drivers/freedreno/freedreno_draw.h @@ -59,6 +59,21 @@ fd_draw(struct fd_context *ctx, enum pc_di_primtype primtype, */ emit_marker(ring, 7); + if (ctx->screen->gpu_id == 320) { + /* dummy-draw workaround: */ + OUT_PKT3(ring, CP_DRAW_INDX, 3); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, + INDEX_SIZE_IGN, IGNORE_VISIBILITY)); + OUT_RING(ring, 0); /* NumIndices */ + + /* ugg, hard-code register offset to avoid pulling in the + * a3xx register headers into something #included from a2xx + */ + OUT_PKT0(ring, 0x2206, 1); /* A3XX_HLSQ_CONST_VSPRESV_RANGE_REG */ + OUT_RING(ring, 0); + } + OUT_PKT3(ring, CP_DRAW_INDX, idx_bo ? 5 : 3); OUT_RING(ring, 0x00000000); /* viz query info. */ OUT_RING(ring, DRAW(primtype, src_sel, |