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authorRob Clark <[email protected]>2019-04-29 10:11:44 -0700
committerRob Clark <[email protected]>2019-05-02 11:19:22 -0700
commit8c77e669a81f67cb9191cae0b69bf5899f541e3a (patch)
tree9935c5c5d3fcefafd66e6256d181a0549480a38e /src/gallium/drivers/freedreno
parent6fa8a6d60f0bbc112870dedbc7e9958f07a85d09 (diff)
freedreno/a6xx: smaller hammer for fb barrier
We just need to do a sequence of commands to flush the cache. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno')
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.c36
-rw-r--r--src/gallium/drivers/freedreno/freedreno_context.c9
-rw-r--r--src/gallium/drivers/freedreno/freedreno_context.h3
3 files changed, 48 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index c17bd49be4d..fca00204e54 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1297,6 +1297,41 @@ fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
}
}
+/* this is *almost* the same as fd6_cache_flush().. which I guess
+ * could be re-worked to be something a bit more generic w/ param
+ * indicating what needs to be flushed.. although that would mean
+ * figuring out which events trigger what state to flush..
+ */
+static void
+fd6_framebuffer_barrier(struct fd_context *ctx)
+{
+ struct fd6_context *fd6_ctx = fd6_context(ctx);
+ struct fd_batch *batch = ctx->batch;
+ struct fd_ringbuffer *ring = batch->draw;
+ unsigned seqno;
+
+ seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
+
+ OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
+ OUT_RING(ring, 0x00000013);
+ OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
+ OUT_RING(ring, seqno);
+ OUT_RING(ring, 0xffffffff);
+ OUT_RING(ring, 0x00000010);
+
+ fd6_event_write(batch, ring, UNK_1D, true);
+ fd6_event_write(batch, ring, UNK_1C, true);
+
+ seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
+
+ fd6_event_write(batch, ring, 0x31, false);
+
+ OUT_PKT7(ring, CP_UNK_A6XX_14, 4);
+ OUT_RING(ring, 0x00000000);
+ OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
+ OUT_RING(ring, seqno);
+}
+
void
fd6_emit_init(struct pipe_context *pctx)
{
@@ -1305,4 +1340,5 @@ fd6_emit_init(struct pipe_context *pctx)
ctx->emit_const_bo = fd6_emit_const_bo;
ctx->emit_ib = fd6_emit_ib;
ctx->mem_to_mem = fd6_mem_to_mem;
+ ctx->framebuffer_barrier = fd6_framebuffer_barrier;
}
diff --git a/src/gallium/drivers/freedreno/freedreno_context.c b/src/gallium/drivers/freedreno/freedreno_context.c
index bf26d00bc1e..c30bfe44dd5 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.c
+++ b/src/gallium/drivers/freedreno/freedreno_context.c
@@ -88,6 +88,15 @@ out:
static void
fd_texture_barrier(struct pipe_context *pctx, unsigned flags)
{
+ if (flags == PIPE_TEXTURE_BARRIER_FRAMEBUFFER) {
+ struct fd_context *ctx = fd_context(pctx);
+
+ if (ctx->framebuffer_barrier) {
+ ctx->framebuffer_barrier(ctx);
+ return;
+ }
+ }
+
/* On devices that could sample from GMEM we could possibly do better.
* Or if we knew that we were doing GMEM bypass we could just emit a
* cache flush, perhaps? But we don't know if future draws would cause
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h b/src/gallium/drivers/freedreno/freedreno_context.h
index 4d22f8c470e..1fcebded21b 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -352,6 +352,9 @@ struct fd_context {
unsigned dst_off, struct pipe_resource *src, unsigned src_off,
unsigned sizedwords);
+ /* handling for barriers: */
+ void (*framebuffer_barrier)(struct fd_context *ctx);
+
/*
* Common pre-cooked VBO state (used for a3xx and later):
*/