freedreno: add adreno 420 support

Very initial support.  Basic stuff working (es2gears, es2tri, and maybe
about half of glmark2).  Expect broken stuff.  Still missing: mem->gmem
(restore), queries, mipmaps (blob segfaults!), hw binning, etc.

Signed-off-by: Rob Clark <[email protected]>

5 files changed, 22 insertions, 11 deletions

diff --git a/src/gallium/drivers/freedreno/ir3/ir3.c b/src/gallium/drivers/freedreno/ir3/ir3.c
index 60d4e4a15d5..41112460155 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3.c
@@ -540,7 +540,8 @@ static int (*emit[])(struct ir3_instruction *instr, void *ptr,
 	emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6,
 };
 
-void * ir3_assemble(struct ir3 *shader, struct ir3_info *info)
+void * ir3_assemble(struct ir3 *shader, struct ir3_info *info,
+		uint32_t gpu_id)
 {
 	uint32_t *ptr, *dwords;
 	uint32_t i;
@@ -550,11 +551,15 @@ void * ir3_assemble(struct ir3 *shader, struct ir3_info *info)
 	info->max_const     = -1;
 	info->instrs_count  = 0;
 
-	/* need a integer number of instruction "groups" (sets of four
-	 * instructions), so pad out w/ NOPs if needed:
-	 * (each instruction is 64bits)
+	/* need a integer number of instruction "groups" (sets of 16
+	 * instructions on a4xx or sets of 4 instructions on a3xx),
+	 * so pad out w/ NOPs if needed: (NOTE each instruction is 64bits)
 	 */
-	info->sizedwords = 2 * align(shader->instrs_count, 4);
+	if (gpu_id >= 400) {
+		info->sizedwords = 2 * align(shader->instrs_count, 16);
+	} else {
+		info->sizedwords = 2 * align(shader->instrs_count, 4);
+	}
 
 	ptr = dwords = calloc(4, info->sizedwords);
 
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h b/src/gallium/drivers/freedreno/ir3/ir3.h
index 8a5e9fd687c..06bad6e26fc 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -264,7 +264,7 @@ struct ir3_block {
 struct ir3 * ir3_create(void);
 void ir3_destroy(struct ir3 *shader);
 void * ir3_assemble(struct ir3 *shader,
-		struct ir3_info *info);
+		struct ir3_info *info, uint32_t gpu_id);
 void * ir3_alloc(struct ir3 *shader, int sz);
 
 struct ir3_block * ir3_block_create(struct ir3 *shader,
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 7de29f33d88..f28ce27a00d 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -49,7 +49,8 @@ static void dump_info(struct ir3_shader_variant *so, const char *str)
 	const char *type = (so->type == SHADER_VERTEX) ? "VERT" : "FRAG";
 
 	// for debug, dump some before/after info:
-	bin = ir3_assemble(so->ir, &info);
+	// TODO make gpu_id configurable on cmdline
+	bin = ir3_assemble(so->ir, &info, 320);
 	if (fd_mesa_debug & FD_DBG_DISASM) {
 		struct ir3_block *block = so->ir->block;
 		struct ir3_register *reg;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 1f7e869d9f3..0c74f2f26f2 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -56,7 +56,7 @@ assemble_variant(struct ir3_shader_variant *v)
 	struct fd_context *ctx = fd_context(v->shader->pctx);
 	uint32_t sz, *bin;
 
-	bin = ir3_assemble(v->ir, &v->info);
+	bin = ir3_assemble(v->ir, &v->info, ctx->screen->gpu_id);
 	sz = v->info.sizedwords * 4;
 
 	v->bo = fd_bo_new(ctx->dev, sz,
@@ -67,7 +67,11 @@ assemble_variant(struct ir3_shader_variant *v)
 
 	free(bin);
 
-	v->instrlen = v->info.sizedwords / 8;
+	if (ctx->screen->gpu_id >= 400) {
+		v->instrlen = v->info.sizedwords / (2 * 16);
+	} else {
+		v->instrlen = v->info.sizedwords / (2 * 4);
+	}
 
 	/* NOTE: if relative addressing is used, we set constlen in
 	 * the compiler (to worst-case value) since we don't know in
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 3d51603fcfb..f70886e2d3b 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -111,7 +111,8 @@ struct ir3_shader_variant {
 	struct ir3 *ir;
 
 	/* the instructions length is in units of instruction groups
-	 * (4 instructions, 8 dwords):
+	 * (4 instructions for a3xx, 16 instructions for a4xx.. each
+	 * instruction is 2 dwords):
 	 */
 	unsigned instrlen;
 
@@ -203,7 +204,7 @@ struct ir3_shader {
 	/* so far, only used for blit_prog shader.. values for
 	 * VPC_VARYING_PS_REPL[i].MODE
 	 */
-	uint32_t vpsrepl[4];
+	uint32_t vpsrepl[8];
 };