freedreno: shader_t -> gl_shader_stage

Just massive search/replace for the most part.

Step towards removing ir3 dependency on disasm.h which is shared by
a2xx.  One step closer to being able to move ir3 out of gallium.

Signed-off-by: Rob Clark <[email protected]>

7 files changed, 51 insertions, 64 deletions

diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h b/src/gallium/drivers/freedreno/ir3/ir3.h
index 1f47cef7e01..d031b570ec8 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -31,7 +31,7 @@
 #include "util/list.h"
 
 #include "instr-a3xx.h"
-#include "disasm.h"  /* TODO move 'enum shader_t' somewhere else.. */
+#include "disasm.h"  /* TODO move 'gl_shader_stage' somewhere else.. */
 
 /* low level intermediate representation of an adreno shader program */
 
@@ -1002,7 +1002,7 @@ int ir3_sched(struct ir3 *ir);
 
 /* register assignment: */
 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
-int ir3_ra(struct ir3 *ir3, enum shader_t type,
+int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
 		bool frag_coord, bool frag_face);
 
 /* legalize: */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 39f6c12c6bc..bb1133d3c7f 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -484,20 +484,7 @@ int main(int argc, char **argv)
 
 	v.key = key;
 	v.shader = &s;
-
-	switch (nir->info.stage) {
-	case MESA_SHADER_FRAGMENT:
-		s.type = v.type = SHADER_FRAGMENT;
-		break;
-	case MESA_SHADER_VERTEX:
-		s.type = v.type = SHADER_VERTEX;
-		break;
-	case MESA_SHADER_COMPUTE:
-		s.type = v.type = SHADER_COMPUTE;
-		break;
-	default:
-		errx(1, "unhandled shader stage: %d", nir->info.stage);
-	}
+	s.type = v.type = nir->info.stage;
 
 	info = "NIR compiler";
 	ret = ir3_compile_shader_nir(s.compiler, &v);
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 0c7a722aa0c..abdff85874f 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -139,16 +139,16 @@ compile_init(struct ir3_compiler *compiler,
 	struct ir3_context *ctx = rzalloc(NULL, struct ir3_context);
 
 	if (compiler->gpu_id >= 400) {
-		if (so->type == SHADER_VERTEX) {
+		if (so->type == MESA_SHADER_VERTEX) {
 			ctx->astc_srgb = so->key.vastc_srgb;
-		} else if (so->type == SHADER_FRAGMENT) {
+		} else if (so->type == MESA_SHADER_FRAGMENT) {
 			ctx->astc_srgb = so->key.fastc_srgb;
 		}
 
 	} else {
-		if (so->type == SHADER_VERTEX) {
+		if (so->type == MESA_SHADER_VERTEX) {
 			ctx->samples = so->key.vsamples;
-		} else if (so->type == SHADER_FRAGMENT) {
+		} else if (so->type == MESA_SHADER_FRAGMENT) {
 			ctx->samples = so->key.fsamples;
 		}
 	}
@@ -238,16 +238,16 @@ compile_init(struct ir3_compiler *compiler,
 	}
 
 	unsigned num_driver_params = 0;
-	if (so->type == SHADER_VERTEX) {
+	if (so->type == MESA_SHADER_VERTEX) {
 		num_driver_params = IR3_DP_VS_COUNT;
-	} else if (so->type == SHADER_COMPUTE) {
+	} else if (so->type == MESA_SHADER_COMPUTE) {
 		num_driver_params = IR3_DP_CS_COUNT;
 	}
 
 	so->constbase.driver_param = constoff;
 	constoff += align(num_driver_params, 4) / 4;
 
-	if ((so->type == SHADER_VERTEX) &&
+	if ((so->type == MESA_SHADER_VERTEX) &&
 			(compiler->gpu_id < 500) &&
 			so->shader->stream_output.num_outputs > 0) {
 		so->constbase.tfbo = constoff;
@@ -3219,7 +3219,7 @@ emit_function(struct ir3_context *ctx, nir_function_impl *impl)
 	if ((ctx->compiler->gpu_id < 500) &&
 			(ctx->so->shader->stream_output.num_outputs > 0) &&
 			!ctx->so->binning_pass) {
-		debug_assert(ctx->so->type == SHADER_VERTEX);
+		debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
 		emit_stream_out(ctx);
 	}
 
@@ -3295,7 +3295,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
 	so->inputs_count = MAX2(so->inputs_count, n + 1);
 	so->inputs[n].interpolate = in->data.interpolation;
 
-	if (ctx->so->type == SHADER_FRAGMENT) {
+	if (ctx->so->type == MESA_SHADER_FRAGMENT) {
 		for (int i = 0; i < ncomp; i++) {
 			struct ir3_instruction *instr = NULL;
 			unsigned idx = (n * 4) + i;
@@ -3351,7 +3351,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
 
 			ctx->ir->inputs[idx] = instr;
 		}
-	} else if (ctx->so->type == SHADER_VERTEX) {
+	} else if (ctx->so->type == MESA_SHADER_VERTEX) {
 		for (int i = 0; i < ncomp; i++) {
 			unsigned idx = (n * 4) + i;
 			compile_assert(ctx, idx < ctx->ir->ninputs);
@@ -3361,7 +3361,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
 		compile_error(ctx, "unknown shader type: %d\n", ctx->so->type);
 	}
 
-	if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
+	if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
 		so->total_in += ncomp;
 	}
 }
@@ -3383,7 +3383,7 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
 	ncomp = MAX2(ncomp, 4);
 	compile_assert(ctx, ncomp == 4);
 
-	if (ctx->so->type == SHADER_FRAGMENT) {
+	if (ctx->so->type == MESA_SHADER_FRAGMENT) {
 		switch (slot) {
 		case FRAG_RESULT_DEPTH:
 			comp = 2;  /* tgsi will write to .z component */
@@ -3398,7 +3398,7 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
 			compile_error(ctx, "unknown FS output name: %s\n",
 					gl_frag_result_name(slot));
 		}
-	} else if (ctx->so->type == SHADER_VERTEX) {
+	} else if (ctx->so->type == MESA_SHADER_VERTEX) {
 		switch (slot) {
 		case VARYING_SLOT_POS:
 			so->writes_pos = true;
@@ -3450,10 +3450,10 @@ max_drvloc(struct exec_list *vars)
 	return drvloc;
 }
 
-static const unsigned max_sysvals[SHADER_MAX] = {
-	[SHADER_FRAGMENT] = 24,  // TODO
-	[SHADER_VERTEX]  = 16,
-	[SHADER_COMPUTE] = 16, // TODO how many do we actually need?
+static const unsigned max_sysvals[] = {
+	[MESA_SHADER_FRAGMENT] = 24,  // TODO
+	[MESA_SHADER_VERTEX]  = 16,
+	[MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
 };
 
 static void
@@ -3482,7 +3482,7 @@ emit_instructions(struct ir3_context *ctx)
 	 * base for bary.f varying fetch instrs:
 	 */
 	struct ir3_instruction *vcoord = NULL;
-	if (ctx->so->type == SHADER_FRAGMENT) {
+	if (ctx->so->type == MESA_SHADER_FRAGMENT) {
 		struct ir3_instruction *xy[2];
 
 		vcoord = create_input_compmask(ctx, 0, 0x3);
@@ -3643,7 +3643,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 	inputs = ir->inputs;
 
 	/* but fixup actual inputs for frag shader: */
-	if (so->type == SHADER_FRAGMENT)
+	if (so->type == MESA_SHADER_FRAGMENT)
 		fixup_frag_inputs(ctx);
 
 	/* at this point, for binning pass, throw away unneeded outputs: */
@@ -3774,7 +3774,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 				reg = in->regs[0]->num - j;
 				actual_in++;
 				so->inputs[i].ncomp++;
-				if ((so->type == SHADER_FRAGMENT) && so->inputs[i].bary) {
+				if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
 					/* assign inloc: */
 					assert(in->regs[1]->flags & IR3_REG_IMMED);
 					in->regs[1]->iim_val = inloc + j;
@@ -3782,7 +3782,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 				}
 			}
 		}
-		if ((so->type == SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
+		if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
 			so->varying_in++;
 			so->inputs[i].compmask = (1 << maxcomp) - 1;
 			inloc += maxcomp;
@@ -3806,7 +3806,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 	}
 
 	/* Note that actual_in counts inputs that are not bary.f'd for FS: */
-	if (so->type == SHADER_VERTEX)
+	if (so->type == MESA_SHADER_VERTEX)
 		so->total_in = actual_in;
 	else
 		so->total_in = max_bary + 1;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index 7c2a8f83b62..bb00190ea38 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -137,12 +137,12 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 
 	if (key) {
 		switch (shader->type) {
-		case SHADER_FRAGMENT:
+		case MESA_SHADER_FRAGMENT:
 			tex_options.saturate_s = key->fsaturate_s;
 			tex_options.saturate_t = key->fsaturate_t;
 			tex_options.saturate_r = key->fsaturate_r;
 			break;
-		case SHADER_VERTEX:
+		case MESA_SHADER_VERTEX:
 			tex_options.saturate_s = key->vsaturate_s;
 			tex_options.saturate_t = key->vsaturate_t;
 			tex_options.saturate_r = key->vsaturate_r;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_ra.c b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
index 9bccd9dd55f..3218d92815d 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_ra.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_ra.c
@@ -326,7 +326,7 @@ struct ir3_ra_instr_data {
 /* register-assign context, per-shader */
 struct ir3_ra_ctx {
 	struct ir3 *ir;
-	enum shader_t type;
+	gl_shader_stage type;
 	bool frag_face;
 
 	struct ir3_ra_reg_set *set;
@@ -1106,7 +1106,7 @@ retry:
 	return 0;
 }
 
-int ir3_ra(struct ir3 *ir, enum shader_t type,
+int ir3_ra(struct ir3 *ir, gl_shader_stage type,
 		bool frag_coord, bool frag_face)
 {
 	struct ir3_ra_ctx ctx = {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index d00323b3bf7..797d75e3155 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -153,7 +153,7 @@ assemble_variant(struct ir3_shader_variant *v)
 	if (shader_debug_enabled(v->shader->type)) {
 		fprintf(stderr, "Native code for unnamed %s shader %s:\n",
 			shader_stage_name(v->shader->type), v->shader->nir->info.name);
-		if (v->shader->type == SHADER_FRAGMENT)
+		if (v->shader->type == MESA_SHADER_FRAGMENT)
 			fprintf(stderr, "SIMD0\n");
 		ir3_shader_disasm(v, bin, stderr);
 	}
@@ -239,7 +239,7 @@ shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
 	 * variants:
 	 */
 	switch (shader->type) {
-	case SHADER_FRAGMENT:
+	case MESA_SHADER_FRAGMENT:
 		if (key.has_per_samp) {
 			key.vsaturate_s = 0;
 			key.vsaturate_t = 0;
@@ -248,7 +248,7 @@ shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
 			key.vsamples = 0;
 		}
 		break;
-	case SHADER_VERTEX:
+	case MESA_SHADER_VERTEX:
 		key.color_two_side = false;
 		key.half_precision = false;
 		key.rasterflat = false;
@@ -312,7 +312,7 @@ ir3_shader_destroy(struct ir3_shader *shader)
 
 struct ir3_shader *
 ir3_shader_create(struct ir3_compiler *compiler,
-		const struct pipe_shader_state *cso, enum shader_t type,
+		const struct pipe_shader_state *cso, gl_shader_stage type,
 		struct pipe_debug_callback *debug)
 {
 	struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
@@ -366,7 +366,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
 
 	shader->compiler = compiler;
 	shader->id = ++shader->compiler->shader_count;
-	shader->type = SHADER_COMPUTE;
+	shader->type = MESA_SHADER_COMPUTE;
 
 	nir_shader *nir;
 	if (cso->ir_type == PIPE_SHADER_IR_NIR) {
@@ -456,7 +456,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 	disasm_a3xx(bin, so->info.sizedwords, 0, out);
 
 	switch (so->type) {
-	case SHADER_VERTEX:
+	case MESA_SHADER_VERTEX:
 		fprintf(out, "; %s: outputs:", type);
 		for (i = 0; i < so->outputs_count; i++) {
 			uint8_t regid = so->outputs[i].regid;
@@ -476,7 +476,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 		}
 		fprintf(out, "\n");
 		break;
-	case SHADER_FRAGMENT:
+	case MESA_SHADER_FRAGMENT:
 		fprintf(out, "; %s: outputs:", type);
 		for (i = 0; i < so->outputs_count; i++) {
 			uint8_t regid = so->outputs[i].regid;
@@ -517,11 +517,11 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 
 	/* print shader type specific info: */
 	switch (so->type) {
-	case SHADER_VERTEX:
+	case MESA_SHADER_VERTEX:
 		dump_output(out, so, VARYING_SLOT_POS, "pos");
 		dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 		break;
-	case SHADER_FRAGMENT:
+	case MESA_SHADER_FRAGMENT:
 		dump_reg(out, "pos (bary)",
 			ir3_find_sysval_regid(so, SYSTEM_VALUE_VARYING_COORD));
 		dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
@@ -874,7 +874,7 @@ void
 ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 		struct fd_context *ctx, const struct pipe_draw_info *info)
 {
-	debug_assert(v->type == SHADER_VERTEX);
+	debug_assert(v->type == MESA_SHADER_VERTEX);
 
 	emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
 
@@ -939,12 +939,12 @@ ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 				ctx->mem_to_mem(ring, vertex_params_rsc, 0,
 						indirect->buffer, src_off, 1);
 
-				ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
+				ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
 						vertex_params_size, NULL, vertex_params_rsc);
 
 				pipe_resource_reference(&vertex_params_rsc, NULL);
 			} else {
-				ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
+				ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
 						vertex_params_size, vertex_params, NULL);
 			}
 
@@ -960,7 +960,7 @@ void
 ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 		struct fd_context *ctx)
 {
-	debug_assert(v->type == SHADER_FRAGMENT);
+	debug_assert(v->type == MESA_SHADER_FRAGMENT);
 
 	emit_common_consts(v, ring, ctx, PIPE_SHADER_FRAGMENT);
 }
@@ -970,7 +970,7 @@ void
 ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 		struct fd_context *ctx, const struct pipe_grid_info *info)
 {
-	debug_assert(v->type == SHADER_COMPUTE);
+	debug_assert(v->type == MESA_SHADER_COMPUTE);
 
 	emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
 
@@ -1004,7 +1004,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 				indirect_offset = info->indirect_offset;
 			}
 
-			ctx->emit_const(ring, SHADER_COMPUTE, offset * 4,
+			ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4,
 					indirect_offset, 4, NULL, indirect);
 
 			pipe_resource_reference(&indirect, NULL);
@@ -1018,7 +1018,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 				[IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
 			};
 
-			ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
+			ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4, 0,
 					ARRAY_SIZE(compute_params), compute_params, NULL);
 		}
 	}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 1c31061af47..270b9c09110 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -345,12 +345,12 @@ struct ir3_shader_variant {
 	struct ir3_shader_variant *next;
 
 	/* replicated here to avoid passing extra ptrs everywhere: */
-	enum shader_t type;
+	gl_shader_stage type;
 	struct ir3_shader *shader;
 };
 
 struct ir3_shader {
-	enum shader_t type;
+	gl_shader_stage type;
 
 	/* shader id (for debug): */
 	uint32_t id;
@@ -370,7 +370,7 @@ struct ir3_shader {
 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 
 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
-		const struct pipe_shader_state *cso, enum shader_t type,
+		const struct pipe_shader_state *cso, gl_shader_stage type,
 		struct pipe_debug_callback *debug);
 struct ir3_shader *
 ir3_shader_create_compute(struct ir3_compiler *compiler,
@@ -399,9 +399,9 @@ static inline const char *
 ir3_shader_stage(struct ir3_shader *shader)
 {
 	switch (shader->type) {
-	case SHADER_VERTEX:     return "VERT";
-	case SHADER_FRAGMENT:   return "FRAG";
-	case SHADER_COMPUTE:    return "CL";
+	case MESA_SHADER_VERTEX:     return "VERT";
+	case MESA_SHADER_FRAGMENT:   return "FRAG";
+	case MESA_SHADER_COMPUTE:    return "CL";
 	default:
 		unreachable("invalid type");
 		return NULL;