diff options
| author | Rob Clark <[email protected]> | 2015-07-25 13:48:07 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2015-07-27 13:51:06 -0400 |
| commit | 020301baccc77e5753ead1e890c0cf24a9675517 (patch) | |
| tree | 1d366c4e5155642e639f4c4d44ea5c924a672492 /src/gallium/drivers/freedreno/ir3/ir3.h | |
| parent | a240748de52f2e469e91b60d29ae872828a594d7 (diff) | |
freedreno/ir3: add support for store instructions
For store instructions, the "dst" register is a read register, not a
written register. (Ie. it is the address to store to.) Lets not
confuse register allocation, scheduling, etc, with these details.
Instead just leave a dummy instr->regs[0], and take "dst" from
instr->regs[1] and srcs following.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/ir3/ir3.h')
| -rw-r--r-- | src/gallium/drivers/freedreno/ir3/ir3.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h b/src/gallium/drivers/freedreno/ir3/ir3.h index c3b61a0fe01..e68170dec58 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3.h +++ b/src/gallium/drivers/freedreno/ir3/ir3.h @@ -554,6 +554,26 @@ is_store(struct ir3_instruction *instr) return false; } +static inline bool is_load(struct ir3_instruction *instr) +{ + if (is_mem(instr)) { + switch (instr->opc) { + case OPC_LDG: + case OPC_LDL: + case OPC_LDP: + case OPC_L2G: + case OPC_LDLW: + case OPC_LDC_4: + case OPC_LDLV: + /* probably some others too.. */ + return true; + default: + break; + } + } + return false; +} + static inline bool is_input(struct ir3_instruction *instr) { /* in some cases, ldlv is used to fetch varying without @@ -1043,6 +1063,7 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type, /* cat6 instructions: */ INSTR2(6, LDLV) INSTR2(6, LDG) +INSTR3(6, STG) /* ************************************************************************* */ /* split this out or find some helper to use.. like main/bitset.h.. */ |