diff options
| author | Rob Clark <[email protected]> | 2014-01-07 10:55:07 -0500 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2014-01-08 16:30:18 -0500 |
| commit | c0766528baaef48902c87bbdaa4f5926c472269b (patch) | |
| tree | f825706059f50c37a9fda7961ec596b0fb6a65da /src/gallium/drivers/freedreno/freedreno_context.h | |
| parent | bfb44c24bc1eff850d47984b2cb60c957ffc143d (diff) | |
freedreno/a3xx: support for hw binning pass
The binning pass sorts vertices into which bins/tiles they apply to.
The visibility information generated during the binning pass can be
used to speed up the rendering pass by filtering out vertices which
do not apply to the current tile. See:
https://github.com/freedreno/freedreno/wiki/Adreno-tiling#optimized-approach
This brings a significant fps boost. A rough assortment of tests
(supertuxkart, etracer, tremulous, glmark2 'build' test, etc) seems
to yield a ~35-45% fps improvement.
For now, to be conservative, the binning pass is not enabled yet by
default. To enable it use:
FD_MESA_DEBUG=binning
So far I haven't found anything that breaks with binning enabled,
but I'd like a bit more testing before I enable it as default.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/freedreno_context.h')
| -rw-r--r-- | src/gallium/drivers/freedreno/freedreno_context.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h b/src/gallium/drivers/freedreno/freedreno_context.h index a8abbca7a62..a0227e49c03 100644 --- a/src/gallium/drivers/freedreno/freedreno_context.h +++ b/src/gallium/drivers/freedreno/freedreno_context.h @@ -111,7 +111,7 @@ struct fd_context { */ enum { /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */ - FD_BUFFER_COLOR = PIPE_CLEAR_COLOR, + FD_BUFFER_COLOR = PIPE_CLEAR_COLOR0, FD_BUFFER_DEPTH = PIPE_CLEAR_DEPTH, FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL, FD_BUFFER_ALL = FD_BUFFER_COLOR | FD_BUFFER_DEPTH | FD_BUFFER_STENCIL, @@ -148,9 +148,14 @@ struct fd_context { struct fd_ringbuffer *rings[4]; unsigned rings_idx; + /* normal draw/clear cmds: */ struct fd_ringbuffer *ring; struct fd_ringmarker *draw_start, *draw_end; + /* binning pass draw/clear cmds: */ + struct fd_ringbuffer *binning_ring; + struct fd_ringmarker *binning_start, *binning_end; + /* Keep track if WAIT_FOR_IDLE is needed for registers we need * to update via RMW: */ @@ -165,6 +170,11 @@ struct fd_context { uint32_t rbrc_draw; } rmw; + /* Keep track of DRAW initiators that need to be patched up depending + * on whether we using binning or not: + */ + struct util_dynarray draw_patches; + struct pipe_scissor_state scissor; /* we don't have a disable/enable bit for scissor, so instead we keep |