diff options
| author | Rob Clark <[email protected]> | 2014-12-01 17:41:21 -0500 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2014-12-01 20:31:23 -0500 |
| commit | 81194ac7675b85a5d2a2a79293602064d1a992a0 (patch) | |
| tree | ee7967ceeb8d87eeaf2fdc10e27aef3f71b31547 /src/gallium/drivers/freedreno/adreno_pm4.xml.h | |
| parent | 5df88c2096281f416b2738debac1c4c329e29673 (diff) | |
freedreno: update generated headers
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/adreno_pm4.xml.h')
| -rw-r--r-- | src/gallium/drivers/freedreno/adreno_pm4.xml.h | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h index 87ae18940a9..41551ba4353 100644 --- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h +++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h @@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15053 bytes, from 2014-11-09 15:45:47) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 63601 bytes, from 2014-11-30 15:38:05) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49147 bytes, from 2014-11-30 15:38:05) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49142 bytes, from 2014-12-02 01:03:04) Copyright (C) 2013-2014 by the following authors: - Rob Clark <[email protected]> (robclark) @@ -172,7 +172,9 @@ enum adreno_pm4_type3_packets { CP_DRAW_INDIRECT = 40, CP_DRAW_INDX_INDIRECT = 41, CP_DRAW_AUTO = 36, + CP_UNKNOWN_19 = 25, CP_UNKNOWN_1A = 26, + CP_UNKNOWN_4E = 78, CP_WIDE_REG_WRITE = 116, IN_IB_PREFETCH_END = 23, IN_SUBBLK_PREFETCH = 31, @@ -203,6 +205,12 @@ enum adreno_state_src { SS_INDIRECT = 4, }; +enum a4xx_index_size { + INDEX4_SIZE_8_BIT = 0, + INDEX4_SIZE_16_BIT = 1, + INDEX4_SIZE_32_BIT = 2, +}; + #define REG_CP_LOAD_STATE_0 0x00000000 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 @@ -374,21 +382,12 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va { return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; } -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700 -#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) -{ - return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; -} -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800 -#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11 -static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val) +#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 +#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 +static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) { return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; } -#define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000 -#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000 -#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000 #define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__MASK 0xffff0000 #define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__SHIFT 16 static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES(uint32_t val) |