freedreno: update generated headers

Signed-off-by: Rob Clark <[email protected]>

3 files changed, 14 insertions, 9 deletions

diff --git a/src/gallium/drivers/freedreno/a6xx/a6xx.xml.h b/src/gallium/drivers/freedreno/a6xx/a6xx.xml.h
index b1a03f7ff7f..ec538f15d4c 100644
--- a/src/gallium/drivers/freedreno/a6xx/a6xx.xml.h
+++ b/src/gallium/drivers/freedreno/a6xx/a6xx.xml.h
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  36805 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  13634 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-14 22:24:38)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  42393 bytes, from 2018-08-17 13:46:53)
 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-14 22:24:38)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 102772 bytes, from 2018-08-14 22:24:38)
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-08-17 13:46:53)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 102966 bytes, from 2018-08-17 13:46:53)
 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
 
@@ -2318,6 +2318,9 @@ static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
 	return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
 }
 
+#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
+#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z		0x00000001
+
 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
@@ -2861,7 +2864,6 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 {
 	return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
 }
-#define A6XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00008000
 
 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
 #define A6XX_RB_MRT_PITCH__MASK					0xffffffff
@@ -2949,6 +2951,9 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
 	return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
 }
 
+#define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
+#define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z			0x00000001
+
 #define REG_A6XX_RB_DEPTH_CNTL					0x00008871
 #define A6XX_RB_DEPTH_CNTL_Z_ENABLE				0x00000001
 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
@@ -3426,7 +3431,8 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
 #define A6XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
 #define A6XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
 
-#define REG_A6XX_VPC_UNKNOWN_9306				0x00009306
+#define REG_A6XX_VPC_SO_OVERRIDE				0x00009306
+#define A6XX_VPC_SO_OVERRIDE_SO_DISABLE				0x00000001
 
 #define REG_A6XX_VPC_UNKNOWN_9600				0x00009600
 
@@ -4035,7 +4041,6 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
 }
 #define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
 #define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
-#define A6XX_SP_FS_MRT_REG_COLOR_SRGB				0x00000400
 
 #define REG_A6XX_SP_UNKNOWN_A99E				0x0000a99e
 
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index f1dd081ebc3..c526a180a63 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -997,7 +997,7 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 	WRITE(REG_A6XX_VPC_UNKNOWN_9236, 1);
 	WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
 
-	WRITE(REG_A6XX_VPC_UNKNOWN_9306, 1);
+	WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 
 	WRITE(REG_A6XX_PC_UNKNOWN_9801, 0);
 	WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 9a51b1c4600..dd0f16a2bcc 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -505,8 +505,8 @@ fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 
 	set_window_offset(ring, x1, y1);
 
-	OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9306, 1);
-	OUT_RING(ring, 1);
+	OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
+	OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 
 	if (use_hw_binning(batch)) {
 		struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];