diff options
| author | Rob Clark <[email protected]> | 2018-06-20 12:50:40 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2018-06-21 08:54:47 -0400 |
| commit | d03bd103f873289ccdb12cc13afc0e35acc6f114 (patch) | |
| tree | 1a1df8489fcbf2bb536583827cb3674af1529970 /src/gallium/drivers/freedreno/a5xx | |
| parent | e1e40935b4adb60e47e90e6d83589c369a26b6e2 (diff) | |
freedreno/a5xx: fix gpu hangs with large compute shaders
Similar to the combined limit for VS+FS, there is an upper limit for
shader size to run from internel memory.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/a5xx')
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_compute.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c index c98442efba6..3d4b155960c 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c @@ -76,6 +76,13 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, const unsigned *local_size = info->block; const struct ir3_info *i = &v->info; enum a3xx_threadsize thrsz; + unsigned instrlen = v->instrlen; + + /* if shader is more than 32*16 instructions, don't preload it. Similar + * to the combined restriction of 64*16 for VS+FS + */ + if (instrlen > 32) + instrlen = 0; /* maybe the limit should be 1024.. basically if we can't have full * occupancy, use TWO_QUAD mode to reduce divergence penalty. @@ -107,7 +114,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, A5XX_HLSQ_CS_CONFIG_ENABLED); OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1); - OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(v->instrlen) | + OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(instrlen) | COND(v->has_ssbo, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE)); OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1); @@ -118,7 +125,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, unsigned constlen = align(v->constlen, 4) / 4; OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2); OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */ - OUT_RING(ring, v->instrlen); /* HLSQ_CS_INSTRLEN */ + OUT_RING(ring, instrlen); /* HLSQ_CS_INSTRLEN */ OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2); OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */ @@ -137,7 +144,8 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v, A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id)); OUT_RING(ring, 0x1); /* HLSQ_CS_CNTL_1 */ - fd5_emit_shader(ring, v); + if (instrlen > 0) + fd5_emit_shader(ring, v); } static void |