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authorRob Clark <[email protected]>2018-06-15 16:32:42 -0400
committerRob Clark <[email protected]>2018-06-21 08:54:47 -0400
commitcf0c7258ee0524709ab6d05a9aafc7415361bd23 (patch)
tree1d22ac00b91293e71253373586dd79c1506a3442 /src/gallium/drivers/freedreno/a5xx
parentb6e690ef80f71cc62fa1095a2601087341be22a3 (diff)
freedreno/a5xx: MSAA
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/a5xx')
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_blend.c2
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_context.c2
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_draw.c5
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_emit.c17
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_gmem.c31
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_screen.c20
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_texture.c1
7 files changed, 54 insertions, 24 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
index 98b6d4498e5..fee6ba346b7 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
@@ -140,8 +140,10 @@ fd5_blend_state_create(struct pipe_context *pctx,
}
so->rb_blend_cntl = A5XX_RB_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
+ COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
so->sp_blend_cntl = A5XX_SP_BLEND_CNTL_UNK8 |
+ COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) |
COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
return so;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_context.c b/src/gallium/drivers/freedreno/a5xx/fd5_context.c
index 426a8e0b046..c43a8ad2eca 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_context.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_context.c
@@ -101,6 +101,8 @@ fd5_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
if (!pctx)
return NULL;
+ util_blitter_set_texture_multisample(fd5_ctx->base.blitter, true);
+
fd5_ctx->vs_pvt_mem = fd_bo_new(screen->dev, 0x2000,
DRM_FREEDRENO_GEM_TYPE_KMEM);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
index 8c3be5eabc8..56525e0a9a4 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
@@ -106,8 +106,6 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.vclamp_color = ctx->rasterizer->clamp_vertex_color,
.fclamp_color = ctx->rasterizer->clamp_fragment_color,
.rasterflat = ctx->rasterizer->flatshade,
- .half_precision = ctx->in_blit &&
- fd_half_precision(&ctx->batch->framebuffer),
.ucp_enables = ctx->rasterizer->clip_plane_enable,
.has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate ||
fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb),
@@ -209,7 +207,8 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_RING(ring, 0x20fffff);
OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
- OUT_RING(ring, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0));
+ OUT_RING(ring, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
+ COND(zsbuf->base.nr_samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 9d17bda476c..d891e68aabc 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -641,7 +641,8 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd5_rasterizer_stateobj(ctx->rasterizer);
OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
- OUT_RING(ring, rasterizer->gras_su_cntl);
+ OUT_RING(ring, rasterizer->gras_su_cntl |
+ COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
OUT_RING(ring, rasterizer->gras_su_point_minmax);
@@ -734,7 +735,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
}
}
- if ((dirty & FD_DIRTY_BLEND)) {
+ if (dirty & FD_DIRTY_BLEND) {
struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
uint32_t i;
@@ -764,14 +765,18 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, blend_control);
}
- OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
- OUT_RING(ring, blend->rb_blend_cntl |
- A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
-
OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
OUT_RING(ring, blend->sp_blend_cntl);
}
+ if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
+ struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
+
+ OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
+ OUT_RING(ring, blend->rb_blend_cntl |
+ A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
+ }
+
if (dirty & FD_DIRTY_BLEND_COLOR) {
struct pipe_blend_color *bcolor = &ctx->blend_color;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index 1dacef067b3..4a883eefd5c 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -85,7 +85,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
psurf->u.tex.first_layer);
if (gmem) {
- stride = gmem->bin_w * rsc->cpp;
+ stride = gmem->bin_w * gmem->cbuf_cpp[i];
size = stride * gmem->bin_h;
base = gmem->cbuf_base[i];
} else {
@@ -580,21 +580,23 @@ fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
emit_zs(ring, pfb->zsbuf, gmem);
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
- // TODO MSAA
+ enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
+
OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
- OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
- OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
- A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
+ OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(samples));
+ OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
+ COND(samples == MSAA_ONE, A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
- OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
- OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
- A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
+ OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
+ OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
+ COND(samples == MSAA_ONE, A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
+
OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
- OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
- OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
- A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
+ OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(samples));
+ OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(samples) |
+ COND(samples == MSAA_ONE, A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE));
}
@@ -640,6 +642,12 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+// bool msaa_resolve = pfb->samples > 1;
+ bool msaa_resolve = false;
+ OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
+ OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE));
+
fd5_emit_blit(batch->ctx, ring);
}
@@ -742,7 +750,6 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
emit_zs(ring, pfb->zsbuf, NULL);
emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
- // TODO MSAA
OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_screen.c b/src/gallium/drivers/freedreno/a5xx/fd5_screen.c
index 7d7e76e869c..6f614751f46 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_screen.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_screen.c
@@ -35,6 +35,20 @@
#include "ir3_compiler.h"
+static bool
+valid_sample_count(unsigned sample_count)
+{
+ switch (sample_count) {
+ case 0:
+ case 1:
+ case 2:
+ case 4:
+ return true;
+ default:
+ return false;
+ }
+}
+
static boolean
fd5_screen_is_format_supported(struct pipe_screen *pscreen,
enum pipe_format format,
@@ -45,7 +59,7 @@ fd5_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned retval = 0;
if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
- (sample_count > 1) || /* TODO add MSAA */
+ !valid_sample_count(sample_count) ||
!util_format_is_supported(format, usage)) {
DBG("not supported: format=%s, target=%d, sample_count=%d, usage=%x",
util_format_name(format), target, sample_count, usage);
@@ -57,11 +71,11 @@ fd5_screen_is_format_supported(struct pipe_screen *pscreen,
retval |= PIPE_BIND_VERTEX_BUFFER;
}
- if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+ if ((usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) &&
(target == PIPE_BUFFER ||
util_format_get_blocksize(format) != 12) &&
(fd5_pipe2tex(format) != (enum a5xx_tex_fmt)~0)) {
- retval |= PIPE_BIND_SAMPLER_VIEW;
+ retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
}
if ((usage & (PIPE_BIND_RENDER_TARGET |
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
index 9795189b6ef..e8e29d0367a 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
@@ -217,6 +217,7 @@ fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
so->texconst0 =
A5XX_TEX_CONST_0_FMT(fd5_pipe2tex(format)) |
+ A5XX_TEX_CONST_0_SAMPLES(fd_msaa_samples(prsc->nr_samples)) |
fd5_tex_swiz(format, cso->swizzle_r, cso->swizzle_g,
cso->swizzle_b, cso->swizzle_a);