freedreno/ir3: move binning_pass out of shader variant key

Prep work for a following patch, that introduces a cache to map from
program state (all shader stages) plus variant key to pre-baked hw
state (which could be emit'd via CP_SET_DRAW_STATE, for example).
To do that, we really want the variant key to be immutable, and to
treat the binning pass shader as an extra shader stage, rather than
as a VS variant.

Signed-off-by: Rob Clark <[email protected]>

5 files changed, 20 insertions, 17 deletions

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
index 66ed7a4af57..1e084fd4c3b 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
@@ -188,7 +188,7 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
 
 	emit_setup(ctx);
 
-	v = ir3_shader_variant(so->shader, key, &ctx->debug);
+	v = ir3_shader_variant(so->shader, key, false, &ctx->debug);
 	if (!v)
 		return;
 
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
index 96ff1a35945..bbb12897b85 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.c
@@ -60,9 +60,9 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 			info->restart_index : 0xffffffff);
 
-	fd5_emit_render_cntl(ctx, false, emit->key.binning_pass);
+	fd5_emit_render_cntl(ctx, false, emit->binning_pass);
 	fd5_draw_emit(ctx->batch, ring, primtype,
-			emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
+			emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 			info, index_offset);
 }
 
@@ -144,13 +144,13 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 	 */
 	emit.no_lrz_write = fp->writes_pos || fp->has_kill;
 
-	emit.key.binning_pass = false;
+	emit.binning_pass = false;
 	emit.dirty = dirty;
 
 	draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 
 	/* and now binning pass: */
-	emit.key.binning_pass = true;
+	emit.binning_pass = true;
 	emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 	emit.vp = NULL;   /* we changed key so need to refetch vp */
 	emit.fp = NULL;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index e3bf9e26ba4..c666b25f137 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -524,7 +524,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 	emit_marker5(ring, 5);
 
-	if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
+	if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
 		unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
 
 		for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
@@ -566,7 +566,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 			if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
 				gras_lrz_cntl = 0;
-			else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
+			else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
 				gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
 
 			OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
@@ -685,7 +685,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
 		unsigned nr = pfb->nr_cbufs;
 
-		if (emit->key.binning_pass)
+		if (emit->binning_pass)
 			nr = 0;
 		else if (ctx->rasterizer->rasterizer_discard)
 			nr = 0;
@@ -701,7 +701,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	}
 
 	ir3_emit_vs_consts(vp, ring, ctx, emit->info);
-	if (!emit->key.binning_pass)
+	if (!emit->binning_pass)
 		ir3_emit_fs_consts(fp, ring, ctx);
 
 	struct pipe_stream_output_info *info = &vp->shader->stream_output;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
index bed52d4e87f..69ea3fa06a4 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.h
@@ -44,6 +44,7 @@ struct fd5_emit {
 	const struct fd_vertex_state *vtx;
 	const struct fd_program_stateobj *prog;
 	const struct pipe_draw_info *info;
+	bool binning_pass;
 	struct ir3_shader_key key;
 	enum fd_dirty_3d_state dirty;
 
@@ -77,7 +78,8 @@ fd5_emit_get_vp(struct fd5_emit *emit)
 {
 	if (!emit->vp) {
 		struct ir3_shader *shader = emit->prog->vp;
-		emit->vp = ir3_shader_variant(shader, emit->key, emit->debug);
+		emit->vp = ir3_shader_variant(shader, emit->key,
+				emit->binning_pass, emit->debug);
 	}
 	return emit->vp;
 }
@@ -86,13 +88,14 @@ static inline const struct ir3_shader_variant *
 fd5_emit_get_fp(struct fd5_emit *emit)
 {
 	if (!emit->fp) {
-		if (emit->key.binning_pass) {
+		if (emit->binning_pass) {
 			/* use dummy stateobj to simplify binning vs non-binning: */
 			static const struct ir3_shader_variant binning_fp = {};
 			emit->fp = &binning_fp;
 		} else {
 			struct ir3_shader *shader = emit->prog->fp;
-			emit->fp = ir3_shader_variant(shader, emit->key, emit->debug);
+			emit->fp = ir3_shader_variant(shader, emit->key,
+					false, emit->debug);
 		}
 	}
 	return emit->fp;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 2a6e3334aed..a30678d0477 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -448,7 +448,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	ir3_link_shaders(&l, s[VS].v, s[FS].v);
 
 	if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
-			!emit->key.binning_pass)
+			!emit->binning_pass)
 		link_stream_out(&l, s[VS].v);
 
 	BITSET_DECLARE(varbs, 128) = {0};
@@ -474,7 +474,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	}
 
 	if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
-			!emit->key.binning_pass) {
+			!emit->binning_pass) {
 		emit_stream_out(ring, s[VS].v, &l);
 
 		OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
@@ -534,7 +534,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 	fd5_context(ctx)->max_loc = l.max_loc;
 
-	if (emit->key.binning_pass) {
+	if (emit->binning_pass) {
 		OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
 		OUT_RING(ring, 0x00000000);    /* SP_FS_OBJ_START_LO */
 		OUT_RING(ring, 0x00000000);    /* SP_FS_OBJ_START_HI */
@@ -613,7 +613,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
 			A5XX_VPC_PACK_PSIZELOC(psize_loc));
 
-	if (!emit->key.binning_pass) {
+	if (!emit->binning_pass) {
 		uint32_t vinterp[8], vpsrepl[8];
 
 		memset(vinterp, 0, sizeof(vinterp));
@@ -704,7 +704,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			OUT_RING(ring, vpsrepl[i]);   /* VPC_VARYING_PS_REPL[i] */
 	}
 
-	if (!emit->key.binning_pass)
+	if (!emit->binning_pass)
 		if (s[FS].instrlen)
 			fd5_emit_shader(ring, s[FS].v);