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authorIlia Mirkin <[email protected]>2017-07-09 18:06:25 -0400
committerIlia Mirkin <[email protected]>2017-07-09 18:36:13 -0400
commit6c7b7aa3d8323a7cde5ab2b84fabc16913adeab4 (patch)
tree3f085a01fd4b3703dd01a81510d9a1c8534650b6 /src/gallium/drivers/freedreno/a5xx
parent7b5f2e00706899e26aaa78e595e21522ccba9c5c (diff)
a5xx: fix condition for updating *_FS_OUTPUT_CNTL
The register values depend on the currently set program, so make sure to revalidate when the program changes. Fixes glsl-1.10-fragdepth as well as dEQP-GLES3.functional.shaders.fragdepth.compare.* Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/a5xx')
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_emit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 378ee2443b6..eeddef52ae3 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -642,7 +642,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
}
- if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
+ if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
unsigned nr = pfb->nr_cbufs;