freedreno: move more batch related tracking to fd_batch

To flush batches out of order, the gmem code needs to not depend on
state from fd_context (since that may apply to a more recent batch).
So this all moves into batch.

The one exception is the gmem/pipe/tile state itself.  But this is
only used from gmem code (and batches are flushed serially).  The
alternative would be having to re-calculate GMEM layout on every
batch, even if the dimensions of the render targets are the same.

Note: This opens up the possibility of pushing gmem/submit into a
helper thread.

Signed-off-by: Rob Clark <[email protected]>

4 files changed, 83 insertions, 78 deletions

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
index e0513860a71..8270c4f0cff 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
@@ -68,8 +68,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			(info->mode == PIPE_PRIM_POINTS))
 		primtype = DI_PT_POINTLIST_PSIZE;
 
-	fd4_draw_emit(ctx, ring,
-			primtype,
+	fd4_draw_emit(ctx->batch, ring, primtype,
 			emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 			info);
 }
@@ -233,7 +232,7 @@ fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 
 	fd4_emit_state(ctx, ring, &emit);
 	fd4_emit_vertex_bufs(ring, &emit);
-	reset_viewport(ring, &ctx->framebuffer);
+	reset_viewport(ring, &ctx->batch->framebuffer);
 
 	OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 	OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
@@ -244,7 +243,7 @@ fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 	OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 	OUT_RING(ring, 0x00000002);
 
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+	fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 }
 
@@ -254,7 +253,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
 {
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
 	struct fd_ringbuffer *ring = ctx->batch->draw;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 	unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 	unsigned dirty = ctx->dirty;
 	unsigned i;
@@ -390,7 +389,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
 	OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 	OUT_RING(ring, 0x00000001);
 
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
+	fd4_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 
 	OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
index 5f5f6cd1e5f..57b16870fab 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h
@@ -48,7 +48,7 @@ static inline uint32_t DRAW4(enum pc_di_primtype prim_type,
 }
 
 static inline void
-fd4_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
+fd4_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
 		enum pc_di_primtype primtype,
 		enum pc_di_vis_cull_mode vismode,
 		enum pc_di_src_sel src_sel, uint32_t count,
@@ -70,7 +70,7 @@ fd4_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		 * we know if we are binning or not
 		 */
 		OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0),
-				&ctx->draw_patches);
+				&batch->draw_patches);
 	} else {
 		OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode));
 	}
@@ -84,7 +84,7 @@ fd4_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 	emit_marker(ring, 7);
 
-	fd_reset_wfi(ctx);
+	fd_reset_wfi(batch->ctx);
 }
 
 
@@ -101,18 +101,19 @@ fd4_size2indextype(unsigned index_size)
 	return INDEX4_SIZE_32_BIT;
 }
 static inline void
-fd4_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
+fd4_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
 		enum pc_di_primtype primtype,
 		enum pc_di_vis_cull_mode vismode,
 		const struct pipe_draw_info *info)
 {
-	struct pipe_index_buffer *idx = &ctx->indexbuf;
 	struct pipe_resource *idx_buffer = NULL;
 	enum a4xx_index_size idx_type;
 	enum pc_di_src_sel src_sel;
 	uint32_t idx_size, idx_offset;
 
 	if (info->indexed) {
+		struct pipe_index_buffer *idx = &batch->ctx->indexbuf;
+
 		assert(!idx->user_buffer);
 
 		idx_buffer = idx->buffer;
@@ -128,7 +129,7 @@ fd4_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		src_sel = DI_SRC_SEL_AUTO_INDEX;
 	}
 
-	fd4_draw(ctx, ring, primtype, vismode, src_sel,
+	fd4_draw(batch, ring, primtype, vismode, src_sel,
 			info->count, info->instance_count,
 			idx_type, idx_size, idx_offset, idx_buffer);
 }
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 5bb712c755c..88e1a40ec90 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -505,7 +505,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	emit_marker(ring, 5);
 
 	if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
-		struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+		struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 		unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 
 		for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
@@ -525,7 +525,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 	if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
 		struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
-		struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+		struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 		uint32_t rb_alpha_control = zsa->rb_alpha_control;
 
 		if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
@@ -625,10 +625,10 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
 				A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
 
-		ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
-		ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
-		ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
-		ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
+		ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
+		ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
+		ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
+		ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
 	}
 
 	if (dirty & FD_DIRTY_VIEWPORT) {
@@ -643,7 +643,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	}
 
 	if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
-		struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+		struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 		unsigned n = pfb->nr_cbufs;
 		/* if we have depth/stencil, we need at least on MRT: */
 		if (pfb->zsbuf)
@@ -663,7 +663,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 		for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 			enum pipe_format format = pipe_surface_format(
-					ctx->framebuffer.cbufs[i]);
+					ctx->batch->framebuffer.cbufs[i]);
 			bool is_int = util_format_is_pure_integer(format);
 			bool has_alpha = util_format_has_alpha(format);
 			uint32_t control = blend->rb_mrt[i].control;
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 524c35a18bd..afd37a88f43 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -132,10 +132,10 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 }
 
 static bool
-use_hw_binning(struct fd_context *ctx)
+use_hw_binning(struct fd_batch *batch)
 {
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 
 	/* this seems to be a hw bug.. but this hack fixes piglit fbo-maxsize: */
 	if ((pfb->width > 4096) && (pfb->height > 4096))
@@ -147,10 +147,10 @@ use_hw_binning(struct fd_context *ctx)
 /* transfer from gmem to system memory (ie. normal RAM) */
 
 static void
-emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
+emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
 		uint32_t base, struct pipe_surface *psurf)
 {
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct fd_ringbuffer *ring = batch->gmem;
 	struct fd_resource *rsc = fd_resource(psurf->texture);
 	enum pipe_format pformat = psurf->format;
 	struct fd_resource_slice *slice;
@@ -180,17 +180,18 @@ emit_gmem2mem_surf(struct fd_context *ctx, bool stencil,
 			A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 			A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
 
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+	fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 }
 
 static void
-fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 {
+	struct fd_context *ctx = batch->ctx;
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	struct fd_ringbuffer *ring = ctx->ring;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct fd_ringbuffer *ring = batch->gmem;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd4_emit emit = {
 			.debug = &ctx->debug,
 			.vtx = &fd4_ctx->solid_vbuf_state,
@@ -269,22 +270,22 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 	fd4_program_emit(ring, &emit, 0, NULL);
 	fd4_emit_vertex_bufs(ring, &emit);
 
-	if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+	if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
-		if (!rsc->stencil || (ctx->resolve & FD_BUFFER_DEPTH))
-			emit_gmem2mem_surf(ctx, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
-		if (rsc->stencil && (ctx->resolve & FD_BUFFER_STENCIL))
-			emit_gmem2mem_surf(ctx, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+		if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
+			emit_gmem2mem_surf(batch, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+		if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
+			emit_gmem2mem_surf(batch, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
 	}
 
-	if (ctx->resolve & FD_BUFFER_COLOR) {
+	if (batch->resolve & FD_BUFFER_COLOR) {
 		unsigned i;
 		for (i = 0; i < pfb->nr_cbufs; i++) {
 			if (!pfb->cbufs[i])
 				continue;
-			if (!(ctx->resolve & (PIPE_CLEAR_COLOR0 << i)))
+			if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 				continue;
-			emit_gmem2mem_surf(ctx, false, gmem->cbuf_base[i], pfb->cbufs[i]);
+			emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
 		}
 	}
 
@@ -298,10 +299,10 @@ fd4_emit_tile_gmem2mem(struct fd_context *ctx, struct fd_tile *tile)
 /* transfer from system memory to gmem */
 
 static void
-emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
+emit_mem2gmem_surf(struct fd_batch *batch, uint32_t *bases,
 		struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
 {
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct fd_ringbuffer *ring = batch->gmem;
 	struct pipe_surface *zsbufs[2];
 
 	emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
@@ -318,17 +319,18 @@ emit_mem2gmem_surf(struct fd_context *ctx, uint32_t *bases,
 
 	fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
 
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
+	fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 }
 
 static void
-fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 {
+	struct fd_context *ctx = batch->ctx;
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	struct fd_ringbuffer *ring = ctx->ring;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct fd_ringbuffer *ring = batch->gmem;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd4_emit emit = {
 			.debug = &ctx->debug,
 			.vtx = &fd4_ctx->blit_vbuf_state,
@@ -455,14 +457,14 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 	bin_w = gmem->bin_w;
 	bin_h = gmem->bin_h;
 
-	if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR)) {
+	if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
 		emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
 		emit.fp = NULL;      /* frag shader changed so clear cache */
 		fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
-		emit_mem2gmem_surf(ctx, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
+		emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
 	}
 
-	if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
+	if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 		switch (pfb->zsbuf->format) {
 		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 		case PIPE_FORMAT_Z32_FLOAT:
@@ -493,7 +495,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 		}
 		emit.fp = NULL;      /* frag shader changed so clear cache */
 		fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
-		emit_mem2gmem_surf(ctx, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
+		emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
 	}
 
 	OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
@@ -508,24 +510,24 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
 }
 
 static void
-patch_draws(struct fd_context *ctx, enum pc_di_vis_cull_mode vismode)
+patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
 {
 	unsigned i;
-	for (i = 0; i < fd_patch_num_elements(&ctx->draw_patches); i++) {
-		struct fd_cs_patch *patch = fd_patch_element(&ctx->draw_patches, i);
+	for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
+		struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
 		*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 	}
-	util_dynarray_resize(&ctx->draw_patches, 0);
+	util_dynarray_resize(&batch->draw_patches, 0);
 }
 
 /* for rendering directly to system memory: */
 static void
-fd4_emit_sysmem_prep(struct fd_context *ctx)
+fd4_emit_sysmem_prep(struct fd_batch *batch)
 {
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+	struct fd_ringbuffer *ring = batch->gmem;
 
-	fd4_emit_restore(ctx, ring);
+	fd4_emit_restore(batch->ctx, ring);
 
 	OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 	OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
@@ -552,14 +554,15 @@ fd4_emit_sysmem_prep(struct fd_context *ctx)
 	OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 	OUT_RING(ring, 0x8);
 
-	patch_draws(ctx, IGNORE_VISIBILITY);
+	patch_draws(batch, IGNORE_VISIBILITY);
 }
 
 static void
-update_vsc_pipe(struct fd_context *ctx)
+update_vsc_pipe(struct fd_batch *batch)
 {
+	struct fd_context *ctx = batch->ctx;
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct fd_ringbuffer *ring = batch->gmem;
 	int i;
 
 	OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
@@ -592,12 +595,12 @@ update_vsc_pipe(struct fd_context *ctx)
 }
 
 static void
-emit_binning_pass(struct fd_context *ctx)
+emit_binning_pass(struct fd_batch *batch)
 {
+	struct fd_context *ctx = batch->ctx;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	struct fd_batch *batch = ctx->batch;
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+	struct fd_ringbuffer *ring = batch->gmem;
 	int i;
 
 	uint32_t x1 = gmem->minx;
@@ -658,20 +661,20 @@ emit_binning_pass(struct fd_context *ctx)
 
 /* before first tile */
 static void
-fd4_emit_tile_init(struct fd_context *ctx)
+fd4_emit_tile_init(struct fd_batch *batch)
 {
-	struct fd_ringbuffer *ring = ctx->ring;
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	struct fd_ringbuffer *ring = batch->gmem;
+	struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 
-	fd4_emit_restore(ctx, ring);
+	fd4_emit_restore(batch->ctx, ring);
 
 	OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 	OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 			A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 
-	update_vsc_pipe(ctx);
+	update_vsc_pipe(batch);
 
-	if (use_hw_binning(ctx)) {
+	if (use_hw_binning(batch)) {
 		OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 		OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 				A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
@@ -682,11 +685,11 @@ fd4_emit_tile_init(struct fd_context *ctx)
 				0x8);
 
 		/* emit hw binning pass: */
-		emit_binning_pass(ctx);
+		emit_binning_pass(batch);
 
-		patch_draws(ctx, USE_VISIBILITY);
+		patch_draws(batch, USE_VISIBILITY);
 	} else {
-		patch_draws(ctx, IGNORE_VISIBILITY);
+		patch_draws(batch, IGNORE_VISIBILITY);
 	}
 
 	OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
@@ -697,10 +700,11 @@ fd4_emit_tile_init(struct fd_context *ctx)
 
 /* before mem2gmem */
 static void
-fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 {
-	struct fd_ringbuffer *ring = ctx->ring;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct fd_context *ctx = batch->ctx;
+	struct fd_ringbuffer *ring = batch->gmem;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
 
 	if (pfb->zsbuf) {
@@ -752,19 +756,20 @@ fd4_emit_tile_prep(struct fd_context *ctx, struct fd_tile *tile)
 
 /* before IB to rendering cmds: */
 static void
-fd4_emit_tile_renderprep(struct fd_context *ctx, struct fd_tile *tile)
+fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 {
+	struct fd_context *ctx = batch->ctx;
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
-	struct fd_ringbuffer *ring = ctx->ring;
+	struct fd_ringbuffer *ring = batch->gmem;
 	struct fd_gmem_stateobj *gmem = &ctx->gmem;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 
 	uint32_t x1 = tile->xoff;
 	uint32_t y1 = tile->yoff;
 	uint32_t x2 = tile->xoff + tile->bin_w - 1;
 	uint32_t y2 = tile->yoff + tile->bin_h - 1;
 
-	if (use_hw_binning(ctx)) {
+	if (use_hw_binning(batch)) {
 		struct fd_vsc_pipe *pipe = &ctx->pipe[tile->p];
 
 		assert(pipe->w * pipe->h);