freedreno: update generated headers

Signed-off-by: Rob Clark <[email protected]>

1 files changed, 20 insertions, 2 deletions

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 70c933877de..2f9f5876166 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-12-05 13:03:25)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90537 bytes, from 2016-11-29 17:10:44)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  92389 bytes, from 2016-12-06 22:06:14)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
 
 Copyright (C) 2013-2016 by the following authors:
@@ -929,12 +929,14 @@ static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT			0
 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
 }
 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK			0x00003f00
 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT			8
 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
 }
 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM			0x00010000
@@ -1019,6 +1021,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		14
 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
 {
+	assert(!(val & 0xf));
 	return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
 }
 
@@ -1218,6 +1221,7 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT		2
 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
 {
+	assert(!(val & 0x3));
 	return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
 }
 
@@ -1294,6 +1298,7 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14
 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
 {
+	assert(!(val & 0x3fff));
 	return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
 }
 
@@ -1302,6 +1307,7 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT			5
 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
 }
 
@@ -1310,6 +1316,7 @@ static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0
 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
 }
 
@@ -1388,6 +1395,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format va
 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12
 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 {
+	assert(!(val & 0xfff));
 	return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
 }
 
@@ -1396,6 +1404,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
 #define A4XX_RB_DEPTH_PITCH__SHIFT				0
 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
 }
 
@@ -1404,6 +1413,7 @@ static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
 #define A4XX_RB_DEPTH_PITCH2__SHIFT				0
 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
 }
 
@@ -1469,6 +1479,7 @@ static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		12
 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
 {
+	assert(!(val & 0xfff));
 	return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
 }
 
@@ -1477,6 +1488,7 @@ static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
 #define A4XX_RB_STENCIL_PITCH__SHIFT				0
 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
 }
 
@@ -2838,12 +2850,14 @@ static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0
 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
 }
 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0
 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT				5
 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
 }
 
@@ -3014,6 +3028,7 @@ static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x000022
 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT			4
 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
 {
+	assert(!(val & 0xf));
 	return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
 }
 
@@ -4020,6 +4035,7 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT				0
 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
 {
+	assert(!(val & 0xfff));
 	return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
 }
 #define A4XX_TEX_CONST_3_DEPTH__MASK				0x7ffc0000
@@ -4034,12 +4050,14 @@ static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT				0
 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
 {
+	assert(!(val & 0xfff));
 	return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
 }
 #define A4XX_TEX_CONST_4_BASE__MASK				0xffffffe0
 #define A4XX_TEX_CONST_4_BASE__SHIFT				5
 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
 {
+	assert(!(val & 0x1f));
 	return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
 }