freedreno: update generated headers

Signed-off-by: Rob Clark <[email protected]>

1 files changed, 203 insertions, 11 deletions

diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
index 0e80564d999..0f69205e054 100644
--- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
+++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14748 bytes, from 2015-04-12 15:01:13)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  66709 bytes, from 2015-04-12 18:16:35)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  57486 bytes, from 2015-04-12 18:10:00)
 
 Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <[email protected]> (robclark)
@@ -43,10 +43,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 enum a4xx_color_fmt {
 	RB4_A8_UNORM = 1,
+	RB4_R8_UNORM = 2,
+	RB4_R4G4B4A4_UNORM = 8,
+	RB4_R5G5B5A1_UNORM = 10,
 	RB4_R5G6R5_UNORM = 14,
-	RB4_Z16_UNORM = 15,
+	RB4_R8G8_UNORM = 15,
+	RB4_R8G8_SNORM = 16,
+	RB4_R8G8_UINT = 17,
+	RB4_R8G8_SINT = 18,
+	RB4_R16_FLOAT = 21,
+	RB4_R16_UINT = 22,
+	RB4_R16_SINT = 23,
 	RB4_R8G8B8_UNORM = 25,
 	RB4_R8G8B8A8_UNORM = 26,
+	RB4_R8G8B8A8_SNORM = 28,
+	RB4_R8G8B8A8_UINT = 29,
+	RB4_R8G8B8A8_SINT = 30,
+	RB4_R10G10B10A2_UNORM = 31,
+	RB4_R10G10B10A2_UINT = 34,
+	RB4_R11G11B10_FLOAT = 39,
+	RB4_R16G16_FLOAT = 42,
+	RB4_R16G16_UINT = 43,
+	RB4_R16G16_SINT = 44,
+	RB4_R32_FLOAT = 45,
+	RB4_R32_UINT = 46,
+	RB4_R32_SINT = 47,
+	RB4_R16G16B16A16_FLOAT = 54,
+	RB4_R16G16B16A16_UINT = 55,
+	RB4_R16G16B16A16_SINT = 56,
+	RB4_R32G32_FLOAT = 57,
+	RB4_R32G32_UINT = 58,
+	RB4_R32G32_SINT = 59,
+	RB4_R32G32B32A32_FLOAT = 60,
+	RB4_R32G32B32A32_UINT = 61,
+	RB4_R32G32B32A32_SINT = 62,
 };
 
 enum a4xx_tile_mode {
@@ -91,7 +121,14 @@ enum a4xx_vtx_fmt {
 	VFMT4_16_16_UNORM = 29,
 	VFMT4_16_16_16_UNORM = 30,
 	VFMT4_16_16_16_16_UNORM = 31,
+	VFMT4_32_UINT = 32,
+	VFMT4_32_32_UINT = 33,
+	VFMT4_32_32_32_UINT = 34,
+	VFMT4_32_32_32_32_UINT = 35,
+	VFMT4_32_SINT = 36,
 	VFMT4_32_32_SINT = 37,
+	VFMT4_32_32_32_SINT = 38,
+	VFMT4_32_32_32_32_SINT = 39,
 	VFMT4_8_UINT = 40,
 	VFMT4_8_8_UINT = 41,
 	VFMT4_8_8_8_UINT = 42,
@@ -125,12 +162,57 @@ enum a4xx_tex_fmt {
 	TFMT4_8_UNORM = 4,
 	TFMT4_8_8_UNORM = 14,
 	TFMT4_8_8_8_8_UNORM = 28,
+	TFMT4_8_8_SNORM = 15,
+	TFMT4_8_8_8_8_SNORM = 29,
+	TFMT4_8_8_UINT = 16,
+	TFMT4_8_8_8_8_UINT = 30,
+	TFMT4_8_8_SINT = 17,
+	TFMT4_8_8_8_8_SINT = 31,
+	TFMT4_16_UINT = 21,
+	TFMT4_16_16_UINT = 41,
+	TFMT4_16_16_16_16_UINT = 54,
+	TFMT4_16_SINT = 22,
+	TFMT4_16_16_SINT = 42,
+	TFMT4_16_16_16_16_SINT = 55,
+	TFMT4_32_UINT = 44,
+	TFMT4_32_32_UINT = 57,
+	TFMT4_32_32_32_32_UINT = 64,
+	TFMT4_32_SINT = 45,
+	TFMT4_32_32_SINT = 58,
+	TFMT4_32_32_32_32_SINT = 65,
 	TFMT4_16_FLOAT = 20,
 	TFMT4_16_16_FLOAT = 40,
 	TFMT4_16_16_16_16_FLOAT = 53,
 	TFMT4_32_FLOAT = 43,
 	TFMT4_32_32_FLOAT = 56,
 	TFMT4_32_32_32_32_FLOAT = 63,
+	TFMT4_9_9_9_E5_FLOAT = 32,
+	TFMT4_11_11_10_FLOAT = 37,
+	TFMT4_ATC_RGB = 100,
+	TFMT4_ATC_RGBA_EXPLICIT = 101,
+	TFMT4_ATC_RGBA_INTERPOLATED = 102,
+	TFMT4_ETC2_RG11_UNORM = 103,
+	TFMT4_ETC2_RG11_SNORM = 104,
+	TFMT4_ETC2_R11_UNORM = 105,
+	TFMT4_ETC2_R11_SNORM = 106,
+	TFMT4_ETC1 = 107,
+	TFMT4_ETC2_RGB8 = 108,
+	TFMT4_ETC2_RGBA8 = 109,
+	TFMT4_ETC2_RGB8A1 = 110,
+	TFMT4_ASTC_4x4 = 111,
+	TFMT4_ASTC_5x4 = 112,
+	TFMT4_ASTC_5x5 = 113,
+	TFMT4_ASTC_6x5 = 114,
+	TFMT4_ASTC_6x6 = 115,
+	TFMT4_ASTC_8x5 = 116,
+	TFMT4_ASTC_8x6 = 117,
+	TFMT4_ASTC_8x8 = 118,
+	TFMT4_ASTC_10x5 = 119,
+	TFMT4_ASTC_10x6 = 120,
+	TFMT4_ASTC_10x8 = 121,
+	TFMT4_ASTC_10x10 = 122,
+	TFMT4_ASTC_12x10 = 123,
+	TFMT4_ASTC_12x12 = 124,
 };
 
 enum a4xx_tex_fetchsize {
@@ -288,13 +370,16 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
 #define A4XX_RB_RENDER_CONTROL2_YCOORD				0x00000002
 #define A4XX_RB_RENDER_CONTROL2_ZCOORD				0x00000004
 #define A4XX_RB_RENDER_CONTROL2_WCOORD				0x00000008
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK			0x00000010
 #define A4XX_RB_RENDER_CONTROL2_FACENESS			0x00000020
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID			0x00000040
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK		0x00000380
 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT		7
 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
 {
 	return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
 }
+#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR			0x00000800
 #define A4XX_RB_RENDER_CONTROL2_VARYING				0x00001000
 
 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
@@ -337,6 +422,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
 {
 	return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
 }
+#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00002000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0x007fc000
 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		14
 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
@@ -464,7 +550,12 @@ static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare
 }
 
 #define REG_A4XX_RB_FS_OUTPUT					0x000020f9
-#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND				0x00000001
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK			0x000000ff
+#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT			0
+static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
+{
+	return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR				0x00000100
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK			0xffff0000
 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT			16
@@ -473,12 +564,54 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
 	return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
 }
 
-#define REG_A4XX_RB_RENDER_CONTROL3				0x000020fb
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK		0x0000001f
-#define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT		0
-static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val)
+#define REG_A4XX_RB_RENDER_COMPONENTS				0x000020fb
+#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
+#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
+#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT			4
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
+#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT			8
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
+#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT			12
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
+#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT			16
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
+#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT			20
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
+#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT			24
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
 {
-	return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK;
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
+}
+#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
+#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT			28
+static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
+{
+	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
 }
 
 #define REG_A4XX_RB_COPY_CONTROL				0x000020fc
@@ -562,7 +695,12 @@ static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
 }
 
 #define REG_A4XX_RB_FS_OUTPUT_REG				0x00002100
-#define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE			0x00000001
+#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK				0x0000000f
+#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT			0
+static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+	return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z			0x00000020
 
 #define REG_A4XX_RB_DEPTH_CONTROL				0x00002101
@@ -1029,6 +1167,9 @@ static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578
 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS			0x00080000
 
 #define REG_A4XX_SP_INSTR_CACHE_CTRL				0x000022c1
+#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER			0x00000080
+#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER			0x00000100
+#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER			0x00000400
 
 #define REG_A4XX_SP_VS_CTRL_REG0				0x000022c4
 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
@@ -1248,6 +1389,12 @@ static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 #define REG_A4XX_SP_FS_LENGTH_REG				0x000022ef
 
 #define REG_A4XX_SP_FS_OUTPUT_REG				0x000022f0
+#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK				0x0000000f
+#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
+{
+	return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
+}
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT		8
@@ -1255,6 +1402,12 @@ static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
 {
 	return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
 }
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK		0xff000000
+#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT		24
+static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+	return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
+}
 
 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
 
@@ -1315,6 +1468,12 @@ static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
 	return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
 }
 
+#define REG_A4XX_SP_GS_OBJ_START				0x0000235c
+
+#define REG_A4XX_SP_GS_PVT_MEM_PARAM				0x0000235d
+
+#define REG_A4XX_SP_GS_PVT_MEM_ADDR				0x0000235e
+
 #define REG_A4XX_SP_GS_LENGTH_REG				0x00002360
 
 #define REG_A4XX_VPC_DEBUG_RAM_SEL				0x00000e60
@@ -1699,6 +1858,14 @@ static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
 	return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
 }
 
+#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP			0x00002076
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK			0xffffffff
+#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT			0
+static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
+{
+	return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
+}
+
 #define REG_A4XX_GRAS_DEPTH_CONTROL				0x00002077
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK			0x00000003
 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT			0
@@ -1905,6 +2072,18 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
 {
 	return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
 }
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK		0x0003fc00
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT		10
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
+}
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK		0x03fc0000
+#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT		18
+static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
+{
+	return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
+}
 
 #define REG_A4XX_HLSQ_CONTROL_3_REG				0x000023c3
 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK			0x000000ff
@@ -2072,6 +2251,18 @@ static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
 #define REG_A4XX_PC_RESTART_INDEX				0x000021c6
 
 #define REG_A4XX_PC_GS_PARAM					0x000021e5
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK			0x000003ff
+#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT			0
+static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
+{
+	return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
+}
+#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK				0x01800000
+#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT			23
+static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
+{
+	return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
+}
 
 #define REG_A4XX_PC_HS_PARAM					0x000021e7
 
@@ -2219,6 +2410,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
 
 #define REG_A4XX_TEX_CONST_0					0x00000000
 #define A4XX_TEX_CONST_0_TILED					0x00000001
+#define A4XX_TEX_CONST_0_SRGB					0x00000004
 #define A4XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT				4
 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)