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authorRob Clark <[email protected]>2016-07-11 17:36:45 -0400
committerRob Clark <[email protected]>2016-07-30 09:23:42 -0400
commit7f8fd02dc7cad1ddcfb610db10ffbb41e3e34e7d (patch)
tree755aec6bfa8e4d9cb4614dd5a8b58e4b21a6b73d /src/gallium/drivers/freedreno/a3xx
parent10baf05b2caaa0900c71ac64c91301e953176516 (diff)
freedreno: re-order support for hw queries
Push query state down to batch, and use the resource tracking to figure out which batch(es) need to be flushed to get the query result. This means we actually need to allocate the prsc up front, before we know the size. So we have to add a special way to allocate an un- backed resource, and then later allocate the backing storage. Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/a3xx')
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_emit.c5
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_emit.h2
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_gmem.c4
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_query.c6
4 files changed, 9 insertions, 8 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index eef5b52f12c..7e83157e38e 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -757,8 +757,9 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
* state, there could have been a context switch between ioctls):
*/
void
-fd3_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
+fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
+ struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
int i;
@@ -894,7 +895,7 @@ fd3_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
fd_wfi(ctx, ring);
- fd_hw_query_enable(ctx, ring);
+ fd_hw_query_enable(batch, ring);
ctx->needs_rb_fbd = true;
}
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
index 110f30e89be..dfe77589542 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
@@ -93,7 +93,7 @@ void fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit);
void fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct fd3_emit *emit);
-void fd3_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring);
+void fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
void fd3_emit_init(struct pipe_context *pctx);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index b9af45683f9..1788c0c7384 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -734,7 +734,7 @@ fd3_emit_sysmem_prep(struct fd_batch *batch)
pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
}
- fd3_emit_restore(batch->ctx, ring);
+ fd3_emit_restore(batch, ring);
OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1);
OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
@@ -927,7 +927,7 @@ fd3_emit_tile_init(struct fd_batch *batch)
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
uint32_t rb_render_control;
- fd3_emit_restore(batch->ctx, ring);
+ fd3_emit_restore(batch, ring);
/* note: use gmem->bin_w/h, the bin_w/h parameters may be truncated
* at the right and bottom edge tiles
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_query.c b/src/gallium/drivers/freedreno/a3xx/fd3_query.c
index 8fc0a0d4229..ec034fc127d 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_query.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_query.c
@@ -46,10 +46,10 @@ struct fd_rb_samp_ctrs {
*/
static struct fd_hw_sample *
-occlusion_get_sample(struct fd_context *ctx, struct fd_ringbuffer *ring)
+occlusion_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
struct fd_hw_sample *samp =
- fd_hw_sample_init(ctx, sizeof(struct fd_rb_samp_ctrs));
+ fd_hw_sample_init(batch, sizeof(struct fd_rb_samp_ctrs));
/* Set RB_SAMPLE_COUNT_ADDR to samp->offset plus value of
* HW_QUERY_BASE_REG register:
@@ -68,7 +68,7 @@ occlusion_get_sample(struct fd_context *ctx, struct fd_ringbuffer *ring)
INDEX_SIZE_IGN, USE_VISIBILITY, 0));
OUT_RING(ring, 0); /* NumIndices */
- fd_event_write(ctx, ring, ZPASS_DONE);
+ fd_event_write(batch->ctx, ring, ZPASS_DONE);
OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1);
OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);