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authorJason Ekstrand <[email protected]>2019-05-06 11:45:46 -0500
committerJason Ekstrand <[email protected]>2019-05-24 08:38:11 -0500
commitf2dc0f28728af63e1a79756dab06a7035fecb590 (patch)
tree567ce89be4af1fc48d287415ab051929f0e1466e /src/gallium/drivers/freedreno/a2xx
parent22421ca7be608f38ce701a43e3f6b7f3132b7aab (diff)
nir: Drop imov/fmov in favor of one mov instruction
The difference between imov and fmov has been a constant source of confusion in NIR for years. No one really knows why we have two or when to use one vs. the other. The real reason is that they do different things in the presence of source and destination modifiers. However, without modifiers (which many back-ends don't have), they are identical. Now that we've reworked nir_lower_to_source_mods to leave one abs/neg instruction in place rather than replacing them with imov or fmov instructions, we don't need two different instructions at all anymore. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Acked-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers/freedreno/a2xx')
-rw-r--r--src/gallium/drivers/freedreno/a2xx/ir2_nir.c25
1 files changed, 11 insertions, 14 deletions
diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
index ddf93a637af..219ba75e59d 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
+++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
@@ -283,7 +283,7 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
} nir_ir2_opc[nir_num_opcodes+1] = {
[0 ... nir_num_opcodes - 1] = {-1, -1},
- [nir_op_fmov] = {MAXs, MAXv},
+ [nir_op_mov] = {MAXs, MAXv},
[nir_op_fsign] = {-1, CNDGTEv},
[nir_op_fnot] = {SETEs, SETEv},
[nir_op_for] = {MAXs, MAXv},
@@ -315,9 +315,6 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
[nir_op_fsin] = {SIN, -1},
/* no fsat, fneg, fabs since source mods deal with those */
- /* some nir passes still generate nir_op_imov */
- [nir_op_imov] = {MAXs, MAXv},
-
/* so we can use this function with non-nir op */
#define ir2_op_cube nir_num_opcodes
[ir2_op_cube] = {-1, CUBEv},
@@ -383,7 +380,7 @@ make_src_noconst(struct ir2_context *ctx, nir_src src)
if (nir_src_as_const_value(src)) {
assert(src.is_ssa);
- instr = instr_create_alu(ctx, nir_op_fmov, src.ssa->num_components);
+ instr = instr_create_alu(ctx, nir_op_mov, src.ssa->num_components);
instr->src[0] = make_src(ctx, src);
return ir2_src(instr->idx, 0, IR2_SRC_SSA);
}
@@ -509,24 +506,24 @@ load_input(struct ir2_context *ctx, nir_dest *dst, unsigned idx)
* TODO: only components that are required by fragment shader
*/
instr = instr_create_alu_reg(ctx,
- ctx->so->is_a20x ? nir_op_fadd : nir_op_fmov, 3, NULL);
+ ctx->so->is_a20x ? nir_op_fadd : nir_op_mov, 3, NULL);
instr->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
instr->src[0].abs = true;
/* on a20x, C64 contains the tile offset */
instr->src[1] = ir2_src(64, 0, IR2_SRC_CONST);
- instr = instr_create_alu_reg(ctx, nir_op_fmov, 4, instr);
+ instr = instr_create_alu_reg(ctx, nir_op_mov, 4, instr);
instr->src[0] = ir2_src(ctx->f->fragcoord, 0, IR2_SRC_INPUT);
instr = instr_create_alu_reg(ctx, nir_op_frcp, 8, instr);
instr->src[0] = ir2_src(ctx->f->fragcoord, IR2_SWIZZLE_Y, IR2_SRC_INPUT);
unsigned reg_idx = instr->reg - ctx->reg; /* XXX */
- instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+ instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
break;
default:
- instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+ instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
instr->src[0] = ir2_src(idx, 0, IR2_SRC_INPUT);
break;
}
@@ -576,7 +573,7 @@ store_output(struct ir2_context *ctx, nir_src src, unsigned slot, unsigned ncomp
return;
}
- instr = instr_create_alu(ctx, nir_op_fmov, ncomp);
+ instr = instr_create_alu(ctx, nir_op_mov, ncomp);
instr->src[0] = make_src(ctx, src);
instr->alu.export = idx;
}
@@ -600,7 +597,7 @@ emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
assert(const_offset); /* TODO can be false in ES2? */
idx = nir_intrinsic_base(intr);
idx += (uint32_t) nir_src_as_const_value(intr->src[0])[0].f32;
- instr = instr_create_alu_dest(ctx, nir_op_fmov, &intr->dest);
+ instr = instr_create_alu_dest(ctx, nir_op_mov, &intr->dest);
instr->src[0] = ir2_src(idx, 0, IR2_SRC_CONST);
break;
case nir_intrinsic_discard:
@@ -780,7 +777,7 @@ emit_undef(struct ir2_context *ctx, nir_ssa_undef_instr * undef)
struct ir2_instr *instr;
- instr = instr_create_alu_dest(ctx, nir_op_fmov,
+ instr = instr_create_alu_dest(ctx, nir_op_mov,
&(nir_dest) {.ssa = undef->def,.is_ssa = true});
instr->src[0] = ir2_src(0, 0, IR2_SRC_CONST);
}
@@ -843,11 +840,11 @@ extra_position_exports(struct ir2_context *ctx, bool binning)
/* fragcoord z/w */
if (ctx->f->fragcoord >= 0 && !binning) {
- instr = instr_create_alu(ctx, nir_op_fmov, 1);
+ instr = instr_create_alu(ctx, nir_op_mov, 1);
instr->src[0] = ir2_src(wincoord->idx, IR2_SWIZZLE_Z, IR2_SRC_SSA);
instr->alu.export = ctx->f->fragcoord;
- instr = instr_create_alu(ctx, nir_op_fmov, 1);
+ instr = instr_create_alu(ctx, nir_op_mov, 1);
instr->src[0] = ctx->position;
instr->src[0].swizzle = IR2_SWIZZLE_W;
instr->alu.export = ctx->f->fragcoord;