etnaviv: update headers from rnndb

Update to etna_viv commit 6c9c706.

Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Wladimir J. van der Laan <[email protected]>

5 files changed, 622 insertions, 89 deletions

diff --git a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
index f8d76b01058..e12188ea52c 100644
--- a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
+++ b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
@@ -8,9 +8,9 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- cmdstream.xml (  15289 bytes, from 2017-09-29 11:52:39)
-- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
-- common.xml    (  23529 bytes, from 2017-09-29 11:52:39)
+- cmdstream.xml (  16595 bytes, from 2017-10-05 21:20:32)
+- copyright.xml (   1597 bytes, from 2016-11-13 13:46:17)
+- common.xml    (  26135 bytes, from 2017-10-05 21:20:32)
 
 Copyright (C) 2012-2017 by the following authors:
 - Wladimir J. van der Laan <[email protected]>
@@ -52,6 +52,8 @@ DEALINGS IN THE SOFTWARE.
 #define FE_OPCODE_RETURN					0x0000000b
 #define FE_OPCODE_DRAW_INSTANCED				0x0000000c
 #define FE_OPCODE_CHIP_SELECT					0x0000000d
+#define FE_OPCODE_WAIT_FENCE					0x0000000f
+#define FE_OPCODE_SNAP_PAGES					0x00000013
 #define PRIMITIVE_TYPE_POINTS					0x00000001
 #define PRIMITIVE_TYPE_LINES					0x00000002
 #define PRIMITIVE_TYPE_LINE_STRIP				0x00000003
@@ -192,6 +194,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIV_FE_STALL_TOKEN_TO__MASK				0x00001f00
 #define VIV_FE_STALL_TOKEN_TO__SHIFT				8
 #define VIV_FE_STALL_TOKEN_TO(x)				(((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
+#define VIV_FE_STALL_TOKEN_UNK28__MASK				0x30000000
+#define VIV_FE_STALL_TOKEN_UNK28__SHIFT				28
+#define VIV_FE_STALL_TOKEN_UNK28(x)				(((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)
 
 #define VIV_FE_CALL						0x00000000
 
@@ -266,5 +271,30 @@ DEALINGS IN THE SOFTWARE.
 #define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT		0
 #define VIV_FE_DRAW_INSTANCED_START_INDEX(x)			(((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)
 
+#define VIV_FE_WAIT_FENCE					0x00000000
+
+#define VIV_FE_WAIT_FENCE_HEADER				0x00000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK			0xf8000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT			27
+#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE			0x78000000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK			0x00030000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT			16
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x)			(((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK		0x0000ffff
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT		0
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x)			(((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)
+
+#define VIV_FE_WAIT_FENCE_ADDRESS				0x00000004
+
+#define VIV_FE_SNAP_PAGES					0x00000000
+
+#define VIV_FE_SNAP_PAGES_HEADER				0x00000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK			0xf8000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT			27
+#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES			0x98000000
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK			0x0000001f
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT			0
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x)			(((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)
+
 
 #endif /* CMDSTREAM_XML */
diff --git a/src/gallium/drivers/etnaviv/hw/common.xml.h b/src/gallium/drivers/etnaviv/hw/common.xml.h
index 85c4990b61a..57369d741da 100644
--- a/src/gallium/drivers/etnaviv/hw/common.xml.h
+++ b/src/gallium/drivers/etnaviv/hw/common.xml.h
@@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state.xml     (  20229 bytes, from 2017-09-29 11:52:39)
-- common.xml    (  23529 bytes, from 2017-09-29 11:52:39)
-- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
-- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml  (  68429 bytes, from 2017-09-29 11:55:19)
-- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+- state.xml     (  26245 bytes, from 2017-10-05 21:32:06)
+- common.xml    (  26135 bytes, from 2017-10-05 21:20:32)
+- state_hi.xml  (  27733 bytes, from 2017-10-05 21:20:32)
+- copyright.xml (   1597 bytes, from 2016-11-13 13:46:17)
+- state_2d.xml  (  51552 bytes, from 2016-11-13 13:46:17)
+- state_3d.xml  (  80819 bytes, from 2017-10-05 21:20:32)
+- state_vg.xml  (   5975 bytes, from 2016-11-13 13:46:17)
 
 Copyright (C) 2012-2017 by the following authors:
 - Wladimir J. van der Laan <[email protected]>
@@ -49,12 +49,7 @@ DEALINGS IN THE SOFTWARE.
 #define SYNC_RECIPIENT_RA					0x00000005
 #define SYNC_RECIPIENT_PE					0x00000007
 #define SYNC_RECIPIENT_DE					0x0000000b
-#define SYNC_RECIPIENT_VG					0x0000000f
-#define SYNC_RECIPIENT_TESSELATOR				0x00000010
-#define SYNC_RECIPIENT_VG2					0x00000011
-#define SYNC_RECIPIENT_TESSELATOR2				0x00000012
-#define SYNC_RECIPIENT_VG3					0x00000013
-#define SYNC_RECIPIENT_TESSELATOR3				0x00000014
+#define SYNC_RECIPIENT_BLT					0x00000010
 #define ENDIAN_MODE_NO_SWAP					0x00000000
 #define ENDIAN_MODE_SWAP_16					0x00000001
 #define ENDIAN_MODE_SWAP_32					0x00000002
@@ -77,6 +72,7 @@ DEALINGS IN THE SOFTWARE.
 #define chipModel_GC800						0x00000800
 #define chipModel_GC860						0x00000860
 #define chipModel_GC880						0x00000880
+#define chipModel_GC900						0x00000900
 #define chipModel_GC1000					0x00001000
 #define chipModel_GC1500					0x00001500
 #define chipModel_GC2000					0x00002000
@@ -88,6 +84,12 @@ DEALINGS IN THE SOFTWARE.
 #define chipModel_GC5000					0x00005000
 #define chipModel_GC5200					0x00005200
 #define chipModel_GC6400					0x00006400
+#define chipModel_GC7000					0x00007000
+#define chipModel_GC7400					0x00007400
+#define chipModel_GC8000					0x00008000
+#define chipModel_GC8100					0x00008100
+#define chipModel_GC8200					0x00008200
+#define chipModel_GC8400					0x00008400
 #define RGBA_BITS_R						0x00000001
 #define RGBA_BITS_G						0x00000002
 #define RGBA_BITS_B						0x00000004
@@ -203,7 +205,7 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures2_RGB888				0x00001000
 #define chipMinorFeatures2_TX__YUV_ASSEMBLER			0x00002000
 #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING		0x00004000
-#define chipMinorFeatures2_EXTRA_TEXTURE_STATE			0x00008000
+#define chipMinorFeatures2_TX_FILTER				0x00008000
 #define chipMinorFeatures2_FULL_DIRECTFB			0x00010000
 #define chipMinorFeatures2_2D_TILING				0x00020000
 #define chipMinorFeatures2_THREAD_WALKER_IN_PS			0x00040000
@@ -242,36 +244,36 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures3_TX_ENHANCEMENTS1			0x00080000
 #define chipMinorFeatures3_SH_ENHANCEMENTS1			0x00100000
 #define chipMinorFeatures3_SH_ENHANCEMENTS2			0x00200000
-#define chipMinorFeatures3_UNK22				0x00400000
+#define chipMinorFeatures3_PE_ENHANCEMENTS1			0x00400000
 #define chipMinorFeatures3_2D_FC_SOURCE				0x00800000
-#define chipMinorFeatures3_UNK24				0x01000000
-#define chipMinorFeatures3_UNK25				0x02000000
+#define chipMinorFeatures3_BUG_FIXES_14				0x01000000
+#define chipMinorFeatures3_POWER_OPTIMIZATIONS_0		0x02000000
 #define chipMinorFeatures3_NEW_HZ				0x04000000
 #define chipMinorFeatures3_PE_DITHER_FIX			0x08000000
-#define chipMinorFeatures3_UNK28				0x10000000
+#define chipMinorFeatures3_DE_ENHANCEMENTS3			0x10000000
 #define chipMinorFeatures3_SH_ENHANCEMENTS3			0x20000000
-#define chipMinorFeatures3_UNK30				0x40000000
-#define chipMinorFeatures3_UNK31				0x80000000
-#define chipMinorFeatures4_UNK0					0x00000001
+#define chipMinorFeatures3_SH_ENHANCEMENTS4			0x40000000
+#define chipMinorFeatures3_TX_ENHANCEMENTS2			0x80000000
+#define chipMinorFeatures4_FE_ENHANCEMENTS1			0x00000001
 #define chipMinorFeatures4_PE_ENHANCEMENTS2			0x00000002
 #define chipMinorFeatures4_FRUSTUM_CLIP_FIX			0x00000004
-#define chipMinorFeatures4_UNK3					0x00000008
-#define chipMinorFeatures4_UNK4					0x00000010
+#define chipMinorFeatures4_DE_NO_GAMMA				0x00000008
+#define chipMinorFeatures4_PA_ENHANCEMENTS_2			0x00000010
 #define chipMinorFeatures4_2D_GAMMA				0x00000020
 #define chipMinorFeatures4_SINGLE_BUFFER			0x00000040
-#define chipMinorFeatures4_UNK7					0x00000080
-#define chipMinorFeatures4_UNK8					0x00000100
-#define chipMinorFeatures4_UNK9					0x00000200
-#define chipMinorFeatures4_UNK10				0x00000400
+#define chipMinorFeatures4_HI_ENHANCEMENTS_1			0x00000080
+#define chipMinorFeatures4_TX_ENHANCEMENTS_3			0x00000100
+#define chipMinorFeatures4_SH_ENHANCEMENTS_5			0x00000200
+#define chipMinorFeatures4_FE_ENHANCEMENTS_2			0x00000400
 #define chipMinorFeatures4_TX_LERP_PRECISION_FIX		0x00000800
 #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION		0x00001000
 #define chipMinorFeatures4_TEXTURE_ASTC				0x00002000
-#define chipMinorFeatures4_UNK14				0x00004000
-#define chipMinorFeatures4_UNK15				0x00008000
+#define chipMinorFeatures4_PE_ENHANCEMENTS_4			0x00004000
+#define chipMinorFeatures4_MC_ENHANCEMENTS_1			0x00008000
 #define chipMinorFeatures4_HALTI2				0x00010000
 #define chipMinorFeatures4_2D_MIRROR_EXTENSION			0x00020000
 #define chipMinorFeatures4_SMALL_MSAA				0x00040000
-#define chipMinorFeatures4_UNK19				0x00080000
+#define chipMinorFeatures4_BUG_FIXES_17				0x00080000
 #define chipMinorFeatures4_NEW_RA				0x00100000
 #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT			0x00200000
 #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2		0x00400000
@@ -280,41 +282,46 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures4_BUG_FIXES18				0x02000000
 #define chipMinorFeatures4_2D_COMPRESSION			0x04000000
 #define chipMinorFeatures4_PROBE				0x08000000
-#define chipMinorFeatures4_UNK28				0x10000000
+#define chipMinorFeatures4_MEDIUM_PRECISION			0x10000000
 #define chipMinorFeatures4_2D_SUPER_TILE_VERSION		0x20000000
-#define chipMinorFeatures4_UNK30				0x40000000
-#define chipMinorFeatures4_UNK31				0x80000000
-#define chipMinorFeatures5_UNK0					0x00000001
-#define chipMinorFeatures5_UNK1					0x00000002
-#define chipMinorFeatures5_UNK2					0x00000004
-#define chipMinorFeatures5_UNK3					0x00000008
+#define chipMinorFeatures4_BUG_FIXES19				0x40000000
+#define chipMinorFeatures4_SH_ENHANCEMENTS6			0x80000000
+#define chipMinorFeatures5_SH_ENHANCEMENTS7			0x00000001
+#define chipMinorFeatures5_BUG_FIXES20				0x00000002
+#define chipMinorFeatures5_DE_ADDRESS_40			0x00000004
+#define chipMinorFeatures5_MINI_MMU_FIX				0x00000008
 #define chipMinorFeatures5_EEZ					0x00000010
-#define chipMinorFeatures5_UNK5					0x00000020
-#define chipMinorFeatures5_UNK6					0x00000040
-#define chipMinorFeatures5_UNK7					0x00000080
-#define chipMinorFeatures5_UNK8					0x00000100
+#define chipMinorFeatures5_BUG_FIXES21				0x00000020
+#define chipMinorFeatures5_EXTRA_VG_CAPS			0x00000040
+#define chipMinorFeatures5_MULTI_SRC_V15			0x00000080
+#define chipMinorFeatures5_BUG_FIXES22				0x00000100
 #define chipMinorFeatures5_HALTI3				0x00000200
-#define chipMinorFeatures5_UNK10				0x00000400
+#define chipMinorFeatures5_TESSELATION_SHADERS			0x00000400
 #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP		0x00000800
-#define chipMinorFeatures5_UNK12				0x00001000
+#define chipMinorFeatures5_MULTI_SRC_V2_STR_QUAD		0x00001000
 #define chipMinorFeatures5_SEPARATE_SRC_DST			0x00002000
 #define chipMinorFeatures5_HALTI4				0x00004000
-#define chipMinorFeatures5_UNK15				0x00008000
+#define chipMinorFeatures5_RA_WRITE_DEPTH			0x00008000
 #define chipMinorFeatures5_ANDROID_ONLY				0x00010000
 #define chipMinorFeatures5_HAS_PRODUCTID			0x00020000
-#define chipMinorFeatures5_UNK18				0x00040000
-#define chipMinorFeatures5_UNK19				0x00080000
+#define chipMinorFeatures5_TX_SUPPORT_DEC			0x00040000
+#define chipMinorFeatures5_S8_MSAA_COMPRESSION			0x00080000
 #define chipMinorFeatures5_PE_DITHER_FIX2			0x00100000
-#define chipMinorFeatures5_UNK21				0x00200000
-#define chipMinorFeatures5_UNK22				0x00400000
-#define chipMinorFeatures5_UNK23				0x00800000
-#define chipMinorFeatures5_UNK24				0x01000000
-#define chipMinorFeatures5_UNK25				0x02000000
-#define chipMinorFeatures5_UNK26				0x04000000
+#define chipMinorFeatures5_L2_CACHE_REMOVE			0x00200000
+#define chipMinorFeatures5_FE_ALLOW_RND_VTX_CNT			0x00400000
+#define chipMinorFeatures5_CUBE_MAP_FL28			0x00800000
+#define chipMinorFeatures5_TX_6BIT_FRAC				0x01000000
+#define chipMinorFeatures5_FE_ALLOW_STALL_PREFETCH_ENG		0x02000000
+#define chipMinorFeatures5_THIRD_PARTY_COMPRESSION		0x04000000
 #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT	0x08000000
 #define chipMinorFeatures5_V2_MSAA_COMP_FIX			0x10000000
-#define chipMinorFeatures5_UNK29				0x20000000
-#define chipMinorFeatures5_UNK30				0x40000000
-#define chipMinorFeatures5_UNK31				0x80000000
+#define chipMinorFeatures5_HALTI5				0x20000000
+#define chipMinorFeatures5_EVIS					0x40000000
+#define chipMinorFeatures5_BLT_ENGINE				0x80000000
+#define chipMinorFeatures6_BUG_FIXES_23				0x00000001
+#define chipMinorFeatures6_BUG_FIXES_24				0x00000002
+#define chipMinorFeatures6_DEC					0x00000004
+#define chipMinorFeatures6_VS_TILE_NV12				0x00000008
+#define chipMinorFeatures6_VS_TILE_NV12_10BIT			0x00000010
 
 #endif /* COMMON_XML */
diff --git a/src/gallium/drivers/etnaviv/hw/isa.xml.h b/src/gallium/drivers/etnaviv/hw/isa.xml.h
index 35a050e2156..f89ab0a0aeb 100644
--- a/src/gallium/drivers/etnaviv/hw/isa.xml.h
+++ b/src/gallium/drivers/etnaviv/hw/isa.xml.h
@@ -8,8 +8,8 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- isa.xml       (  34708 bytes, from 2017-09-29 11:52:39)
-- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
+- isa.xml       (  35432 bytes, from 2017-10-05 21:20:32)
+- copyright.xml (   1597 bytes, from 2016-11-13 13:46:17)
 
 Copyright (C) 2012-2017 by the following authors:
 - Wladimir J. van der Laan <[email protected]>
diff --git a/src/gallium/drivers/etnaviv/hw/state.xml.h b/src/gallium/drivers/etnaviv/hw/state.xml.h
index bd82218a3d7..729d0ee08f0 100644
--- a/src/gallium/drivers/etnaviv/hw/state.xml.h
+++ b/src/gallium/drivers/etnaviv/hw/state.xml.h
@@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state.xml     (  20229 bytes, from 2017-09-29 11:52:39)
-- common.xml    (  23529 bytes, from 2017-09-29 11:52:39)
-- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
-- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml  (  68429 bytes, from 2017-09-29 11:55:19)
-- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+- state.xml     (  26245 bytes, from 2017-10-05 21:32:06)
+- common.xml    (  26135 bytes, from 2017-10-05 21:20:32)
+- state_hi.xml  (  27733 bytes, from 2017-10-05 21:20:32)
+- copyright.xml (   1597 bytes, from 2016-11-13 13:46:17)
+- state_2d.xml  (  51552 bytes, from 2016-11-13 13:46:17)
+- state_3d.xml  (  80819 bytes, from 2017-10-05 21:20:32)
+- state_vg.xml  (   5975 bytes, from 2016-11-13 13:46:17)
 
 Copyright (C) 2012-2017 by the following authors:
 - Wladimir J. van der Laan <[email protected]>
@@ -192,17 +192,40 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0)		       (0x000006a0 + 0x4*(i0))
 
-#define VIVS_FE_UNK00700(i0)				       (0x00000700 + 0x4*(i0))
-#define VIVS_FE_UNK00700__ESIZE					0x00000004
-#define VIVS_FE_UNK00700__LEN					0x00000010
+#define VIVS_FE_GENERIC_ATTRIB(i0)			       (0x00000000 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB__ESIZE				0x00000004
+#define VIVS_FE_GENERIC_ATTRIB__LEN				0x00000010
 
-#define VIVS_FE_UNK00740(i0)				       (0x00000740 + 0x4*(i0))
-#define VIVS_FE_UNK00740__ESIZE					0x00000004
-#define VIVS_FE_UNK00740__LEN					0x00000010
+#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0)		       (0x000006c0 + 0x4*(i0))
 
-#define VIVS_FE_UNK00780(i0)				       (0x00000780 + 0x4*(i0))
-#define VIVS_FE_UNK00780__ESIZE					0x00000004
-#define VIVS_FE_UNK00780__LEN					0x00000010
+#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0)		       (0x00000700 + 0x4*(i0))
+
+#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0)		       (0x00000740 + 0x4*(i0))
+
+#define VIVS_FE_GENERIC_ATTRIB_UNK00780(i0)		       (0x00000780 + 0x4*(i0))
+
+#define VIVS_FE_HALTI5_UNK007C4					0x000007c4
+
+#define VIVS_FE_HALTI5_UNK007D0(i0)			       (0x000007d0 + 0x4*(i0))
+#define VIVS_FE_HALTI5_UNK007D0__ESIZE				0x00000004
+#define VIVS_FE_HALTI5_UNK007D0__LEN				0x00000002
+
+#define VIVS_FE_HALTI5_UNK007D8					0x000007d8
+
+#define VIVS_FE_DESC_START					0x000007dc
+
+#define VIVS_FE_DESC_END					0x000007e0
+
+#define VIVS_FE_DESC_AVAIL					0x000007e4
+#define VIVS_FE_DESC_AVAIL_COUNT__MASK				0x0000007f
+#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT				0
+#define VIVS_FE_DESC_AVAIL_COUNT(x)				(((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
+
+#define VIVS_FE_FENCE_WAIT_DATA_LOW				0x000007e8
+
+#define VIVS_FE_FENCE_WAIT_DATA_HIGH				0x000007f4
+
+#define VIVS_FE_ROBUSTNESS_UNK007F8				0x000007f8
 
 #define VIVS_GL							0x00000000
 
@@ -228,6 +251,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK			0x00001f00
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT			8
 #define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK			0x30000000
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT			28
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x)			(((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
 
 #define VIVS_GL_FLUSH_CACHE					0x0000380c
 #define VIVS_GL_FLUSH_CACHE_DEPTH				0x00000001
@@ -237,6 +263,10 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS				0x00000010
 #define VIVS_GL_FLUSH_CACHE_SHADER_L1				0x00000020
 #define VIVS_GL_FLUSH_CACHE_SHADER_L2				0x00000040
+#define VIVS_GL_FLUSH_CACHE_UNK10				0x00000400
+#define VIVS_GL_FLUSH_CACHE_UNK11				0x00000800
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12			0x00001000
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13			0x00002000
 
 #define VIVS_GL_FLUSH_MMU					0x00003810
 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU				0x00000001
@@ -298,6 +328,8 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT		28
 #define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK)
 
+#define VIVS_GL_OCCLUSION_QUERY_ADDR				0x00003824
+
 #define VIVS_GL_VARYING_COMPONENT_USE(i0)		       (0x00003828 + 0x4*(i0))
 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE			0x00000004
 #define VIVS_GL_VARYING_COMPONENT_USE__LEN			0x00000002
@@ -350,6 +382,10 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT		30
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
 
+#define VIVS_GL_UNK0382C					0x0000382c
+
+#define VIVS_GL_OCCLUSION_QUERY_CONTROL				0x00003830
+
 #define VIVS_GL_UNK03834					0x00003834
 
 #define VIVS_GL_UNK03838					0x00003838
@@ -363,8 +399,44 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_GL_UNK03854					0x00003854
 
+#define VIVS_GL_BUG_FIXES					0x00003860
+
+#define VIVS_GL_FENCE_OUT_ADDRESS				0x00003868
+
+#define VIVS_GL_FENCE_OUT_DATA_LOW				0x0000386c
+
+#define VIVS_GL_HALTI5_UNK03884					0x00003884
+
+#define VIVS_GL_HALTI5_UNK03888					0x00003888
+
+#define VIVS_GL_GS_UNK0388C					0x0000388c
+
+#define VIVS_GL_FENCE_OUT_DATA_HIGH				0x00003898
+
+#define VIVS_GL_SHADER_INDEX					0x0000389c
+
+#define VIVS_GL_GS_UNK038A0(i0)				       (0x000038a0 + 0x4*(i0))
+#define VIVS_GL_GS_UNK038A0__ESIZE				0x00000004
+#define VIVS_GL_GS_UNK038A0__LEN				0x00000008
+
+#define VIVS_GL_HALTI5_UNK038C0(i0)			       (0x000038c0 + 0x4*(i0))
+#define VIVS_GL_HALTI5_UNK038C0__ESIZE				0x00000004
+#define VIVS_GL_HALTI5_UNK038C0__LEN				0x00000010
+
+#define VIVS_GL_SECURITY_UNK3900				0x00003900
+
+#define VIVS_GL_SECURITY_UNK3904				0x00003904
+
 #define VIVS_GL_UNK03A00					0x00003a00
 
+#define VIVS_GL_UNK03A04					0x00003a04
+
+#define VIVS_GL_UNK03A08					0x00003a08
+
+#define VIVS_GL_UNK03A0C					0x00003a0c
+
+#define VIVS_GL_UNK03A10					0x00003a10
+
 #define VIVS_GL_STALL_TOKEN					0x00003c00
 #define VIVS_GL_STALL_TOKEN_FROM__MASK				0x0000001f
 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT				0
@@ -387,6 +459,99 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0)		       (0x00014680 + 0x4*(i0))
 
+#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0)	       (0x000146c0 + 0x4*(i0))
+
+#define VIVS_NFE_HALTI5_UNK17800(i0)			       (0x00017800 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17800__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17800__LEN				0x00000020
+
+#define VIVS_NFE_HALTI5_UNK17880(i0)			       (0x00017880 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17880__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17880__LEN				0x00000020
+
+#define VIVS_NFE_HALTI5_UNK17900(i0)			       (0x00017900 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17900__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17900__LEN				0x00000020
+
+#define VIVS_NFE_HALTI5_UNK17980(i0)			       (0x00017980 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17980__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17980__LEN				0x00000020
+
+#define VIVS_NFE_HALTI5_UNK17A00(i0)			       (0x00017a00 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17A00__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17A00__LEN				0x00000020
+
+#define VIVS_NFE_HALTI5_UNK17A80(i0)			       (0x00017a80 + 0x4*(i0))
+#define VIVS_NFE_HALTI5_UNK17A80__ESIZE				0x00000004
+#define VIVS_NFE_HALTI5_UNK17A80__LEN				0x00000020
+
+#define VIVS_BLT						0x00000000
+
+#define VIVS_BLT_UNK14000					0x00014000
+
+#define VIVS_BLT_UNK14008					0x00014008
+
+#define VIVS_BLT_UNK1400C					0x0001400c
+
+#define VIVS_BLT_UNK14010					0x00014010
+
+#define VIVS_BLT_UNK14014					0x00014014
+
+#define VIVS_BLT_UNK14018					0x00014018
+
+#define VIVS_BLT_UNK14020					0x00014020
+
+#define VIVS_BLT_UNK14024					0x00014024
+
+#define VIVS_BLT_UNK14028					0x00014028
+
+#define VIVS_BLT_UNK1402C					0x0001402c
+
+#define VIVS_BLT_UNK14030					0x00014030
+
+#define VIVS_BLT_UNK14034					0x00014034
+
+#define VIVS_BLT_UNK14038					0x00014038
+
+#define VIVS_BLT_UNK1403C					0x0001403c
+
+#define VIVS_BLT_UNK14040					0x00014040
+
+#define VIVS_BLT_UNK14044					0x00014044
+
+#define VIVS_BLT_UNK14048					0x00014048
+
+#define VIVS_BLT_UNK1404C					0x0001404c
+
+#define VIVS_BLT_UNK14050					0x00014050
+
+#define VIVS_BLT_UNK14054					0x00014054
+
+#define VIVS_BLT_UNK14058					0x00014058
+
+#define VIVS_BLT_UNK1405C					0x0001405c
+
+#define VIVS_BLT_UNK14060					0x00014060
+
+#define VIVS_BLT_UNK14064					0x00014064
+
+#define VIVS_BLT_UNK1409C					0x0001409c
+
+#define VIVS_BLT_UNK140A0					0x000140a0
+
+#define VIVS_BLT_FENCE_OUT_ADDRESS				0x000140a4
+
+#define VIVS_BLT_FENCE_OUT_DATA_LOW				0x000140a8
+
+#define VIVS_BLT_UNK140AC					0x000140ac
+
+#define VIVS_BLT_FENCE_OUT_DATA_HIGH				0x000140b4
+
+#define VIVS_BLT_ENABLE						0x000140b8
+#define VIVS_BLT_ENABLE_ENABLE					0x00000001
+
+#define VIVS_BLT_UNK140BC					0x000140bc
+
 #define VIVS_DUMMY						0x00000000
 
 #define VIVS_DUMMY_DUMMY					0x0003fffc
diff --git a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
index b025117c0da..9084e643d3c 100644
--- a/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
+++ b/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
@@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state.xml     (  20229 bytes, from 2017-09-29 11:52:39)
-- common.xml    (  23529 bytes, from 2017-09-29 11:52:39)
-- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
-- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml  (  68429 bytes, from 2017-09-29 11:55:19)
-- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+- state.xml     (  26245 bytes, from 2017-10-05 21:32:06)
+- common.xml    (  26135 bytes, from 2017-10-05 21:20:32)
+- state_hi.xml  (  27733 bytes, from 2017-10-05 21:20:32)
+- copyright.xml (   1597 bytes, from 2016-11-13 13:46:17)
+- state_2d.xml  (  51552 bytes, from 2016-11-13 13:46:17)
+- state_3d.xml  (  80819 bytes, from 2017-10-05 21:20:32)
+- state_vg.xml  (   5975 bytes, from 2016-11-13 13:46:17)
 
 Copyright (C) 2012-2017 by the following authors:
 - Wladimir J. van der Laan <[email protected]>
@@ -102,6 +102,7 @@ DEALINGS IN THE SOFTWARE.
 #define RS_FORMAT_B10G11R11F					0x0000001d
 #define RS_FORMAT_A2B10G10R10UI					0x0000001e
 #define RS_FORMAT_G8R8						0x0000001f
+#define RS_FORMAT_R8						0x00000023
 #define TEXTURE_FORMAT_NONE					0x00000000
 #define TEXTURE_FORMAT_A8					0x00000001
 #define TEXTURE_FORMAT_L8					0x00000002
@@ -294,6 +295,49 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_VS_INST_ADDR					0x0000086c
 
+#define VIVS_VS_HALTI5_UNK00870					0x00000870
+
+#define VIVS_VS_HALTI5_UNK00874					0x00000874
+
+#define VIVS_VS_HALTI5_UNK00878					0x00000878
+
+#define VIVS_VS_HALTI5_UNK0087C					0x0000087c
+
+#define VIVS_VS_HALTI5_UNK00880					0x00000880
+
+#define VIVS_VS_HALTI1_UNK00884					0x00000884
+
+#define VIVS_VS_UNK0088C					0x0000088c
+
+#define VIVS_VS_ICACHE_UNK00890					0x00000890
+
+#define VIVS_VS_HALTI5_UNK00898(i0)			       (0x00000898 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK00898__ESIZE				0x00000004
+#define VIVS_VS_HALTI5_UNK00898__LEN				0x00000002
+
+#define VIVS_VS_HALTI5_UNK008A0					0x000008a0
+
+#define VIVS_VS_HALTI5_UNK008A8					0x000008a8
+
+#define VIVS_VS_ICACHE_INVALIDATE				0x000008b0
+#define VIVS_VS_ICACHE_INVALIDATE_UNK0				0x00000001
+#define VIVS_VS_ICACHE_INVALIDATE_UNK1				0x00000002
+#define VIVS_VS_ICACHE_INVALIDATE_UNK2				0x00000004
+#define VIVS_VS_ICACHE_INVALIDATE_UNK3				0x00000008
+#define VIVS_VS_ICACHE_INVALIDATE_UNK4				0x00000010
+
+#define VIVS_VS_HALTI5_UNK008B8					0x000008b8
+
+#define VIVS_VS_HALTI5_UNK008BC					0x000008bc
+
+#define VIVS_VS_HALTI5_UNK008C0(i0)			       (0x000008c0 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK008C0__ESIZE				0x00000004
+#define VIVS_VS_HALTI5_UNK008C0__LEN				0x00000008
+
+#define VIVS_VS_HALTI5_UNK008E0(i0)			       (0x000008e0 + 0x4*(i0))
+#define VIVS_VS_HALTI5_UNK008E0__ESIZE				0x00000004
+#define VIVS_VS_HALTI5_UNK008E0__LEN				0x00000008
+
 #define VIVS_VS_INST_MEM(i0)				       (0x00004000 + 0x4*(i0))
 #define VIVS_VS_INST_MEM__ESIZE					0x00000004
 #define VIVS_VS_INST_MEM__LEN					0x00000400
@@ -302,6 +346,10 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_VS_UNIFORMS__ESIZE					0x00000004
 #define VIVS_VS_UNIFORMS__LEN					0x00000400
 
+#define VIVS_VS_HALTI5_UNK15600					0x00015600
+
+#define VIVS_VS_HALTI5_UNK15604					0x00015604
+
 #define VIVS_CL							0x00000000
 
 #define VIVS_CL_CONFIG						0x00000900
@@ -393,6 +441,12 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_CL_UNK00954					0x00000954
 
+#define VIVS_CL_HALTI5_UNK00958					0x00000958
+
+#define VIVS_CL_HALTI5_UNK0095C					0x0000095c
+
+#define VIVS_CL_HALTI5_UNK00960					0x00000960
+
 #define VIVS_PA							0x00000000
 
 #define VIVS_PA_VIEWPORT_SCALE_X				0x00000a00
@@ -411,6 +465,8 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_PA_POINT_SIZE					0x00000a1c
 
+#define VIVS_PA_UNK00A24					0x00000a24
+
 #define VIVS_PA_SYSTEM_MODE					0x00000a28
 #define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST		0x00000001
 #define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER			0x00000010
@@ -475,6 +531,12 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_PA_ZFARCLIPPING					0x00000a8c
 
+#define VIVS_PA_HALTI5_UNK00A90(i0)			       (0x00000a90 + 0x4*(i0))
+#define VIVS_PA_HALTI5_UNK00A90__ESIZE				0x00000004
+#define VIVS_PA_HALTI5_UNK00A90__LEN				0x00000004
+
+#define VIVS_PA_HALTI5_UNK00AA8					0x00000aa8
+
 #define VIVS_SE							0x00000000
 
 #define VIVS_SE_SCISSOR_LEFT					0x00000c00
@@ -520,6 +582,10 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT			12
 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x)			(((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK)
 
+#define VIVS_RA_UNK00E24					0x00000e24
+
+#define VIVS_RA_HALTI5_UNK00E34					0x00000e34
+
 #define VIVS_RA_CENTROID_TABLE(i0)			       (0x00000e40 + 0x4*(i0))
 #define VIVS_RA_CENTROID_TABLE__ESIZE				0x00000004
 #define VIVS_RA_CENTROID_TABLE__LEN				0x00000010
@@ -563,11 +629,41 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_PS_INST_ADDR					0x00001028
 
+#define VIVS_PS_UNK0102C					0x0000102c
+
 #define VIVS_PS_CONTROL_EXT					0x00001030
 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK		0x00000003
 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT		0
 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT(x)		(((x) << VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT) & VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK)
 
+#define VIVS_PS_UNK01034					0x00001034
+
+#define VIVS_PS_UNK01038					0x00001038
+
+#define VIVS_PS_HALTI3_UNK0103C					0x0000103c
+
+#define VIVS_PS_UNK01040(i0)				       (0x00001040 + 0x4*(i0))
+#define VIVS_PS_UNK01040__ESIZE					0x00000004
+#define VIVS_PS_UNK01040__LEN					0x00000002
+
+#define VIVS_PS_UNK01048					0x00001048
+
+#define VIVS_PS_ICACHE_UNK0104C					0x0000104c
+
+#define VIVS_PS_HALTI4_UNK01054					0x00001054
+
+#define VIVS_PS_HALTI5_UNK01058					0x00001058
+
+#define VIVS_PS_HALTI5_UNK01080(i0)			       (0x00001080 + 0x4*(i0))
+#define VIVS_PS_HALTI5_UNK01080__ESIZE				0x00000004
+#define VIVS_PS_HALTI5_UNK01080__LEN				0x00000004
+
+#define VIVS_PS_HALTI5_UNK01090					0x00001090
+
+#define VIVS_PS_HALTI5_UNK01094					0x00001094
+
+#define VIVS_PS_HALTI5_UNK01098					0x00001098
+
 #define VIVS_PS_INST_MEM(i0)				       (0x00006000 + 0x4*(i0))
 #define VIVS_PS_INST_MEM__ESIZE					0x00000004
 #define VIVS_PS_INST_MEM__LEN					0x00000400
@@ -576,6 +672,122 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_PS_UNIFORMS__ESIZE					0x00000004
 #define VIVS_PS_UNIFORMS__LEN					0x00000400
 
+#define VIVS_GS							0x00000000
+
+#define VIVS_GS_UNK01100					0x00001100
+
+#define VIVS_GS_UNK01104					0x00001104
+
+#define VIVS_GS_UNK01108					0x00001108
+
+#define VIVS_GS_UNK0110C					0x0000110c
+
+#define VIVS_GS_UNK01110					0x00001110
+
+#define VIVS_GS_UNK01114					0x00001114
+
+#define VIVS_GS_UNK0111C					0x0000111c
+
+#define VIVS_GS_UNK01120(i0)				       (0x00001120 + 0x4*(i0))
+#define VIVS_GS_UNK01120__ESIZE					0x00000004
+#define VIVS_GS_UNK01120__LEN					0x00000008
+
+#define VIVS_GS_UNK01140					0x00001140
+
+#define VIVS_GS_UNK01144					0x00001144
+
+#define VIVS_GS_UNK01148					0x00001148
+
+#define VIVS_GS_UNK0114C					0x0000114c
+
+#define VIVS_GS_UNK01154					0x00001154
+
+#define VIVS_TCS						0x00000000
+
+#define VIVS_TCS_UNK007C0					0x000007c0
+
+#define VIVS_TCS_UNK14A00					0x00014a00
+
+#define VIVS_TCS_UNK14A04					0x00014a04
+
+#define VIVS_TCS_UNK14A08					0x00014a08
+
+#define VIVS_TCS_UNK14A10					0x00014a10
+
+#define VIVS_TCS_UNK14A14					0x00014a14
+
+#define VIVS_TCS_UNK14A18					0x00014a18
+
+#define VIVS_TCS_UNK14A1C					0x00014a1c
+
+#define VIVS_TCS_UNK14A20(i0)				       (0x00014a20 + 0x4*(i0))
+#define VIVS_TCS_UNK14A20__ESIZE				0x00000004
+#define VIVS_TCS_UNK14A20__LEN					0x00000008
+
+#define VIVS_TCS_UNK14A40					0x00014a40
+
+#define VIVS_TCS_UNK14A44					0x00014a44
+
+#define VIVS_TCS_UNK14A4C					0x00014a4c
+
+#define VIVS_TES						0x00000000
+
+#define VIVS_TES_UNK14B00					0x00014b00
+
+#define VIVS_TES_UNK14B04					0x00014b04
+
+#define VIVS_TES_UNK14B08					0x00014b08
+
+#define VIVS_TES_UNK14B0C					0x00014b0c
+
+#define VIVS_TES_UNK14B14					0x00014b14
+
+#define VIVS_TES_UNK14B18					0x00014b18
+
+#define VIVS_TES_UNK14B1C					0x00014b1c
+
+#define VIVS_TES_UNK14B20					0x00014b20
+
+#define VIVS_TES_UNK14B24					0x00014b24
+
+#define VIVS_TES_UNK14B2C					0x00014b2c
+
+#define VIVS_TES_UNK14B34					0x00014b34
+
+#define VIVS_TES_UNK14B40(i0)				       (0x00014b40 + 0x4*(i0))
+#define VIVS_TES_UNK14B40__ESIZE				0x00000004
+#define VIVS_TES_UNK14B40__LEN					0x00000008
+
+#define VIVS_TFB						0x00000000
+
+#define VIVS_TFB_UNK1C000					0x0001c000
+
+#define VIVS_TFB_UNK1C008					0x0001c008
+
+#define VIVS_TFB_FLUSH						0x0001c00c
+
+#define VIVS_TFB_UNK1C014					0x0001c014
+
+#define VIVS_TFB_UNK1C040(i0)				       (0x0001c040 + 0x4*(i0))
+#define VIVS_TFB_UNK1C040__ESIZE				0x00000004
+#define VIVS_TFB_UNK1C040__LEN					0x00000004
+
+#define VIVS_TFB_UNK1C080(i0)				       (0x0001c080 + 0x4*(i0))
+#define VIVS_TFB_UNK1C080__ESIZE				0x00000004
+#define VIVS_TFB_UNK1C080__LEN					0x00000004
+
+#define VIVS_TFB_UNK1C0C0(i0)				       (0x0001c0c0 + 0x4*(i0))
+#define VIVS_TFB_UNK1C0C0__ESIZE				0x00000004
+#define VIVS_TFB_UNK1C0C0__LEN					0x00000004
+
+#define VIVS_TFB_UNK1C100(i0)				       (0x0001c100 + 0x4*(i0))
+#define VIVS_TFB_UNK1C100__ESIZE				0x00000004
+#define VIVS_TFB_UNK1C100__LEN					0x00000004
+
+#define VIVS_TFB_UNK1C800(i0)				       (0x0001c800 + 0x4*(i0))
+#define VIVS_TFB_UNK1C800__ESIZE				0x00000004
+#define VIVS_TFB_UNK1C800__LEN					0x00000200
+
 #define VIVS_PE							0x00000000
 
 #define VIVS_PE_DEPTH_CONFIG					0x00001400
@@ -740,7 +952,7 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK			0x00020000
 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED			0x00100000
 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK			0x00200000
-#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK			0x3f000000
+#define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK			0x7f000000
 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT			24
 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x)			(((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK)
 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK			0x80000000
@@ -772,6 +984,8 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_PE_PIPE_ADDR_UNK01520(i0)			       (0x00001520 + 0x4*(i0))
 
+#define VIVS_PE_PIPE_ADDR_UNK01540(i0)			       (0x00001540 + 0x4*(i0))
+
 #define VIVS_PE_STENCIL_CONFIG_EXT				0x000014a0
 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK		0x000000ff
 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT		0
@@ -801,6 +1015,8 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_PE_LOGIC_OP_UNK24__SHIFT				24
 #define VIVS_PE_LOGIC_OP_UNK24(x)				(((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK)
 #define VIVS_PE_LOGIC_OP_UNK24_MASK				0x08000000
+#define VIVS_PE_LOGIC_OP_UNK31_MASK				0x40000000
+#define VIVS_PE_LOGIC_OP_UNK31					0x80000000
 
 #define VIVS_PE_DITHER(i0)				       (0x000014a8 + 0x4*(i0))
 #define VIVS_PE_DITHER__ESIZE					0x00000004
@@ -830,6 +1046,12 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT	8
 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK)
 
+#define VIVS_PE_HALTI3_UNK014BC					0x000014bc
+
+#define VIVS_PE_HALTI4_UNK014C0					0x000014c0
+
+#define VIVS_PE_ROBUSTNESS_UNK014C4				0x000014c4
+
 #define VIVS_PE_UNK01580(i0)				       (0x00001580 + 0x4*(i0))
 #define VIVS_PE_UNK01580__ESIZE					0x00000004
 #define VIVS_PE_UNK01580__LEN					0x00000003
@@ -852,6 +1074,30 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_PE_RT_CONFIG_UNK16__SHIFT				16
 #define VIVS_PE_RT_CONFIG_UNK16(x)				(((x) << VIVS_PE_RT_CONFIG_UNK16__SHIFT) & VIVS_PE_RT_CONFIG_UNK16__MASK)
 
+#define VIVS_PE_HALTI5_UNK14920(i0)			       (0x00014920 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14920__ESIZE				0x00000004
+#define VIVS_PE_HALTI5_UNK14920__LEN				0x00000007
+
+#define VIVS_PE_HALTI5_UNK14940(i0)			       (0x00014940 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14940__ESIZE				0x00000004
+#define VIVS_PE_HALTI5_UNK14940__LEN				0x00000007
+
+#define VIVS_PE_HALTI5_UNK14960(i0)			       (0x00014960 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14960__ESIZE				0x00000004
+#define VIVS_PE_HALTI5_UNK14960__LEN				0x00000007
+
+#define VIVS_PE_HALTI5_UNK14980(i0)			       (0x00014980 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK14980__ESIZE				0x00000004
+#define VIVS_PE_HALTI5_UNK14980__LEN				0x00000007
+
+#define VIVS_PE_HALTI5_UNK149A0(i0)			       (0x000149a0 + 0x4*(i0))
+#define VIVS_PE_HALTI5_UNK149A0__ESIZE				0x00000004
+#define VIVS_PE_HALTI5_UNK149A0__LEN				0x00000007
+
+#define VIVS_PE_ROBUSTNESS_UNK149C0(i0)			       (0x000149c0 + 0x4*(i0))
+#define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE			0x00000004
+#define VIVS_PE_ROBUSTNESS_UNK149C0__LEN			0x00000008
+
 #define VIVS_CO							0x00000000
 
 #define VIVS_CO_UNK03008					0x00003008
@@ -876,6 +1122,8 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_CO_UNK03048					0x00003048
 
+#define VIVS_CO_ICACHE_UNK0304C					0x0000304c
+
 #define VIVS_CO_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
 #define VIVS_CO_SAMPLER__ESIZE					0x00000004
 #define VIVS_CO_SAMPLER__LEN					0x00000008
@@ -1032,6 +1280,8 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8			0x00000400
 #define VIVS_TS_MEM_CONFIG_UNK12				0x00001000
 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE			0x00002000
+#define VIVS_TS_MEM_CONFIG_UNK14				0x00004000
+#define VIVS_TS_MEM_CONFIG_UNK21				0x00200000
 
 #define VIVS_TS_COLOR_STATUS_BASE				0x00001658
 
@@ -1068,6 +1318,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK			0x000000f0
 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT			4
 #define VIVS_TS_SAMPLER_CONFIG_FORMAT(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
+#define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK			0x00003800
+#define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT			11
+#define VIVS_TS_SAMPLER_CONFIG_UNK11(x)				(((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK)
 
 #define VIVS_TS_SAMPLER_STATUS_BASE(i0)			       (0x00001740 + 0x4*(i0))
 
@@ -1075,6 +1328,8 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0)		       (0x00001780 + 0x4*(i0))
 
+#define VIVS_TS_SAMPLER_SURFACE_BASE(i0)		       (0x00001a80 + 0x4*(i0))
+
 #define VIVS_TS_RT(i0)					       (0x00000000 + 0x4*(i0))
 #define VIVS_TS_RT__ESIZE					0x00000004
 #define VIVS_TS_RT__LEN						0x00000008
@@ -1210,6 +1465,7 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK			0x00700000
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
 #define VIVS_TE_SAMPLER_CONFIG1_UNK25				0x02000000
 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
@@ -1223,9 +1479,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE				0x00000040
 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN				0x0000000e
 
-#define VIVS_TE_SAMPLER_UNK02C00(i0, i1)		       (0x00002c00 + 0x4*(i0) + 0x40*(i1))
-#define VIVS_TE_SAMPLER_UNK02C00__ESIZE				0x00000040
-#define VIVS_TE_SAMPLER_UNK02C00__LEN				0x0000000e
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1)		       (0x00002c00 + 0x4*(i0) + 0x40*(i1))
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE			0x00000040
+#define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN			0x0000000e
 
 #define VIVS_NTE						0x00000000
 
@@ -1315,6 +1571,7 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK		0x00700000
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
 #define VIVS_NTE_SAMPLER_CONFIG1_UNK25				0x02000000
 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
@@ -1324,9 +1581,31 @@ DEALINGS IN THE SOFTWARE.
 
 #define VIVS_NTE_SAMPLER_UNK10480(i0)			       (0x00010480 + 0x4*(i0))
 
-#define VIVS_NTE_SAMPLER_UNK10500(i0)			       (0x00010500 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_ASTC_UNK10500(i0)		       (0x00010500 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ASTC_UNK10580(i0)		       (0x00010580 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ASTC_UNK10600(i0)		       (0x00010600 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ASTC_UNK10680(i0)		       (0x00010600 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_BASELOD(i0)			       (0x00010700 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_UNK10780(i0)			       (0x00010780 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0)		       (0x00011000 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0)		       (0x00011080 + 0x4*(i0))
 
-#define VIVS_NTE_SAMPLER_UNK10700(i0)			       (0x00010700 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0)		       (0x00011100 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0)		       (0x00011180 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0)		       (0x00011200 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0)		       (0x00011280 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0)		       (0x00011300 + 0x4*(i0))
 
 #define VIVS_NTE_SAMPLER_ADDR(i0)			       (0x00010800 + 0x40*(i0))
 #define VIVS_NTE_SAMPLER_ADDR__ESIZE				0x00000040
@@ -1344,6 +1623,50 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_NTE_UNK12400__ESIZE				0x00000004
 #define VIVS_NTE_UNK12400__LEN					0x00000100
 
+#define VIVS_NTE_HALTI3_UNK14C00(i0)			       (0x00014c00 + 0x4*(i0))
+#define VIVS_NTE_HALTI3_UNK14C00__ESIZE				0x00000004
+#define VIVS_NTE_HALTI3_UNK14C00__LEN				0x00000010
+
+#define VIVS_NTE_DESCRIPTOR_UNK14C40				0x00014c40
+
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE				0x00014c48
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK		0x000001ff
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT		0
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x)			(((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK)
+#define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29			0x20000000
+
+#define VIVS_NTE_DESCRIPTOR(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_NTE_DESCRIPTOR__ESIZE				0x00000004
+#define VIVS_NTE_DESCRIPTOR__LEN				0x00000080
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK15C00(i0)		       (0x00015800 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK15E00(i0)		       (0x00015a00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK15C00(i0)		       (0x00015c00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK15E00(i0)		       (0x00015e00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK16C00(i0)		       (0x00016000 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK16E00(i0)		       (0x00016200 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17000(i0)		       (0x00016400 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17200(i0)		       (0x00016600 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_MIRROR_UNK17400(i0)		       (0x00016800 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK16C00(i0)		       (0x00016c00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK16E00(i0)		       (0x00016e00 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK17000(i0)		       (0x00017000 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK17200(i0)		       (0x00017200 + 0x4*(i0))
+
+#define VIVS_NTE_DESCRIPTOR_UNK17400(i0)		       (0x00017400 + 0x4*(i0))
+
 #define VIVS_SH							0x00000000
 
 #define VIVS_SH_UNK20000(i0)				       (0x00020000 + 0x4*(i0))
@@ -1362,5 +1685,13 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_SH_UNIFORMS__ESIZE					0x00000004
 #define VIVS_SH_UNIFORMS__LEN					0x00000800
 
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0)		       (0x00034000 + 0x4*(i0))
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE			0x00000004
+#define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN			0x00000800
+
+#define VIVS_SH_HALTI5_UNIFORMS(i0)			       (0x00036000 + 0x4*(i0))
+#define VIVS_SH_HALTI5_UNIFORMS__ESIZE				0x00000004
+#define VIVS_SH_HALTI5_UNIFORMS__LEN				0x00000800
+
 
 #endif /* STATE_3D_XML */