etnaviv: GC7000: Factor out RS blit functionality

Prepare for BLT-based blitting path by moving RS-based
blitting to the RS implementation file, making this
self-contained.

Signed-off-by: Wladimir J. van der Laan <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>

1 files changed, 0 insertions, 79 deletions

diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c
index 5ec9f167483..508c7b1b6ab 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -91,85 +91,6 @@ etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
 #define EMIT_STATE_RELOC(state_name, src_value) \
    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 
-/* submit RS state, without any processing and no dependence on context
- * except TS if this is a source-to-destination blit. */
-void
-etna_submit_rs_state(struct etna_context *ctx,
-                     const struct compiled_rs_state *cs)
-{
-   struct etna_screen *screen = etna_screen(ctx->base.screen);
-   struct etna_cmd_stream *stream = ctx->stream;
-   struct etna_coalesce coalesce;
-
-   if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
-      /* Inplace resolve is no-op if TS is not configured */
-      return;
-
-   ctx->stats.rs_operations++;
-
-   if (cs->RS_KICKER_INPLACE) {
-      etna_cmd_stream_reserve(stream, 6);
-      etna_coalesce_start(stream, &coalesce);
-      /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
-      /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
-      /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
-      etna_coalesce_end(stream, &coalesce);
-   } else if (screen->specs.pixel_pipes == 1) {
-      etna_cmd_stream_reserve(stream, 22);
-      etna_coalesce_start(stream, &coalesce);
-      /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
-      /* 2   */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]);
-      /* 3   */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
-      /* 4   */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]);
-      /* 5   */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
-      /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
-      /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
-      /*10   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
-      /*11 - pad */
-      /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
-      /*14   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
-      /*15   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
-      /*16   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
-      /*17   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
-      /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
-      /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
-      etna_coalesce_end(stream, &coalesce);
-   } else if (screen->specs.pixel_pipes == 2) {
-      etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
-      etna_coalesce_start(stream, &coalesce);
-      /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
-      /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
-      /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
-      /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs->source[0]);
-      if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI) {
-         /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs->source[1]);
-         /*9 - pad */
-      }
-      /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs->dest[0]);
-      if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI) {
-         /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs->dest[1]);
-         /*13 - pad */
-      }
-      /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs->RS_PIPE_OFFSET[0]);
-      /*16   */ EMIT_STATE(RS_PIPE_OFFSET(1), cs->RS_PIPE_OFFSET[1]);
-      /*17 - pad */
-      /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
-      /*20/21*/ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
-      /*22   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
-      /*23 - pad */
-      /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
-      /*26   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
-      /*27   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
-      /*28   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
-      /*29   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
-      /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
-      /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
-      etna_coalesce_end(stream, &coalesce);
-   } else {
-      abort();
-   }
-}
-
 /* Create bit field that specifies which samplers are active and thus need to be
  * programmed
  * 32 bits is enough for 32 samplers. As far as I know this is the upper bound