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author | Francisco Jerez <[email protected]> | 2012-04-30 20:21:38 +0200 |
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committer | Francisco Jerez <[email protected]> | 2012-05-11 12:39:41 +0200 |
commit | 9e550c34237898385c07af2cbb2da76670ed994e (patch) | |
tree | 88ed61d838762ab6e4b1e81667fe6cf41e1dfb39 /src/gallium/docs | |
parent | 581ddbcf93ea8111e71ef43e90fa6937cf46a2cb (diff) |
gallium/tgsi: Add support for barriers.
Diffstat (limited to 'src/gallium/docs')
-rw-r--r-- | src/gallium/docs/source/tgsi.rst | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index f32aff1c7b3..20611cb3788 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -1514,6 +1514,55 @@ Resource Access Opcodes ignored. +.. _threadsyncopcodes: + +Inter-thread synchronization opcodes +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +These opcodes are intended for communication between threads running +within the same compute grid. For now they're only valid in compute +programs. + +.. opcode:: MFENCE - Memory fence + + Syntax: ``MFENCE resource`` + + Example: ``MFENCE RES[0]`` + + This opcode forces strong ordering between any memory access + operations that affect the specified resource. This means that + previous loads and stores (and only those) will be performed and + visible to other threads before the program execution continues. + + +.. opcode:: LFENCE - Load memory fence + + Syntax: ``LFENCE resource`` + + Example: ``LFENCE RES[0]`` + + Similar to MFENCE, but it only affects the ordering of memory loads. + + +.. opcode:: SFENCE - Store memory fence + + Syntax: ``SFENCE resource`` + + Example: ``SFENCE RES[0]`` + + Similar to MFENCE, but it only affects the ordering of memory stores. + + +.. opcode:: BARRIER - Thread group barrier + + ``BARRIER`` + + This opcode suspends the execution of the current thread until all + the remaining threads in the working group reach the same point of + the program. Results are unspecified if any of the remaining + threads terminates or never reaches an executed BARRIER instruction. + + Explanation of symbols used ------------------------------ |